EECE144 logic design

EECE144, Fall 2014 Quiz 4 Project

5-bit Arithmetic Logic Unit (ALU) Objective:

 Reinforce understanding of combinational logic design and the design process.

 Practice combining models in Verilog to create complex designs.

Overview

In this project you will write and simulate a Verilog program that implements the 5-bit ALU

shown in Figure 1. The ALU will perform the operations listed in the table below.

A

B

OUT

C V

ALU

5'b

5'b

5'b

3'b

Select

Figure 1

Procedure:

1. Design the ALU shown in Figure 1, use any components you need (refer to figure 1 for inputs and outputs). The ALU should work as indicated in the table above (if select is 000 the output should be A, if select is 001, output should be B, etc).

2. Use Logisim to implement your design and simulate it.

3. Using Verilogger (or any other Verilog simulator) create a top model to implement the ALU. Describe the ALU using behavioral modeling. You can modify and use any of the modules you have created in lab 6 and Lab 7 to aid in your design. You can simply add the Verilog files to your design and instantiate the required components.

4. Create a test module to simulate your code. Your test bench should include all 8 functions.

Select (3 bits) Function Output

000 Pass A A

001 Pass B B

010 Addition A + B

011 Invert A A’

100 Invert B B’

101 AND A & B

110 OR A | B

111 XOR A ^ B

5. You have to demonstrate your results to your TA to be signed off. You will be asked questions about your code during demonstration.

Deliverables

1. Use the Lab Report Template as the basis for your lab report.

2. Include the Logisim diagram.

3. Submit all Verilog source files.

4. Include a snapshot of your simulation result.

5. The lab report is due by 11:59PM on December 11 (Hard Deadline).

Note: This is not a team project. Each student should submit

his/her own work. You should develop your own code; all

duplicates will receive no credit for this assignment.