computer help "Quartes"

LAB_1: Full Adder

(Due 10/30/2014 at 1:00 PM)

Part_1

Write a dataflow-style Verilog module corresponding to the full-adder circuit functionality

in Figure 1 (shown below).

In order to test the functionality of your code, you are required to write a test-bench (as

demonstrated in the previous class meeting).

Figure 1

Q1)

Is the schematic synthesized from your Verilog code similar to the one shown in Fig.1?

Does it match your partner’s design? Explain.

Part_2

Using the Full adder module designed in part 1, design a 16-bit Ripple adder along the

lines of Figure 2 (shown below)

In order to test the functionality of your code, you are required to write a test-bench (as

demonstrated in the previous class meeting).

Figure 2

Q2)

Is the schematic synthesized from your Verilog code similar to the one shown in Fig.1?

Does it match your partner’s design? Explain.

Note: You need to submit the working code, schematics, simulation waveforms as a

single attachment by the end of the lab (today). The full report is due at the beginning of

the next class meeting.

Please follow the Lab report guidelines posted on Moodle.