SPICE Asignment

Full N ame ____________________________________ Student ID ____________________________ A. Szeto - EE430 - Fall‘14

______ 100

SPIC E # 1 - DESIG N IN G A DIFFEREN TIA L B JT A M PLIFIER (D ue Friday, O ct. 17 at 10A M . Penalty = 10% per calendar day late. C opying an old report is cheating!!)th

D esign a differential amplifier performance specifications:

-- Achieve a single-ended D M gain of 40 to 50 and a single-ended CM mode gain of |0.05| or less. O perating environment: AC

1 2s Sig1signal source (v ) has R = 2kÙ and is applied to the left input transistor (Q ). T he other input transistor (Q ) has its base

Sig2 s Sig2 Lgrounded via a 2kÙ resistor (R ). T he differential amplifier is floating (i.e., only v , R & R are connected to ground).

2L -- D rive a 150 kÙ grounded load (R ) that’s connected at the collector of Q .

in Sig1 Sig2 -- Achieve a differential AC input resistance, R , (including R and R ) that’s greater than 30 kÙ .

D esign C onstraints:

[1] U se the customized 2N 2222 bipolar transistor found in B lackboard or modify the 2N2222 found in PSPICE Lite but must

Achange this transistor to have a forward â = 175 and V = 180V as follows: place that transistor onto your schematic, highlight the symbol and change its BF and VAF as needed and then save under another name. D o same for all your transistors.

CC[2] U se no resistors larger than 20 kÙ or smaller than 20 Ù . U se no capacitors. U se symmetrical power supplies, V = ±9 V .

CC[3] N o ideal current sources allowed. B uild actual current sources using 2N 2222 transistors and resistors tied either to +V or -

CCV . [Hint: Study Example 8.4 and Fig.2.15 for setting up your ac input sources.]. CAN N OT specify resistors to > 2 digits.

SU B M IT T H E FO LLO W IN G IN TH IS O RD ER FO R G RAD IN G : Staple all the sheets together so that your SPICE printout can be viewed without being dismantled. U se this assignment sheet as your cover page. For hand analyses, treat your final design like a H W

BEonproblem, e.g., do not use to your SPICE results. Instead assume all transistors are forward active with V = 0.7V and â = 175.

C[a] D ESIG N RAT IO N AL (M U ST B E TY PED ): In 1-2 pages, describe your circuit and your design approach (choice of R , bias

CQI & current mirror?). Include the schematic of your amplifier with the final component values and names shown. (20 points)

in vdm vcm[b] SPICE AN ALY SIS: Activate SPICE’s .TF option to determine your amp's D C values for R , A , and A . O btain B ode magnitude (in dB ) and phase plots (in log scale 100 H z to 10 M H z) of your DM and CM gains and clearly mark their -3dB and +3dB frequencies (see Fig. 9.35). Include in your report the com plete SPICE printout (“*.out” in PSPICE & “error log” in LT

i_CM id SigSpice) from your CM gain simulation only. For CM , use v of Fig. 2.15 with v set to zero. Include both R . (15 pts)

[H ints: T o have SPICE directly determine your circuit’s input resistance, output resistance, and voltage gain, you’ll need to insert the transfer function analysis command (.T F) and designate the output node and input source (highlight node & press Shift ‘N ’ to name it). If using O rC A D ’s PSPIC E, just activate .O P, .AC, and .T F commands and designate the input node as ‘V _inputsource’ and the output node as ‘V (output node).’ For your ground, pick the symbol called “0 source” in the source library.]

BEon[c] D C H AN D AN ALY SIS: Analyze your final circuit (as simulated by SPICE) by assuming that V = 0.7V only. U se N O

REF C CESPICE results here. Instead calculate by hand I , and the I and V of all the transistors in your final circuit. (15 pts.)

[d] AC H AN D AN ALY SIS: Continue analyzing your final circuit using the hand results from step [c] (not SPICE values).

in S vdmCalculate the differential input resistance (R ) seen by v , the differential single-ended gain (A ) and the common-mode

vcm Sig1 Sig2 Asingle-ended gain (A ). Do not forget R and R in your calculations. N eatly show all your work and use â = 175 and V = 180V in your hand calculations. (20 pts.)

[e] SU M M ARY T AB LE: Fill in the table below and explain any discrepancies that exceed ±10% . Y ou must analytically verify your explanations for full credit! [Hint: see Step 8 on backside] (15 points)

[f] O V ERALL Q U ALIT Y: Low power dissipation (<110 mW ), an efficient design (i.e., minimum number of resistors & transistors), no internal ground node, good CM RR, neatness and report organization, CM RR > 58 dB . (15 points)

CI of Input

B JT #1

CI of Input

BJT #2

C I of B ias

B JT #3

CI of B ias

B JT #4

D M Band- width

D ifferential

inR with

sigR = 2kÙ

Single-ended

vcmA with

SigR = 2kÙ

Single-ended

vdmA with

SigR = 2kÙ

Hand Calculations N /A

SPICE Results

Percent discrepancy (Explain on another page if > 10% .)

N /A N /A

SU G G ESTED D ESIG N PR O C ED U R E

Step 1 -- Carefully determine your design goals and constraints. Review Section 8.3.4 & 8.3.5 of the textbook on differential amplifiers. Study Example 8.4 and Fig. 8.15 & 8.18 and decide which circuit could meet your design

id vdgoals (required R and A ).

id vdStep 2 -- U se the corresponding equations for R and A to estimate the values of the collector resistances and the quiescent currents required. [H int: the collector bias current will strongly affect your differential amp’s input

idresistance, R .]

Step 3 -- B efore doing endless SPICE simulations, check if your

id vdcircuit satisfies the required R and A using the appropriate equations. If your hand calculations shows promise, then verify your design using SPICE. M odify circuit component values as necessary or try the other differential amplifier initially examined in Step 1. It’s a good idea to name your key nodes rather than accepting SPICE’s “weird” default node names.

Step 4 -- D etermine the most appropriate type of current mirror to give you the quiescent current needed from Step 2. D esign the current mirror (see sections 7.3.4 & 7.5.5 of textbook) after selecting a reasonable value (0.5-1.5

REFmA) for your master bias current (I ). [H int: T o reduce CM gain and increase CM RR, use a current

omirror with a larger output resistance (R ).]

o oStep 5 -- Calculate the output resistance (R ) of the current mirror biasing the diff amp and use R to determine your single-ended

vCMcommon mode voltage gain (A ). [H int: D raw and analyze via the CM half circuit approach.]. M odify or choose a

odifferent type of current mirror if the output resistance (R ) of the mirror biasing the diff amp gives you a CM gain that’s too

. vCMlarge U sually you’d want A as small as possible. If your design’s CM RR is inadequate, try using a current mirror that

ohas a larger output resistance (R ), either a W idlar, W ilson, or cascode mirror.

Step 6 -- Iterate between Steps 1-5 to fine tune your design. Compare your hand calculations with SPICE simulations. T hey should readily agree to within 10% . Study Fig. 2.15 & 8.27 for connecting your ac signal sources.

Step 7 -- After finalizing your design, obtain the required SPICE outputs and annotate your plots profusely. D escribe using good English the design procedures and key equations used. N ow treat your finalized differential amplifier like a homework problem and calculate its D C bias currents, ac gains, and input resistance and put your hand calculated answers in the table above.

Step 8 -- Analyze discrepancies greater than 10% between the hand analysis of your FIN AL CIRCU IT and SPICE's results. [H int: Are values for ac â used by SPICE the same as the nominal â of 175 used in your hand calculations? Look in the .O P portion of your output file.]

W H A T IF Y O U R SPICE SIM U LA TIO N B O M B S O R PRO D U C ES W EIRD R ESU LTS?

(O nly PSPICE or LT Spice M AY be used for your SPICE assignments. Download the appropriate tutorial from B lackboard)

Step A -- Check all your D C node voltages (SPICE's Small Signal Bias) to determine the status of all transistors. T o check if they are properly biased, check the SPICE's O perating Point Information and find the and D C junction voltages and currents of all the transistors. Are any are in saturation or cut-off? R emember, excessively low or high quiescent currents cause â to be small (deviate significantly from its nominal value of 175).

Step B -- Check for circuit description errors. Are the D C power supplies and the ac sources okay? Are all your components connected (no unconnected wires)? For transistors biased below 0 V D C, their substrate nodes must be connected to the negative supply. SPICE's default for the 4th transistor node is ground.

Step C -- Check for exponent errors in the circuit description and transistor models. Avoid using letter abbreviations for units unless you are sure. N ote: m = M = 1E-3 (milli-) and M EG = 1E6 (mega-). Check for mix-ups between the letter O and the number zero. Similarly check for mix-ups between the letter "l" and the number "1."

Step D – For other possible problems, download and carefully read the handout on “O vercom ing SPICE Sim ulation Bugs” available on Blackboard. For reference materials on using LT SPICE or PSPICE, download tutorials as needed from B lackboard.