lab report

Lab 12 – Latches and Flip-Flops

Mugisha Omary

Lab 12 – Latches and Flip-Flops

Laboratory Report for EENG 3302

College of Engineering and Computer Science

Department of Electrical Engineering

University of Texas at Tyler

Houston, Texas

December 10, 2013

Mugisha Omary

Group Members

Jonathan Vidana

Hamza Ahmad

Shamir Mohammed

Abstract

The purpose of this experiment is to be able to understand how latches operate and their similarities and differences to flip-flops by using NAND gates.

I. Project description

The latch is a digital memory circuit that can remain in the state in which it was set even after the input signals are removed. Latches are basically similar to flip-flops because they are bi-stable devices that can reside in either of two states by virtue of a feedback arrangement, in which the outputs are connected back to the opposite inputs. The main difference between latches and flip-flops is in the method used for changing their state. Latches are level-triggered and flip-flops are edge-triggered.

After completion of this experiment, we will be able to understand the operation of laches and similarities and differences to flip-flops.

II. Theoretical background

When the clock is high the input D propogates to the output Q as it is and when the clock is low the output is held(irrespective of the changes in input D).This definition indicates that D latch can be implemented as a multiplexer with clock signal as the select input of multiplexer. Applying analogy , we realise that when clock=1 the input to the CMOS pass transistor should be D and when clock=0 the input to the pass transistor should be value of D just before the transition of clock from 1 to 0.To obtain the value of D just before transition a buffer is needed.The final design is given below:

Figure 1-D latch

In digital systems, the types of circuits that can retain previous input levels after original inputs are removed are called sequential circuits.

The set-reset (S-R) latch has two input, a SET input and a RESET input, and two outputs, Q and Q. When the Q output is a 1, the latch is SET; when the Q output is a 0, the latch is RESET.

When an active-LOW input is applied to the SET input, the latch goes to the SET (Q = 1) condition and remains that way until an active-LOW signal is applied to the RESET input. Then it goes to the RESET (Q = 0) condition.

An invalid condition occurs if active-LOW inputs are applied at the same time to both the SET and the RESET inputs. During the time both the inputs are active, the Q output is 1 and the  output is a 1 (clearly an invalid condition). When both inputs go HIGH (inactive), the S-R latch stays latched in one state or the other. However, the exact state is not easily predictable. The final state of the latch depends on which input was active last as two inputs went to the inactive state.

Many applications require that the latch be enabled or gated by another source, called a clock. A gated S-R latch does not accept the input condition until the gate input is HIGH, and the required transitions will take place.

Figure 2- A gated S-R latch

The gated D-latch has one data input and a clock input. The addition of the inverter causes the RESET input to be the opposite the SET input. If a 1 is present on the D input and the clock is HIGH (gate enabled), then the latch is SET. If a 0 is present on the D input while the clock is HIGH, then the latch will be RESET. While the clock is HIGH, the outputs can change if the inputs change. Once the clock goes LOW, however, the output will not change. Notice that the inverter prevents the invalid state that was possible in the S-R latches.

A major disadvantage of the 7475 is that when the clock is HIGH (enabled), the output changes with any changes of the input. Thus, there is no isolation between the input and output during the HIGH portion of the clock pulse.

Figure 3- A gated D latch

Flip-flops are synchronous bi-stable devices. In this case synchronous means that the output changes states only at the specified point on a triggering input called the clock; that is, changes in the output occur in synchronization with the clock.

An edge triggered flip-flop changes state either at the positive edge (rising edge) or at the negative edge (falling edge) of the clock pulse and is sensitive to its inputs only at this transition of the clock. An edge-triggered flip-flop provides the desired isolation between the input and output.

The preset () and clear () (active-LOW) inputs allow the flip-flop to be preset or cleared whether the clock is activated or not. These types of inputs are called asynchronous inputs.

The functioning of the J-K flip-flop is identical to that of the S-R flip-flop in the SET, RESET, and no-change conditions of operation. The difference is that the J-K flip-flop has no invalid state, as does the S-R flip-flop. The J-K flip-flop overcomes this condition by cross-connecting the outputs back to the inputs. This connection causes the flip-flop to toggle (change to the opposite state) when the J and K inputs are both active-HIGH, thus eliminating the invalid state.

Figure 4- An Edge-Triggered S-R Flip-Flop

The operation of the 7474 DUAL D-Type Positive Edge-Triggered Flip-Flop is as follows:

The 7474 contain two identical D-type positive edge-triggered flip-flops, each with active-LOW preset (PRE) and clear (CLR) inputs. When A goes HIGH, QA goes HIGH on the rising edge of A. (Notice that the D input of the flip-flop, A is always a 1). After QA goes to a 1, the D input of the flip-flop, B is a 1, and when the next positive edge of the clock occurs, QB goes HIGH. When QB goes HIGH, then the QB output goes LOW and immediately resets QA back to 0. Because the D input of the flip-flop, B is now LOW, QB will go LOW on the next clock pulse. As you can see, QB was ON for exactly one clock period regardless of how long you kept switch A on.

Figure 5- An Edge-Triggered D Flip-Flop

The operation of the 74ALS112A Dual J-K Negative Edge-Triggered Flip-Flop is as follows:

The 74ALS112A consist of two identical negative edge-triggered J-K flip-flops with active-LOW PRE and CLR inputs. First, operate the CLR and PRE, and verify that the Q and Q outputs respond properly.

Before performing the clocked portion of this experiment, clear the flip-flop, and then place the () and () inputs in the inactive states (both HIGH). Notice that the J-K flip-flop toggles when both the J and K inputs are HIGH and the clock is pulsed. Also notice that you cannot change the output of the flip-flop by changing the state of the J and K inputs while the clock is HIGH. Observe that the output changes on the negative edge (on the HIGH-to-LOW transmission) of the clock pulse.

Figure 6- An Edge Triggered J-K Flip-Flop

III. Methods and materials

Equipment

· Texas Instruments 7400 NAND gate

· Texas Instruments 7474 dual D-type flip-flop

· Texas Instruments 7475 gated D latch

· Texas Instruments 74ALS112A dual J-K flip-flop

· Twin Industries TW-E41-1060 Breadboard

· Oscilloscope

· Power Supply

Procedure

We installed the integrated circuit on the breadboard as shown and operated the data switches for each exercise below and check the results by verified the data expected in the truth table to make sure they matched with those obtained experimentally.

IV. Results

Table 1- Truth for a S-R latch

S	R	Q	Q’
0	0	Q	Q’
0	1	0	1
1	0	1	0
1	1	Invalid	Invalid

Figure 7- A gated S-R latch

Figure 8- A gated S-R latch

Figure 9-S-R latch waveforms

Table 2- Truth table for Gated D Latch

E	D	Q	Q’
1	0	0	1
1	1	1	0
0	X	Q	Q’

Figure 10- A gated D-latch

Figure 11- A gated D-latch waveform

Table 3- Truth table for D Flip Flop with Edge- Triggered

Clock	D	Q
Rising Edge	0	0
Rising Edge	1	1
Non-Rising Edge	X	Q

Figure 12- An Edge-Triggered D Flip-Flop

Table 4-Truth table for D Flip Flop

D	Q (current state)	Q+ (next state)	Operation
0	0	0	Reset
0	1	0	Reset
1	0	1	Set
1	1	1	Set

Figure 13- D Flip Flop

J	K	Q (current state)	Q+ (next state)	Operation
0	0	0	0	No change
0	0	1	1	No change
0	1	0	0	Reset
0	1	1	0	Reset
1	0	0	1	Set
1	0	1	1	Set
1	1	0	1	Toggle
1	1	1	0	Toggle

Truth table for a J-K flips flop.

Figure 14-J-K flip-flop using the 74ALS112A

Figure 15- J-K Flip Flop

Discussion

Latches are circuits that store single bits. One basic type of latch is the RS-latch which has two inputs, labeled Set and Reset. These two inputs, which are typically labeled S and R, provide a means for changing the state, Q, of the circuit. When both inputs, R and S, are equal to 0 the latch maintains its existing state. When R=0 and S=1 the latch is said to be in the Set state. In this case, the circuit output is 1. When R=1 and S=0 the latch is said to be in the reset state and the circuit output is 0. Finally, if R=S=1 the circuit output is going to be 0. This is considered to be an illegal state for an RS-latch. A flip-flop is a basic sequential circuit element that stores one bit. A flip-flop changes its output state at the edge of a controlling clock signal. When a set of n flip-flops is used to store n bits of information, we refer to these flip-flops as a register. A common clock is used for each flip-flop in a register.

CONCLUSION

Latches and flip flops have digital memory circuits that can remain in the state in which they were set and analyzed. Latches act as bi-stable devices that can reside in either of two states by feedback arrangement, where the outputs are connected back to the opposite inputs. The main difference between latches and flip-flops is in the method used for changing their state. Latches are level-triggered and flip-flops are edge-triggered.

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