EET230 Digital Systems LAB Unit-2 Lab

Method

In the first part of this lab assignment I will use 3 - AND3 gates with 9 inputs, 1 output and a OR3 gate. I will connect 3 inputs to an AND3 gate then connect those gates to the OR3 gate and that will be connected to the output. Once my first circuit is complete I will start a compilation and start my second circuit.

Unit 2 Lab Assignment Results

Experiment: Hardware Description Languages and Quartus II

Chapter 4: 4-53 (Page 246)

53. Write a VHDL program for the logic circuit in Figure 4–64

Chapter 5: 5-32 (Page 295)

32. Write a VHDL program using the data flow approach (Boolean expressions) to describe the logic circuit in Figure 5–51(b).