CSUN COMP 222 Architecture Notes: The Functional
Division of the System Bus
Topic: Functional Division of the System Bus (Address, Data, Control)
Context: Signal Classification and Exam Constant: "Which Signal Goes Where?"
Part I: The Conceptual Framework and Critical Insight
The system bus is the fundamental infrastructure connecting the core components of the Von
Neumann architecture: the Central Processing Unit (CPU), Main Memory, and Input/Output (I/O)
devices. This infrastructure is not a single, monolithic pathway but a logical trifurcation into three
distinct groups of parallel wires, each assigned an immutable, non-overlapping function. Mastery
in computer organization, particularly for a COMP 222 student, begins with the absolute certainty
of this functional division.
The critical insight is that the function of each bus is derived directly from the three essential
questions required for any digital communication:
WHERE are we going? This is the domain of the Address Bus (AB).
WHAT are we sending? This is the domain of the Data Bus (DB).
HOW and WHEN do we coordinate this? This is the domain of the Control Bus (CB).
A common pitfall is misunderstanding the nature of the information. For example, a memory
address is a number, but it is functionally a location, not a data payload, and thus belongs
exclusively to the AB. The control signals, though perhaps numerically encoded in modern serial
systems, are functionally commands, residing in the CB’s domain. This strict functional separation
is maintained across all system cycles to prevent communication errors, known as bus
contention, and is the foundational concept for understanding system architecture and
performance limits.
Part II: The Address Bus (AB) – The Unidirectional Locator
The Address Bus is the specialized channel dedicated to identifying a single target location within
the systems address space. It is the architectural map used by the Bus Master to point to a
specific cell in memory or a particular I/O device register.
A. Core Functional Characteristics
The AB’s function is simple and singular, leading to rigid characteristics:
Function: To broadcast a unique binary coordinate. This coordinate can represent either a byte-
addressable location in main memory (RAM or ROM) or a specific port assigned to an I/O
peripheral controller.
Directionality: The AB is fundamentally unidirectional. Information flows strictly out from the
device requesting the transaction (the CPU or a DMA controller, which is known as the Bus
Master) and in to all listening devices (memory modules, I/O controllers). No peripheral device
can initiate the placement of an address onto the AB; they are passive listeners who decode the
address to see if they are the intended recipient.
Bus Width and Capacity: The physical number of lines on the Address Bus determines the
systems theoretical maximum addressable memory. If the bus is
N
bits wide, it can generate
2N
unique addresses. This calculation is a fundamental constraint:
A 20-bit AB limits the system to
220
, or 1 Megabyte (MB), of addressable memory.
A 32-bit AB limits the system to
232
, or 4 Gigabytes (GB), of addressable memory.
Modern 64-bit CPUs, while architecturally 64-bit, often implement only 48 physical address lines,
limiting the physical addressable space to 256 Terabytes (TB), though the virtual address space
remains larger.
B. Signal Classification for the Address Bus
There is only one functional type of signal transmitted on the Address Bus: the Address Lines
themselves.
The Address Lines (
A0, A1, A2, … AN
): These parallel lines carry the binary code representing
the target location.
A0
is the least significant bit, and
AN
is the most significant bit. The
combined state of all these lines forms the final, unambiguous location coordinate.
Part III: The Data Bus (DB) – The Bidirectional Payload Carrier
The Data Bus is the most heavily trafficked channel, responsible for the actual movement of
instructions and data between the CPU, memory, and I/O devices. It carries the substance of the
computation.
A. Core Functional Characteristics
The DBs role as the universal payload carrier necessitates specific design points:
Function: To transport the binary representation of information that is being acted upon or
stored. This payload includes:
Machine instructions (the opcode and operand fields).
Operand data (numbers, characters, boolean values).
Calculated results (the output from the ALU).
Status information (e.g., in advanced interrupt schemes).
Directionality: The DB is inherently bidirectional. This is a requirement of the CPUs primary
operations:
Read Operation (Input): Data must flow from Memory/I/O to the CPU.
Write Operation (Output): Data must flow from the CPU to Memory/I/O.
Bus Width and Throughput: The width of the Data Bus determines the amount of information
that can be transferred in a single bus cycle. This is the primary determinant of system
throughput, or bandwidth:
A wider DB (e.g., 64 bits) allows for a larger data word or a complete instruction to be fetched
simultaneously, vastly improving efficiency over a narrow DB (e.g., 8 bits).
Contention Management: Because the DB is bidirectional, complex electronic switches called tri-
state drivers are required. In any given clock cycle, only one device is allowed to assert (drive) the
DB lines. All other devices must place their drivers in a high-impedance (floating) state to prevent
electrical collision. The Control Bus dictates precisely which device is allowed to drive the DB.
B. Signal Classification for the Data Bus
The only functional signals on the Data Bus are the data lines themselves.
The Data Lines (
D0, D1, D2,… DW
): These parallel lines carry the binary pattern of the
information payload.
Part IV: The Control Bus (CB) – The Mixed-Directionality Coordinator
The Control Bus is the most complex of the three, as it does not carry location or data but carries
the signals necessary for choreography, synchronization, and resource management. It is the
mechanism that prevents chaos.
A. Core Functional Characteristics
The complexity of the CB leads to its defining characteristic: mixed directionality. It contains lines
driven by the CPU, lines driven by peripherals, and lines shared for handshaking.
Function: To regulate the timing, define the type, and manage the access rights for all
transactions occurring on the Address and Data Buses. The major functional groups include:
Timing: Establishing a universal rhythm.
Transaction Command: Specifying Read, Write, Memory, or I/O.
Arbitration: Managing shared access to the AB/DB.
Status and Interrupts: Handling asynchronous external events.
Directionality: Mixed Directionality is the defining feature of the CB, reflecting its role as a two-
way street for system governance. Some signals are strictly output from the CPU (like Read
commands), while others are inputs to the CPU (like Interrupt requests).
B. Comprehensive Signal Catalog for the Control Bus (List Format)
The Control Bus carries several functionally distinct groups of signals.
1. Timing and Initialization Signals (CPU Output)
These are fundamental pulses and resets that establish the systems operational state.
The Clock (CLK) Signal: Provides the periodic, consistent electrical pulse that acts as the universal
timing reference for every single synchronous operation in the system. All changes on the AB and
DB are synchronized to the rising or falling edge of this signal.
The Reset (
RST
―
) Signal: When asserted (often active low), this signal forces the CPU and all
connected peripherals to clear their internal registers and return to a predefined initial state,
typically initiating the system boot sequence.
2. Transaction Type and Command Signals (CPU Output)
These signals specify what kind of operation is taking place and what action the target device
should take. These signals are typically unidirectional from the CPU.
The Read (
RD
―
) Signal: This command, when asserted, instructs the memory or I/O device
currently addressed on the AB to activate its tri-state drivers and place its data onto the Data Bus
(DB).
The Write (
WR
―
) Signal: This command, when asserted, instructs the memory or I/O device
currently addressed on the AB to activate its data latches and capture the data currently being
driven by the CPU onto the Data Bus (DB).
The Memory Request (
MREQ
―
) Signal: This indicator, asserted simultaneously with the address,
tells all listeners that the address currently on the AB refers to a location within the main memory
address space.
The I/O Request (
IOREQ
―
) Signal: This indicator, asserted simultaneously with the address, tells
all listeners that the address on the AB refers to a specific I/O port address, routing the
transaction away from the memory controller.
3. Bus Arbitration Signals (Mixed Directionality)
These signals manage access to the shared AB and DB, ensuring that only one Bus Master (either
the CPU or a DMA controller) is driving the buses at any given time.
The Bus Request (
BR
―
) Signal: A signal asserted by a potential Bus Master (like a DMA controller)
to formally request permission from the current Master (usually the CPU) to take control of the
AB and DB. This signal is bidirectional in the sense that it originates from a peripheral but is
directed toward the CPU.
The Bus Grant (
BG
―
) Signal: A signal asserted by the CPU, in response to a
BR
―
, indicating that it is
finishing its current cycle and will soon place its drivers for the AB and DB into a high-impedance
state, thus relinquishing control. This signal is unidirectional (CPU
→
Device).
4. Status, Synchronization, and Interrupt Signals (Device Input to CPU)
These signals manage asynchronous events, speed differences, and external requests for service.
The Ready (
READY
―
) Signal: A synchronization signal asserted by a slower peripheral or memory
device to instruct the faster CPU to pause by inserting one or more Wait States into the current
bus cycle. This is crucial for managing timing discrepancies and is essentially bidirectional (Device
→
CPU).
The Interrupt Request (
∫
―
¿
) Signal: A signal asserted by a peripheral to inform the CPU that an
asynchronous event has occurred (e.g., keypress, network packet arrival) and that it requires
immediate attention. This is a crucial bidirectional signal (Device
→
CPU).
The Non-Maskable Interrupt (
NMI
―
) Signal: A special, high-priority interrupt request that the CPU
cannot ignore or postpone, typically reserved for catastrophic system errors like imminent power
failure. This is bidirectional (Device
→
CPU).
The Interrupt Acknowledge (
INTA
―
) Signal: A command asserted by the CPU to confirm it has
recognized an
∫
―
¿
request and is ready to receive the interrupt vector (often via the Data Bus).
This signal is unidirectional (CPU
→
Device).
Part V: The Coordinated Execution Cycle (The Interplay)
Understanding the functional division is best realized by tracing a single Memory Read operation
through the Fetch-Decode-Execute cycle. In this deep trace, we observe the precise moment
each bus is active, reinforcing their separate roles.
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A. Phase 1: The Instruction Fetch
The CPU needs to retrieve the instruction at the address contained in the Program Counter (PC).
Step 1: Location Broadcast (Address Bus is Active)
CPU Action: The address from the Program Counter (PC) is loaded into the Memory Address
Register (MAR).
Bus Action: The address stored in the MAR is immediately driven onto the Address Bus (AB). The
AB is now broadcasting the location of the instruction.
Control State: The Control Bus is initially stable, ensuring no conflicting commands are present.
The Data Bus is idle (high impedance).
Step 2: Command Assertion (Control Bus is Active)
CPU Action: The Control Unit decodes the need for a memory read operation.
Bus Action: The Control Unit asserts the
MREQ
―
(Memory Request) signal and the
RD
―
(Read)
signal onto the Control Bus (CB). The CB is now broadcasting the command.
Target Response: The memory controller latches the address from the AB and prepares to
retrieve the data.
Step 3: Synchronization and Wait State Check (Control Bus Intervenes)
CPU Action: The CPU checks the
READY
―
signal on the Control Bus.
Bus Action: If memory is slow, the memory controller asserts
READY
―
high, forcing the CPU to
insert Wait States. The Control Bus (CB) is orchestrating the timing delay.
Timing: The AB maintains the address, and the DB remains idle during this delay.
Step 4: Data Transfer (Data Bus is Active)
CPU Action: Once the
READY
―
signal confirms the memory is ready, the CPU continues.
Bus Action: The memory controller activates its drivers and places the instruction word onto the
Data Bus (DB). The DB is now carrying the payload.
Final Latch: The CPU latches the data from the DB into the Memory Buffer Register (MBR).
Step 5: Transaction Termination (Control Bus Releases)
CPU Action: The instruction is successfully captured in the MBR.
Bus Action: The Control Unit de-asserts (raises) the
RD
―
signal on the Control Bus (CB). This
command release causes the memory controller to immediately disable its DB drivers, returning
the DB to an idle state and preventing contention.
B. Synthesis of the Fetch Cycle Interplay
The functional division is absolute across the cycle:
The AB defines the target location once and remains stable.
The CB initiates the command (
RD
―
), manages the delay (
READY
―
), and terminates the
transaction.
The DB is only active for one brief window, carrying the instruction payload, and only when
permitted by the CB (
RD
―
asserted).
Part VI: Extended Analysis of Complex Control Bus Functions
Since the Control Bus is the most functionally diverse and critical for coordination, we must
examine its key roles in detail, particularly arbitration and asynchronous events.
1. Bus Arbitration: Managing the AB/DB Resource
Arbitration is the process of deciding which device—the CPU or another Bus Master (like a DMA
controller)—is allowed to use the Address and Data Buses at any given moment. This is a pure
Control Bus function.
The Request: The potential Master asserts the
BR
―
(Bus Request) signal on the CB. This is a direct
command to the CPU.
CPU Reaction: The CPU receives
BR
―
and must finish its current instruction cycle. It then uses the
CB to inform the requester it has relinquished control.
The Grant: The CPU asserts the
BG
―
(Bus Grant) signal on the CB. This is the command that
officially transfers the mastership.
Control Overlap: During a DMA transfer, the CPU is effectively locked out from using the Address
Bus or the Data Bus. This period is governed entirely by the status of the
BR
―
and
BG
―
lines on the
Control Bus. The DMA controller then uses the AB to send its data addresses and the DB to
transfer the payload, all while generating its own internal
RD
―
or
WR
―
signals, essentially
mimicking the CPUs transaction role.
2. Interrupts: Handling Asynchronous Events
Interrupts allow the CPU to respond to unpredictable external events (like a key press or a disk
error) without constantly polling every device, a massive efficiency gain.
The Signal: The device asserts the
∫
―
¿
(Interrupt Request) signal on the CB. This is an immediate,
high-priority status report.
CPU Acknowledgment: The CPU, upon recognizing the
∫
―
¿
, asserts the
INTA
―
(Interrupt
Acknowledge) signal on the CB, confirming that it is pausing its program execution.
Vector Transfer: In many architectures, the interrupting device responds to
INTA
―
by placing a
small code (the interrupt vector) onto the Data Bus (DB). This is a critical point: while the request
is a CB function, the response (the vector) is data and uses the DB, showcasing the interplay. The
Control Bus dictates the timing of this DB transfer.
NMI Distinction: The Non-Maskable Interrupt (
NMI
―
) is architecturally separate on the Control
Bus because its request cannot be ignored by the CPUs internal interrupt mask flag, highlighting
its critical status.
Part VII: Signal Type Classification Summary (List Format)
To summarize the definitive functional assignments, here is a categorized list of common signals
and their required bus, which is the primary focus of the exam topic.
A. Bus Assigned to Location Coordinates
Address Bus (AB) is the sole carrier of location information.
A0, A1, A2, … AN
(Address Lines)
B. Bus Assigned to Information Payloads
Data Bus (DB) is the sole carrier of the content or information being moved.
D0, D1, D2,… DW
(Data Lines)
Machine Instructions (Opcode and Operands in transit)
ALU Result Data
Interrupt Vector (during the
INTA
―
response cycle)
C. Bus Assigned to Command, Timing, and Orchestration
Control Bus (CB) is the carrier for all signals that manage the transactions timing, type, or
resource access.
Timing Signals:
Clock (CLK)
Reset (
RST
―
)
Ready (
READY
―
)
Transaction Command Signals:
Read (
RD
―
)
Write (
WR
―
)
Memory Request (
MREQ
―
)
I/O Request (
IOREQ
―
)
Arbitration and Status Signals:
Bus Request (
BR
―
)
Bus Grant (
BG
―
)
Interrupt Request (
∫
―
¿
)
Interrupt Acknowledge (
INTA
―
)
Non-Maskable Interrupt (
NMI
―
)
Part VIII: Architectural Evolution and Conclusion
While the traditional parallel bus has given way to high-speed serial protocols like PCI Express
(PCIe), the functional segregation remains the conceptual bedrock.
1. The Functional Division in Serial Systems
In a PCIe link, a single high-speed differential pair replaces the separate AB, DB, and CB wires.
However, the information carried still adheres to the functional division:
Address and Data: The AB and DB functions are merged into the Transaction Layer Packet (TLP)
payload. The TLP contains fields for the destination address (AB function) and the payload data
(DB function).
Control: The CB functions (commands, timing) are implemented by various packet header fields
and protocol layers:
Command: The TLP header includes a "Type" field (e.g., Memory Read Request, Memory Write
Request) which replaces the
RD
―
and
WR
―
control signals.
Timing/Flow: The Data Link Layer manages flow control using credits and acknowledgments,
which replaces the
READY
―
signal and the explicit clock pulse for synchronization.
This evolution confirms that the functional division is a profound architectural principle, not just a
wiring scheme. It is the logical necessity that enables error-free communication, regardless of the
physical medium.
