CSUN COMP 222 Architecture Notes: Deep Dive into the MIPS R-
Type Instruction
Topic: The Register-Type (R-Type) Instruction Format
Context: Opcode (6 bits), rs, rt, rd, shamt (5 bits each), funct (6 bits)
Part I: A Student’s Foundational Insight into the R-Type Structure
As a COMP 222 student focusing on computer organization, my primary insight into
the MIPS R-Type instruction is that it embodies the core tenets of Reduced
Instruction Set Computing (RISC). Unlike complex instructions that might embed
memory addresses or large constants, the R-Type format is meticulously
constrained to exactly 32 bits, with every field dedicated to identifying registers or
defining the specific operation.
The genius of the R-Type lies in its opcode field being consistently zero (
0000002
).
This is not an arbitrary choice; it is a dedicated signal to the Control Unit. It screams:
“I am an R-Type instruction! Ignore the opcode and look only at the funct field to
determine what I actually do.” This functional redundancy—using the opcode for
classification and the function field for specification—is a design choice that
dramatically simplifies the hardware required for decoding and execution.
When studying this format, it’s essential to move beyond simple memorization and
understand the data flow. When an R-Type instruction like add
t0,
t1, $t2 is
executed, the entire process is completed internally within the CPU, relying only on
the registers and the Arithmetic Logic Unit (ALU). No external memory access is
required. This efficiency of design, minimizing complexity by maximizing regularity,
is the central lesson of the MIPS architecture.
Part II: The Bit-Level Anatomy of the R-Type Format
The R-Type instruction format is a fixed-length 32-bit word, a requirement imposed
by the MIPS design to ensure fast and regular instruction fetching. This 32-bit word
is subdivided into six non-overlapping fields, each with a specific and predictable
function in the execution cycle.
1. The Opcode Field (Bits 31–26) – The Format Identifier
The opcode occupies the six most significant bits of the instruction word. Its role in
the R-Type is counter-intuitive but absolutely critical for the Control Unit.
Size and Location: 6 bits (Bits 31 to 26).
Value: For all fundamental R-Type instructions (arithmetic, logic, shifts, and jumps
like jr), the opcode must be set to zero, represented in binary as 〔〕
000000 〔UNDERSCORE 〕2
.
Functional Role: The zero value serves as a primary flag, telling the CPU’s Control
Unit to route the remaining 26 bits of the instruction word to the R-Type decoding
logic. This instantly distinguishes the R-Type from the I-Type
(Immediate/Load/Store) and J-Type (Jump) formats, which utilize non-zero
opcodes. The opcode thus performs a classification function, delegating the actual
operation identification to the function field.
2. The rs Field (Bits 25–21) – The First Source Register
The rs field identifies the register containing the first operand for the ALU
operation.
Size and Location: 5 bits (Bits 25 to 21).
Encoding Capacity: With 5 bits, this field can specify
25=32
unique registers,
corresponding precisely to the 32 general-purpose registers available in the MIPS
register file (e.g.,
t0,
s1, $sp).
Functional Role: During the Instruction Decode stage of the pipeline, the 5-bit value
in the rs field is extracted and used as an address input to the Register File’s read
port 1. The data stored in that register is then retrieved and forwarded to the ALU
for computation.
3. The rt Field (Bits 20–16) – The Second Source Register
The rt field has a dual role, but for standard R-Type arithmetic and logic operations,
it specifies the second source register.
Size and Location: 5 bits (Bits 20 to 16).
Encoding Capacity: Like rs, it can specify any of the 32 general-purpose registers.
Functional Role: During the Decode stage, the 5-bit value in the rt field is extracted
and used as an address input to the Register File’s read port 2. The data stored in
this register is also forwarded to the ALU, acting as the second operand. Note that
this field’s name can be misleading; while historically it meant “Target Register,” in
R-Type arithmetic, it typically serves as a second source.
4. The rd Field (Bits 15–11) – The Destination Register
The rd field is universally reserved for naming the register that will receive the
result of the ALU operation.
Size and Location: 5 bits (Bits 15 to 11).
Encoding Capacity: Can specify any of the 32 registers.
Functional Role: This is the critical field for the Write Back stage. Its 5-bit value is
routed to the Register File’s write address port. Once the ALU completes its
calculation, the result is directed back to the Register File and stored in the specific
register location designated by this field. For an instruction like add
t0,
t1,
t2, theregister
t0 is specified by the rd field.
5. The shamt Field (Bits 10–6) – The Shift Amount
The shamt field, or Shift Amount, is a specialized operand field used only by shift
instructions (like sll - shift left logical) and is ignored by all other R-Type
instructions.
Size and Location: 5 bits (Bits 10 to 6).
Encoding Capacity: 5 bits allow for a maximum shift amount of
25−1=31
positions.
Functional Role: If the instruction is a shift operation (e.g., sll
t0,
t1, 5), the rs field is
unused and set to zero, and the shift amount (5 in this example) is encoded directly
into the shamt field. During the Execution stage, the ALUs shifter component uses
this 5-bit value to determine how many positions to shift the operand provided by
the rt register. If the instruction is not a shift instruction (e.g., add), this field must
be set to zero and is ignored by the Control Unit.
6. The Function Field (Bits 5–0) – The Operation Specifier
The funct field is the true identifier for the R-Type operation. It is the sole indicator
of the action once the Control Unit confirms the opcode is zero.
Size and Location: 6 bits (Bits 5 to 0).
Encoding Capacity: 6 bits allow for
26=64
unique R-Type operations to be encoded,
providing ample space for standard arithmetic, logical, and specialized instructions.
Functional Role: The 6-bit value is fed into the Control Unit’s secondary decoding
logic. This logic determines the exact command signals needed for the ALU. For
example, the function code for add is
1000002
, while the function code for sub is
1000102
. This field ultimately dictates the ALUs mode of operation.
Part III: Functional Flow and Control Unit Interaction
The successful execution of an R-Type instruction hinges on the precise and
coordinated use of these six fields by the Control Unit and the Register File.
1. Decoding Logic and Data Path Setup
The R-Type instruction undergoes a specific decoding process:
Opcode Check: The 6-bit opcode is examined first. Since it is
0000002
, the Control
Unit immediately sets the necessary control lines:
RegDst (Register Destination) = 1: This signal directs the MUX (multiplexer)
connected to the Register File write address port to select the rd field (bits 15–11)
as the destination, overriding the default rt field used by I-Type instructions.
ALUSrc (ALU Source) = 0: This signal ensures that the second input to the ALU
comes from the Register File (the data from the rt register) and not from the sign-
extended immediate field (which would be used by I-Type).
MemRead/MemWrite = 0: This signal prevents any activation of the data memory
unit, confirming that R-Type instructions are purely computational and do not
interact with memory.
Function Field Analysis: After the initial checks, the Control Unit completely ignores
the opcode and uses the 6-bit funct field as the sole input to determine the specific
ALU operation. A specialized component, often called the ALU Control Unit, takes
the funct field and generates a 4-bit (or similar width) code that tells the ALU
exactly which operation to perform (e.g., 0010 for ADD, 0110 for SUB, 0000 for
AND).
2. The Register File as Central Hub
The 32-register Register File is the central hub for R-Type execution:
Three Ports: The Register File has three address ports: two for reading (
rs
and
rt
)
and one for writing (
rd
).
Simultaneous Reads: In the Decode stage, the
rs
and
rt
fields are simultaneously
used to retrieve two 32-bit operands. This parallel read capability is essential for
speed.
Sequential Write: In the Write Back stage, the single write address (selected via the
RegDst signal from the rd field) is used to store the 32-bit result.
The strict 5-bit size for the register fields is a direct result of the design trade-off
that limits MIPS to 32 registers. This constraint keeps the instruction word compact
and the decoding logic simple, fulfilling the RISC philosophy. Expanding the register
set, while potentially improving performance, would require 6 bits per field (for 64
registers), thus requiring 3 more bits total, and potentially forcing a design
compromise elsewhere in the fixed 32-bit format.
Part IV: The R-Type Instruction in the MIPS Execution Pipeline
Execution of an R-Type instruction, such as the exemplary add
t0,
t1, $t2, is a
textbook walk-through of the five stages of the classic MIPS pipeline. Understanding
this flow is crucial for COMP 222 exams.
1. Stage 1: Instruction Fetch (IF)
Action: The address in the Program Counter (PC) is used to access Instruction
Memory.
Result: The 32-bit R-Type instruction word is fetched and stored in the Instruction
Register (IR).
Update: The PC is incremented by 4 (the size of one instruction word) to point to the
next instruction.
2. Stage 2: Instruction Decode (ID) and Register Fetch
Action: The Control Unit decodes the instruction fields.
The opcode (〔〕
000000 〔UNDERSCORE 〕2
) is recognized as an R-Type.
The rs field (
t1
) and rt field (
t2
) are used to read the data contents of these two
registers from the Register File.
Result: Two 32-bit source operands are now available, ready to be forwarded to the
next stage.
Control Signals: Control signals (like
RegDst=1
and
ALUSrc=0
) are generated,
specifying the R-Type execution path.
3. Stage 3: Execute (EX)
Action: The ALU performs the computation.
The two source operands (data from
t1
and
t2
) arrive at the ALU inputs.
The ALU Control Unit uses the funct field (〔〕
100000 〔UNDERSCORE 〕2
for
ADD) to set the ALU to addition mode.
For shift operations, the shamt field is used to control the shift amount, with the rs
field being ignored.
Result: The 32-bit result of the operation (e.g.,
t1+t2
) is calculated.
4. Stage 4: Memory Access (MEM)
Action: R-Type instructions perform no memory operations.
Result: The instruction simply passes through this stage, with the ALU result being
forwarded.
Efficiency Note: This is where the RISC philosophy simplifies the pipeline. Since R-
Type instructions are purely computational, they do not need the memory access
hardware, allowing the pipeline stage to be structurally simple and fast.
5. Stage 5: Write Back (WB)
Action: The result is written back to the Register File.
The 32-bit result from the ALU is routed back to the Register File’s data input port.
The write address is determined by the rd field (selected by the
RegDst=1
signal),
which specifies $t0.
Result: The register
t0isupdatedwiththesumof
t1 and $t2. The instruction is complete.
Part V: The Encoding and Decoding Process (Assembler to Machine Code)
The fixed format of the R-Type instruction allows for a simple and deterministic
conversion process, which is the job of the assembler. This process ensures the
structural regularity that the hardware relies on.
1. Assembly to Binary Encoding Example
Let’s trace the instruction add
t0,
t1,
t2throughtheencodingprocess . Wemustusethestandardizedregisternumbers :
t0
is 8,
t1
is 9,∧¿
t2
is 10
. The add‘ function code is 〔〕
32 〔UNDERSCORE 〕10
(〔〕
100000 〔UNDERSCORE 〕2
).
The process involves mapping the three source/destination registers and the
operation into the fixed 32-bit structure:
Step A: Determine the Opcode: For add, the instruction is R-Type, so the opcode
must be 〔〕
000000 〔UNDERSCORE 〕2
.
Step B: Determine the rs Field (Source 1): The second operand in the MIPS assembly
format is
t1
(register 9).
Decimal Value: 9
5-bit Binary: 〔〕
01001 〔UNDERSCORE 〕2
Step C: Determine the rt Field (Source 2): The third operand is
t2
(register 10).
Decimal Value: 10
5-bit Binary: 〔〕
01010 〔UNDERSCORE 〕2
Step D: Determine the rd Field (Destination): The first operand is the destination,
t0
(register 8).
Decimal Value: 8
5-bit Binary: 〔〕
01000 〔UNDERSCORE 〕2
Step E: Determine the shamt Field: Since this is an add instruction (not a shift), the
field must be zero.
Decimal Value: 0
5-bit Binary: 〔〕
00000 〔UNDERSCORE 〕2
Step F: Determine the funct Field: The function code for add is 32.
Decimal Value: 32
6-bit Binary: 〔〕
100000 〔UNDERSCORE 〕2
Final 32-bit Machine Code Construction (Concatenation):
The final machine code is constructed by concatenating these six binary fields in
order, from most significant bit to least significant bit:
Opcode rs rt rd shamt funct
〔〕
000000 〔UNDERSCORE 〕2
〔〕
01001 〔UNDERSCORE 〕2
〔〕
01010 〔UNDERSCORE 〕2
〔〕
01000 〔UNDERSCORE 〕2
〔〕
00000 〔UNDERSCORE 〕2
〔〕
100000 〔UNDERSCORE 〕2
Full Binary Word: 〔〕
000000 01001 01010 0100000000 100000 〔UNDERSCORE 〕2
Hexadecimal Representation (The standard display): The 32 bits are grouped into 8
groups of 4 bits:
〔〕
0000 0001 00101010 0100 0000 0010 0000 〔UNDERSCORE 〕2
〔〕
012 A4020 〔UNDERSCORE 〕16
The assembler’s job is simply this bit manipulation and concatenation, which is
straightforward due to the R-Type’s highly regular and predictable field structure.
2. Binary to Assembly Decoding
The decoding process in the CPU reverses this mapping. When the Control Unit
reads 〔〕
012 A4020 〔UNDERSCORE 〕16
:
It extracts the first 6 bits (〔〕
000000 〔UNDERSCORE 〕2
), confirming it is an R-
Type.
It looks at the last 6 bits (〔〕
100000 〔UNDERSCORE 〕2
), identifying the
operation as add.
It extracts the 5 bits starting from bit 25 (〔〕
01001 〔UNDERSCORE 〕2
), which is
register 9 (
t1
), setting it as the first source (
rs
).
It extracts the 5 bits starting from bit 20 (〔〕
01010 〔UNDERSCORE 〕2
), which is
register 10 (
t2
), setting it as the second source (
rt
).
It extracts the 5 bits starting from bit 15 (〔〕
01000 〔UNDERSCORE 〕2
), which is
register 8 (
t0
), setting it as the destination (
rd
).
It extracts the 5 bits for
shamt
(〔〕
00000 〔UNDERSCORE 〕2
), confirming no
shifting is involved.
The CPU thus reconstructs the three register numbers and the operation type
necessary for the execution stage.
Part VI: Comprehensive R-Type Instruction Examples and Encoding Practice
To ensure a thorough grasp of the R-Type, we will explore several diverse examples,
detailing the function and the binary field mapping for each.
Example A: Subtraction Operation (sub
s0,
s1, $s2)
This is a core arithmetic operation, mirroring the add example but utilizing a
different function code.
Assembly: sub
s0,
s1,
s2¿
s1 - s2
andstorein
s0$)
Register Mapping:
Destination
rd
: ‘
s0
(Register 16)
Source 1
rs
: ‘
s1
(Register 17)
Source 2
rt
: ‘
s2
(Register 18)
Field Values (Binary/Decimal):
Opcode: 〔〕
000000 〔UNDERSCORE 〕2
(0)
rs: 〔〕
10001〔UNDERSCORE 〕2
(17)
rt: 〔〕
10010 〔UNDERSCORE 〕2
(18)
rd: 〔〕
10000 〔UNDERSCORE 〕2
(16)
shamt: 〔〕
00000 〔UNDERSCORE 〕2
(0)
Funct: 〔〕
100010 〔UNDERSCORE 〕2
(34 for sub)
Full Binary Sequence: 〔〕
000000 1000110010 10000 00000 100010〔UNDERSCORE 〕2
Example B: Logical AND Operation (and
t3,
s4, $t4)
This illustrates a bitwise logical operation, which uses the same register fields but a
different function code.
Assembly: and
t3,
s4,
t4¿
s4 \ AND \ t4
andstorein
t3$)
Register Mapping:
Destination
rd
: ‘
t3
(Register 11)
Source 1
rs
: ‘
s4
(Register 20)
Source 2
rt
: ‘
t4
(Register 12)
Field Values (Binary/Decimal):
Opcode: 〔〕
000000 〔UNDERSCORE 〕2
(0)
rs: 〔〕
10100 〔UNDERSCORE 〕2
(20)
rt: 〔〕
01100〔UNDERSCORE 〕2
(12)
rd: 〔〕
01011 〔UNDERSCORE 〕2
(11)
shamt: 〔〕
00000 〔UNDERSCORE 〕2
(0)
Funct: 〔〕
100100 〔UNDERSCORE 〕2
(36 for and)
Full Binary Sequence: 〔〕
000000 10100 01100 01011 00000 100100〔UNDERSCORE 〕2
Example C: Shift Logical Left Operation (sll
a0,
a1, 4)
This is a shift instruction, which is the only R-Type operation that utilizes the
dedicated shamt field, and notably ignores the rs field.
Assembly: sll
a0,
a1, 4 (Shift the contents of
a1
left by 4 bits and store in
a0
)
Register Mapping:
Destination
rd
: ‘
a0
(Register 4)
Source (Register to be shifted)
rt
: ‘
a1
(Register 5)
Unused Source
rs
: 〔〕
00000 〔UNDERSCORE 〕2
(0 - must be zero)
Field Values (Binary/Decimal):
Opcode: 〔〕
000000 〔UNDERSCORE 〕2
(0)
rs: 〔〕
00000 〔UNDERSCORE 〕2
(0)
rt: 〔〕
00101 〔UNDERSCORE 〕2
(5)
rd: 〔〕
00100 〔UNDERSCORE 〕2
(4)
shamt: 〔〕
00100 〔UNDERSCORE 〕2
(4) - The 4-bit shift amount is directly
encoded here.
Funct: 〔〕
000000 〔UNDERSCORE 〕2
(0 for sll) - Note that the sll operation uses
a different function code than add. The opcode and funct fields are both zero for sll,
which is why the shamt field becomes the critical differentiator for the Control Unit.
Full Binary Sequence: 〔〕
000000 00000 00101 0010000100 000000 〔UNDERSCORE〕2
Example D: Register Jump Operation (jr $ra)
This is a control flow instruction that uses the R-Type format purely to leverage the
register access capabilities, demonstrating a non-arithmetic use case.
Assembly: jr
ra ¿
ra$)
Register Mapping:
Source
rs
: ‘
ra
(Register 31) - This register holds the jump target address.
Destination
rd
: 〔〕
00000 〔UNDERSCORE 〕2
(0 - ignored)
Source
rt
: 〔〕
00000 〔UNDERSCORE 〕2
(0 - ignored)
Field Values (Binary/Decimal):
Opcode: 〔〕
000000 〔UNDERSCORE 〕2
(0)
rs: 〔〕
11111〔UNDERSCORE 〕2
(31)
rt: 〔〕
00000 〔UNDERSCORE 〕2
(0)
rd: 〔〕
00000 〔UNDERSCORE 〕2
(0)
shamt: 〔〕
00000 〔UNDERSCORE 〕2
(0)
Funct: 〔〕
001000 〔UNDERSCORE 〕2
(8 for jr)
Execution Note: The ALU is bypassed entirely. The address read from
rs
(
ra
) is
routed directly to the Program Counter (PC) during the Execution stage, completing
the jump and changing the program flow.
Part VII: Architectural Implications and Trade-offs
The rigid structure of the R-Type is not a limitation but a deliberate design trade-off
that yields significant advantages, which are the essence of the RISC philosophy
espoused by MIPS.
1. The Design Philosophy of Regularity
The fact that all MIPS instructions, including R-Type, are exactly 32 bits long offers
the following:
Simplicity of Fetch: The CPU always knows exactly how many bytes (four) to fetch
from memory in the IF stage, simplifying the Control Unit and enabling faster,
constant-time memory access.
Pipelining Efficiency: Fixed-length instructions greatly simplify the decoding and
execution stages in the pipeline. All fields (rs, rt, rd) are always in the exact same bit
positions (e.g.,
rs
is always bits 25–21), allowing the hardware to simultaneously
decode fields and fetch register values before the Control Unit has fully identified
the instruction type. This parallel preparation is crucial for maximizing clock speed.
2. The Trade-off: Code Density
The R-Type instruction’s reliance on only register operands means that any time
data needs to be loaded from memory or any immediate (constant) value is used, a
separate instruction, specifically an I-Type instruction (like lw, addi), must be used.
Example: To perform
t0=t1+5
:
The value 5 must first be loaded into a temporary register
t3
using an I-Type
instruction (addi
t3,
zero, 5).
Then, the addition can be performed using an R-Type instruction (add
t0,
t1, $t3).
Result: RISC code tends to require more instructions (lower code density) than
equivalent CISC code (e.g., x86), but the simplicity of the R-Type instructions allows
the pipeline to execute them much faster. This architectural choice prioritizes high
clock speed and instruction throughput over code size.
3. Register-to-Register Operation and Data Hazards
The R-Type enforces the principle of register-to-register operations. The ALU only
operates on data already present in the high-speed register file.
Performance: This is much faster than performing memory-to-register or memory-
to-memory operations, a characteristic of CISC. By requiring data to be loaded
explicitly via I-Type instructions, the design separates the slow memory access
(Load/Store) from the fast computation (R-Type), simplifying hazard detection in
the pipeline.
Data Hazards: The R-Type structure dictates that two source operands are read and
one result is written back. This clear input/output structure makes it easy for the
pipelines forwarding logic to detect when a subsequent instruction needs the result
of a preceding R-Type instruction, enabling efficient data forwarding (or bypassing)
to mitigate pipeline stalls (Data Hazards).
Part VIII: The R-Type as the Foundation of the MIPS Instruction Set
The R-Type instruction set forms the backbone of the MIPS ISA, encompassing all
purely computational and logical operations. This demonstrates the completeness
and power of a small, regular instruction set.
The categories of operations consistently mapped to the R-Type format include:
Integer Arithmetic: This includes the fundamental add, sub, addu (unsigned add),
and subu (unsigned subtract) operations. These rely on the
rs
and
rt
fields for
operands and the
rd
field for the destination.
Logical Operations: Bitwise operations such as and, or, xor (exclusive OR), and nor
(NOT OR). These are essential for masking, setting, and clearing specific bits within
a word.
Shift Operations: The shift instructions, sll (shift left logical), srl (shift right logical),
and sra (shift right arithmetic), are the only instructions that rely on the dedicated
shamt
field, highlighting its specific utility.
Comparison and Set Operations: Instructions like slt (set on less than) and sltu (set
on less than unsigned) compare two source registers (
rs
and
rt
) and set the
destination register (
rd
) to 1 if the condition is true, or 0 if false.
Multiplication and Division (Special Registers): While full 32-bit multiplication and
division can utilize special R-Type instructions (mult, div), these operations
typically write their 64-bit results to the separate high-speed
HI
and
LO
registers,
requiring further R-Type instructions (mflo, mfhi - move from low/high) to access
the final result and place it into a general-purpose register. These specialized move
instructions still utilize the R-Type format for their execution logic.
In conclusion, the MIPS R-Type instruction, with its precise
6+5+5+5+5+6
bit
structure, is far more than a simple assembly template. It is a carefully engineered
artifact that represents the definitive solution to building a fast, pipelined CPU core.
By dedicating all 32 bits to register addressing and control signals, and by using the
zero opcode as a primary decoder, the R-Type format ensures the regularity
necessary for hardware simplicity and high-frequency operation, making it the most
important instruction format to master in your COMP 222 studies.
