CSUN COMP 222 Architecture Notes: Deep Dive into the MIPS J-
Type Instruction
Topic: The Jump-Type (J-Type) Instruction Format
Context: Opcode (6 bits) + Address (26 bits)
Part I: Foundational Insight and The Necessity of the J-Type
For a student of COMP 222, the MIPS J-Type instruction format, exemplified by the
simple command j label (jump to a specific label), serves a singular, critical purpose:
facilitating unconditional program control transfer across large segments of
memory. It represents the only instruction that breaks the rigid R-Type/I-Type field
structure, reflecting its unique and powerful role in program flow.
My initial insight into the J-Type is recognizing its primary architectural
justification: the range limitation of the I-Type branch instructions. While
conditional branches like beq (I-Type) use a 16-bit displacement for relative jumps,
limiting their reach to
±217
bytes (or
±215
instructions), the J-Type uses 26 bits to
specify an absolute destination, enabling jumps across a much wider address space.
This makes it indispensable for:
Calling large, distant functions.
Jumping out of deeply nested loop structures.
Implementing long-range, unconditional control flow.
The J-Type embodies a different design trade-off than the I-Type. Instead of carrying
a register or a small constant, it sacrifices those fields entirely to maximize the size
of the address component. Understanding the J-Type is primarily about mastering
the esoteric method by which the CPU transforms those 26 bits into a complete,
valid 32-bit memory address.
Part II: The 32-Bit Anatomy of the J-Type Format
The J-Type, like all MIPS instructions, occupies a fixed 32-bit word, but it is split into
only two primary fields, giving disproportionate space to the address component.
1. The Opcode Field (Bits 31–26) – The Universal Command
The opcode occupies the most significant 6 bits, confirming its role as the
instruction classifier.
Size and Location: 6 bits (Bits 31 to 26).
Value: For the standard unconditional jump (j), the opcode is typically
216
(
0000102
).
For the jump-and-link instruction (jal), used for function calls, the opcode is
316
(
0000112
).
Functional Role: A non-zero, non-R-Type-family opcode immediately informs the
Control Unit that this instruction is a J-Type. This triggers the unique control signals
that will bypass the Register File and ALU inputs entirely, directing the flow to the
Program Counter (PC) update logic. The Control Unit also sets the necessary internal
logic to perform the two critical steps of J-Type address synthesis: the shift-left-2
operation and the PC upper bit concatenation.
2. The Address Field (Bits 25–0) – The 26-bit Immediate
This field is the single largest component of any MIPS instruction, consuming
26 /32
,
or
81.25 %
, of the available bits.
Size and Location: 26 bits (Bits 25 to 0).
Encoding Capacity:
226
unique values.
Functional Role: This is not a final, absolute memory address. Instead, it represents
the lower 28 bits of the target address, once byte alignment is accounted for. The
MIPS architecture guarantees that all instructions are word-aligned (addresses are
multiples of 4), meaning the least significant 2 bits are always
002
. By omitting these
two bits from the instruction, the MIPS designers gained 4-fold addressing power
for free (since
226 ×4=228
), allowing the jump to cover
228
memory words.
Part III: The Exclusive Mechanism of Jump Address Calculation
The process of transforming the 26-bit address field into a complete, executable 32-
bit jump target address is the most critical and complex aspect of the J-Type
instruction, involving a three-step hardware mechanism that executes in the
Execution stage of the pipeline.
Step 1: The Address Field (26 bits)
The instruction word is fetched, and the 26-bit address field is extracted from bits
25 through 0. This field is treated as an unsigned value representing a word offset.
Address Field=Instruction Bits[25 :0]
Step 2: The Word Alignment Shift (Shift Left 2)
Because the MIPS architecture mandates word alignment, the two least significant
bits of any instruction address must be zero. The hardware capitalizes on this fact to
reclaim two bits of address space.
Action: The 26-bit address field is shifted left by 2 bits. This operation is equivalent
to multiplying the value by
22
, or 4.
Result: This yields a 28-bit unsigned value that is guaranteed to be a byte-aligned
address, and it represents the lower 28 bits of the final 32-bit memory address.
Lower 28 Bits=Address Field ≪2Lower 28 Bits=Instruction Bits[25 :0 ]∨¿002
Step 3: Concatenation with the Program Counter (PC)
The remaining 4 most significant bits of the 32-bit address must be sourced. Instead
of making the jump address fully absolute, which would require a full 32 bits and
necessitate a 64-bit instruction, MIPS chooses a compromise based on locality: it
assumes the jump target is within the same
228
byte (256 MB) block of memory as
the current instruction.
Action: The 4 most significant bits of the current Program Counter (PC) are
extracted and concatenated with the 28-bit result from Step 2.
Result: This synthesizes the final 32-bit target address.
Target Address=PC[31 : 28]∨¿(Address Field ≪2)
The 256 Megabyte Boundary Limitation
This concatenation method, while space-efficient, imposes a critical limitation: the
jump target must reside within the same 256 MB block as the instruction that is
currently being executed. This block is defined by the upper 4 bits of the PC. If a
program needs to jump further than this boundary (which is highly unlikely in
standard user code but possible in operating system kernels or very large
applications), the compiler must insert a special sequence of Load Upper Immediate
(lui) and Jump Register (jr) instructions to synthesize the full 32-bit address. This is
a crucial concept to understand for advanced topics in COMP 222.
Part IV: The J-Type in the MIPS Pipeline – The Jump Hazard
The execution of a J-Type instruction presents a classic example of a Control Hazard
in the MIPS pipeline, which is a required discussion point for this course.
1. The Conflict
When an instruction is fetched in the IF stage, the PC is immediately incremented to
point to the next instruction (
PC+4
). Instructions following it are fetched
sequentially.
A J-Type instruction, however, invalidates this sequential execution. The instruction
following the jump is fetched before the Control Unit has fully decoded the J-Type
and calculated the new target address.
The actual jump address calculation is only completed in the Execution (EX) stage.
By the time the jump address is known, the two instructions immediately following
the J-Type are already fetched and residing in the pipeline registers (ID/EX).
2. The Solution: The Branch Delay Slot
To resolve this conflict without requiring the pipeline to stall for two entire clock
cycles (a significant performance hit), the MIPS architecture introduced the Branch
Delay Slot (BDS).
Definition: The instruction immediately following a J-Type (or any branch/jump)
instruction, located at
PC+4
, is the instruction in the delay slot.
Rule: The instruction in the delay slot is always executed, regardless of whether the
jump is taken or not.
Compilers Role: The compiler is responsible for scheduling a useful, independent
instruction into this slot that does not affect the correctness of the program flow,
assuming the jump is always taken. Often, this is an instruction from before the
jump that can be moved without side effects, or a harmless nop (no operation)
instruction is inserted to prevent side effects, though this still results in one wasted
cycle.
This design choice complicates the compilers task but allows the pipeline to remain
simpler, avoiding the complex forwarding and interlock hardware needed to cancel
instructions, thus keeping the clock frequency high.
Part V: The Two Jump Commands – j vs. jal
While both j and jal use the identical J-Type instruction format, their functional
difference is profound, defining the primary way MIPS handles subroutine
(function) calls.
1. Unconditional Jump (j)
Assembly Syntax: j label
Opcode:
216
(
0000102
)
Action: It performs the 26-bit address calculation and unconditionally loads the
resulting 32-bit address into the Program Counter (PC). No other register is
modified. It is used for long loops or structural jumps within a program block.
2. Jump and Link (jal)
Assembly Syntax: jal function_name
Opcode:
316
(
0000112
)
Action: This is the standard MIPS function call mechanism. It performs the same
unconditional jump as j, but with one additional, critical step: it stores the return
address.
Return Address Calculation: The address of the instruction immediately following
the delay slot (
PC+8
) is saved into the dedicated return address register, $ra
(Register 31).
Return Path: When the function is finished, it uses the R-Type instruction jr $ra
(Jump Register) to return to the correct location in the calling code.
This difference highlights how a single instruction format can be reused with a
different opcode to implement a sophisticated control flow mechanism, leveraging
the dedicated $ra register.
Part VI: Comprehensive Encoding and Decoding Examples
Tracing the conversion of the jump label into the 26-bit machine code value
reinforces the importance of the address calculation rules.
Example: Encoding a Function Call (jal calculate_sum)
Assume the following addresses in memory, assuming the MIPS code segment
typically starts at 〔〕
0x00400000〔UNDERSCORE 〕16
:
Current Instruction Address (PC): 〔〕
0x00400040〔UNDERSCORE 〕16
Target Function Address (calculate_sum): 〔〕
0x00401004 〔UNDERSCORE 〕16
Goal: Determine the 26-bit address field for jal calculate_sum.
Extract the Target Address: The target is 〔〕
0x00401004 〔UNDERSCORE 〕16
.
Apply Word Alignment (Remove 2 LSBs): Since instructions are word-aligned, the
〔〕
04 〔UNDERSCORE 〕16
at the end is 〔〕
00000100 〔UNDERSCORE 〕2
. We
must divide the address by 4, which means dropping the two least significant zero
bits.
0x0040100416 →00 0000 0000 0100 0000 00000001 00012Target Address/4=0x0010040116
Extract the Lower 26 Bits: The resulting value,
0x0010040116
, is already 26 bits long
(since
226
is slightly larger than
0x0400000016
).
Address Field=0001 00000000 1000 0000 00012
Note: The full 32-bit target is
0000000001000000000100000001002
.
Determine the Opcode: For jal, the opcode is
0000112
.
Final Machine Code: Concatenate the 6-bit opcode with the 26-bit address field.
Machine Code=000011∨¿0001 0000 0000 1000 0000 00012Hexadecimal Machine Code=0xC 04040116
Execution Trace: Jump Target Verification
When the CPU executes
0xC 04040116
:
Opcode Check: It sees
0000112
(jal), confirming J-Type.
PC Upper 4 Bits: The current PC is
0x0040004016
, so the upper 4 bits are
00002
.
26-bit Address:
0001 0000 00001000 0000 00012
Shift Left 2: Becomes
0001 0000 00001000 0000 0001 002
(28 bits).
Concatenate:
PC[31:28]∨¿Lower 28 Bits
00002∨¿00010000 0000 1000 0000 0001002Final Address=0x0040100416
The jump succeeds, and the return address (
0x0040004816
, the instruction after the
delay slot) is saved in $ra.
Part VII: J-Type and Control Flow Complexity
The MIPS ISA provides two fundamental unconditional jumps, each suitable for
different scenarios, depending on whether the jump target is a large, static location
(J-Type) or a dynamic, calculated location (R-Type).
1. The R-Type Jump Register (jr $rs)
Format: R-Type (Opcode=0, Funct=8).
Address Source: The entire 32-bit address is sourced from a register (
rs
).
Use Cases:
Function Return: Using jr $ra to return from a subroutine, where the address was
dynamically saved by jal.
Indirect Jumps: Implementing features like switch statements or function pointers,
where the target address is calculated at runtime and stored in a register.
Advantages: Complete 32-bit address space coverage (no 256 MB limitation).
Dynamic target address determination.
2. The J-Type Unconditional Jump (j label)
Format: J-Type (Opcode=2 or 3).
Address Source: The 26-bit address field, combined with
PC[31:28]
.
Use Cases:
Static Jumps: Used for all simple, unconditional jumps to labels that are fixed at
compile time.
Function Calls: Used by jal for the initial jump to the function entry point.
Advantages: Simpler instruction fetching and decoding since the address is
embedded. Allows for
228
word addressable space via a short instruction.
The two jump types are complementary: the J-Type handles the bulk of static code
flow efficiently, while the R-Type jr handles the complexity of dynamic control flow
and function returns.
Part VIII: Architectural and Compiler Implications of J-Type
The J-Type’s design has profound implications for how compilers organize code and
how the hardware is built.
1. Compiler Organization and Memory Segmentation
The J-Type effectively dictates the MIPS memory segmentation scheme for the code
segment. Since the jump is limited to the current 256 MB block, compilers must
ensure that all code for a single program or module that requires static linking
remains within this boundary. This constraint reinforces the segmentation of the
address space:
Kernel Segment: High addresses (e.g., 〔〕
0x80000000〔UNDERSCORE 〕16
and
above)
Text/Code Segment: Lower addresses (e.g., 〔〕
0x00400000〔UNDERSCORE 〕16
), typically placed to ensure all static jumps stay within the
228
word address space
relative to the upper 4 PC bits.
2. Pipelining Cost and Optimization
The Control Hazard caused by the J-Type and branches (beq, bne) is often cited as
the primary reason why five-stage pipelines were not sufficient for deep
performance. Modern high-performance processors handle the jump hazard
through more advanced techniques:
Branch Prediction: Dedicated hardware attempts to guess the jump target before
the instruction is decoded, reducing the chance of a pipeline stall.
Instruction Cancellation (Flushing): If a prediction is wrong, the instructions in the
pipeline are flushed, losing cycles but maintaining correctness.
In the simple MIPS design studied in COMP 222, the Branch Delay Slot is the sole
mitigation. A key learning point is that while the BDS saves one cycle of stall, the J-
Type still consumes a cycle of wasted effort whenever a nop must be scheduled into
the slot.
3. The Instruction Word Trade-off Revisited
The J-Type represents the extreme trade-off of the MIPS fixed 32-bit instruction
format. It highlights the following principles:
Maximization of Address Space: By leveraging word alignment (Shift Left 2), the
26
bits effectively address
28
bits of memory.
Locality of Reference: By using the upper 4 bits of the current PC, MIPS relies on the
principle that most jumps are short, achieving a wide addressability without
needing a full 32-bit address field in the instruction.
In summary, the MIPS J-Type instruction format is the specialized tool for
unconditional control flow. It uses its two unique fields—the opcode and the 26-bit
address—to implement long-range jumps and function calls. The complex synthesis
of the 32-bit target address from the 26-bit field and the upper 4 bits of the PC,
combined with the necessity of the Branch Delay Slot to mitigate the control hazard,
makes the J-Type one of the most architecturally profound and essential topics to
master for your COMP 222 curriculum.
