CSUN COMP 222 Architecture Notes: Deep Dive into
the MIPS I-Type Instruction
Topic: The Immediate-Type (I-Type) Instruction Format
Context: Opcode (6 bits), rs (5 bits), rt (5 bits), immediate (16 bits)
Part I: The Architectural Rationale and Student Insight
The MIPS I-Type instruction format is the architectural compromise that gives the RISC design its
practical efficiency. While the R-Type enforces the pure register-to-register principle, the I-Type
acknowledges the undeniable reality of high-frequency operations: most computations involve
small constant values, and nearly all memory accesses require an offset from a base register.
As a COMP 222 student, the key insight here is the concept of code density. If MIPS were limited
only to R-Type instructions, every constant would first require a memory load or two separate
instructions to synthesize the constant. The I-Type bypasses this inefficiency by embedding a 16-
bit constant (or address offset) directly within the instruction word itself. This approach:
Saves Memory: Eliminates the need for multiple instructions to achieve a single goal.
Saves Time: Prevents pipeline bubbles and delays associated with extra instruction fetches.
The I-Type format must be studied not as a single template, but as three distinct templates,
because the 16-bit immediate field serves radically different purposes:
For addi (Immediate Arithmetic): The field is used as a numerical operand that must be sign-
extended to 32 bits.
For lw/sw (Load/Store): The field is used as a signed offset to calculate a memory address.
For beq/bne (Branching): The field is used as a signed displacement to calculate the new Program
Counter (PC) address.
This triple functionality is the core complexity of the I-Type, requiring the Control Unit to route
the 16 bits through three different hardware paths based on the opcode.
Part II: The 32-Bit Anatomy of the I-Type Format
Like the R-Type, the I-Type is a fixed 32-bit word, designed for the same rapid fetching and
decoding pipeline. However, its field distribution reflects its need to carry a significant constant.
1. The Opcode Field (Bits 31–26) – The Definitive Identifier
For the I-Type, the opcode is not zero, as it is in the R-Type. The non-zero value acts as the
primary signal to the Control Unit.
Size and Location: 6 bits (Bits 31 to 26).
Value: This field holds the unique identifier for the specific I-Type instruction. For example, the
opcode for addi (add immediate) is
816
(
0010002
), the opcode for lw (load word) is
2316
(
1000112
), and the opcode for beq (branch if equal) is
416
(
0001002
).
Functional Role: It is the definitive instruction classifier. The Control Units initial logic uses this
value to determine two things instantly:
This is not an R-Type instruction (Opcode
≠0
).
This instruction requires the 16-bit immediate field (I-Type structure).
2. The rs Field (Bits 25–21) – The Source/Base Register
The rs field maintains its consistent role as the first source register across all I-Type functions.
Size and Location: 5 bits (Bits 25 to 21).
Functional Role (Immediate Arithmetic): It specifies the source register whose value is added to
the immediate constant (e.g., in addi
t0,
t1, 10,
rs
is
t1
).
Functional Role (Load/Store): It specifies the base address register whose contents are added to
the immediate offset to calculate the memory address (e.g., in lw
t0,8¿
s1
¿,
rs
is
s1$).
Functional Role (Branching): It specifies the first register operand for the comparison (e.g., in beq
t0,
t1, label,
rs
is
t0
).
3. The rt Field (Bits 20–16) – The Destination/Source/Comparison Register (The Field of
Ambiguity)
The rt field is the most functionally ambiguous field in the MIPS instruction set, as its role
changes dramatically depending on the I-Type operation.
Size and Location: 5 bits (Bits 20 to 16).
Role 1: Destination Register (Immediate Arithmetic/Load): For instructions like addi or lw, the rt
field designates the register that receives the result (e.g., the sum or the loaded word). This is the
only case where
rt
functions as a destination, similar to the
rd
field in R-Type.
Role 2: Source Register (Store): For instructions like sw (store word), the rt field designates the
register whose contents are to be stored into memory. Here, it acts as a source register, providing
the data payload.
Role 3: Second Comparison Register (Branching): For instructions like beq or bne, the rt field
designates the second register operand for the comparison against
rs
. It is neither a source nor a
destination in the computational sense, but a second required input for the branch condition
logic.
The Control Unit must use the 6-bit opcode to correctly interpret the 5-bit rt field, determining if
it should be routed to the Register Files write address port, or to its read port 2.
4. The Immediate Field (Bits 15–0) – The 16-bit Payload
This 16-bit field is the defining feature of the I-Type and the source of its power and complexity.
Size and Location: 16 bits (Bits 15 to 0).
Encoding Capacity: It can represent
216=65 ,536
unique values. Since it is treated as a signed
integer (two’s complement), it can represent integers in the range
[−32768 ,+32767]
.
Functional Role: Its interpretation dictates the entire execution path.
Part III: The Three Primary Functions of the I-Type
We now examine the hardware mechanisms required for the Control Unit to properly utilize the
16-bit immediate field for its three roles.
1. Immediate Arithmetic and Logical Operations (addi, andi)
These operations perform a computation between a register value (
rs
) and the embedded
constant.
Example: addi
t0,
t1, 10 (
t0← t 1+10
)
rs
is
t1
.
rt
is
t0
(the destination).
Immediate is 〔〕
10 〔UNDERSCORE 〕10
.
The Crucial Mechanism: Sign Extension
The ALU is a 32-bit unit. The 16-bit immediate cannot be simply padded with 16 leading zeros,
because MIPS operations are usually signed. If the immediate constant is negative (e.g.,
−5
),
padding it with zeros would result in a large positive number (
0000 …0000 1111 …1011
),
leading to incorrect computation.
The Control Unit routes the 16-bit immediate through a Sign Extender unit.
Rule: The most significant bit of the 16-bit immediate (bit 15) is replicated 16 times to fill the
upper 16 bits of the 32-bit word.
If bit 15 is 0 (positive immediate), the 32-bit constant is padded with 〔 〕
0000 …0000 〔UNDERSCORE 〕2
.
If bit 15 is 1 (negative immediate), the 32-bit constant is padded with 〔 〕
1111 …1111〔UNDERSCORE 〕2
.
Data Flow: The 32-bit contents of
rs
and the sign-extended 32-bit immediate are fed to the ALU
inputs, and the result is written back to the
rt
register.
2. Data Transfer Operations (Load/Store) (lw, sw)
Load and Store instructions are the only way MIPS interacts with the memory hierarchy. The 16-
bit immediate field is used to calculate the physical memory address.
Example (Load): lw
t0,8¿
s1
¿¿
t0 \leftarrow \text{Memory}[$s1 + 8]$)
rs
is
s1
(Base Register).
rt
is
t0
(Destination for the loaded word).
Immediate is 〔〕
8〔UNDERSCORE〕10
(Offset).
The Address Calculation: The effective memory address is calculated as:
Effective Address=Contents of Register(rs)+Sign-Extended Immediate Offset
The sign-extended 16-bit immediate is added to the 32-bit value in the base register
rs
using the
ALU.
Data Flow:
ALU: Performs the addition to generate the 32-bit memory address.
Memory Stage: This address is then passed to the Data Memory Unit.
Load (lw): The data read from memory is written back to the
rt
register.
Store (sw): The contents of the
rt
register (the data payload) are written to the calculated
memory address.
Constraint: Because the offset is only 16 bits, Load/Store instructions can only access memory
locations within
±32
KB of the address stored in the base register (
rs
). This is known as base-
plus-displacement addressing.
3. Conditional Branch Operations (beq, bne)
Conditional branches determine the program flow based on a comparison between two registers.
Example: beq
t0,
t1, label (If
t0=t1
, jump to label)
rs
is
t0
.
rt
is
t1
.
Immediate is the branch offset (a 16-bit signed number).
The Comparison: The ALU is used to perform the comparison. For beq, the ALU calculates
rs− rt
.
If the result is zero, the Zero flag is set, and the branch is taken.
The Jump Target Calculation (PC-Relative Addressing): The branch offset is a signed 16-bit
number that specifies how many instructions to jump forward or backward.
Rule 1: Word Alignment and Shift: Since all instructions are 4 bytes (one word), the 16-bit
immediate is logically shifted left by 2 bits before sign extension. This creates a 30-bit
displacement, effectively multiplying the offset by 4 and ensuring the target address is word-
aligned (divisible by 4).
Rule 2: PC-Relative: The new PC address is calculated relative to the instruction after the branch
instruction (PC + 4).
New PC=(PC+4)+(Sign-Extended(Immediate ≪2))
Reach Constraint: This calculation limits the branch target to
±215
instructions (or
±217
bytes)
relative to the current instruction. While substantial, it is a key reason MIPS uses the J-Type
format for unconditional, long-range jumps.
Part IV: Detailed Encoding and Sign Extension Walkthrough
Understanding how a constant like
−4
is encoded and utilized is crucial for I-Type
comprehension.
Encoding Example: Adding a Negative Immediate (addi
s0,
s1, -4)
This operation is frequently used to adjust the stack pointer or array indices.
Instruction: addi
s0,
s1, -4
Register Mapping:
Opcode: addi
→
〔〕
001000 〔UNDERSCORE 〕2
rs
(Source): ‘
s1
→
Register 〔〕〔〕
17 〔UNDERSCORE 〕10 →10001 〔UNDERSCORE 〕2
rt
(Destination): ‘
s0
→
Register 〔 〕 〔 〕
16 〔UNDERSCORE 〕10 →10000 〔UNDERSCORE 〕2
Immediate Field Encoding:
Decimal Value: 〔〕
−4〔UNDERSCORE〕10
16-bit Twos Complement: 〔〕
1111 11111111 1100 〔UNDERSCORE 〕2
Machine Code (Concatenation):
001000 1000110000 1111 11111111 11002
Execution: Sign Extension in the Pipeline
The CPU fetches the 32-bit instruction.
The Control Unit sees the addi opcode and routes the 16-bit immediate ( 〔 〕
1111 …1100 〔UNDERSCORE 〕2
) to the Sign Extender.
The Sign Extender observes the most significant bit (bit 15) is a and pads the upper 16 bits with
ones.
Resulting 32-bit constant: 〔 〕
1111 11111111 1111 111111111111 1100〔UNDERSCORE 〕2
(which is 〔 〕
−4〔UNDERSCORE〕10
).
The ALU then calculates
s1
+ (32-bit
−4
), ensuring the subtraction is performed correctly.
Part V: I-Type in the MIPS Pipeline – A Three-Way Split
The I-Type execution path diverges significantly from the R-Type in the Execute (EX) and Memory
(MEM) stages, necessitating complex MUX (multiplexer) control by the Control Unit.
1. Control Signals for I-Type Instructions
The I-Type opcode dictates how the main control signals are set, fundamentally altering the data
path compared to the R-Type:
RegDst (Register Destination) = 0: For addi and lw, this signal selects the
rt
field (bits 20–16) as
the write-back destination register, overriding the
rd
field used by R-Type.
ALUSrc (ALU Source) = 1: This signal is crucial. It directs the ALU’s second input MUX to select the
sign-extended 32-bit immediate (from the Sign Extender) instead of the value from the Register
File’s second read port (used for
rt
in R-Type).
MemtoReg (Memory to Register): This signal controls the data source for the Write Back stage. It
is set to 1 for lw (to select data from Data Memory) and 0 for addi (to select data from the ALU).
2. Pipeline Flow Divergence
The I-Type instructions follow the first two stages (IF and ID) identically to the R-Type, but then
diverge:
Immediate Arithmetic (addi):
EX: The ALU receives the value of
rs
and the Sign-Extended immediate. It computes the
sum/result.
MEM: The instruction passes through.
WB: The ALU result is written to
rt
.
Load/Store (lw, sw):
EX: The ALU computes the memory address (
rs+sign-extended offset
).
MEM:
For lw, Data Memory is read using the calculated address.
For sw, Data Memory is written using the calculated address, and the data comes from
rt
.
WB: Only for lw, the data retrieved from memory is written to
rt
. For sw, the instruction
completes in MEM.
Branching (beq, bne):
EX: The ALU performs two functions simultaneously:
It computes the new branch target address by adding PC+4 to the shifted/extended immediate.
It performs the comparison (
rs − rt
) to check the branch condition (Zero flag).
MEM/WB: If the condition is met, the PC is updated in the IF stage of the next clock cycle with
the newly calculated branch target address. If not met, the PC continues to PC+4.
Part VI: Load/Store (I-Type) vs. General Addressing Modes
The MIPS I-Type architecture restricts memory access to only one addressing mode: base-plus-
displacement. This is another key architectural insight.
Why Only One Mode? The strict use of the I-Type format for lw and sw ensures that the hardware
always knows that the memory address will be calculated by adding the contents of a register (
rs
) and a 16-bit offset (immediate). This dramatically simplifies the ALU control logic and the
address calculation path, contributing to the fast clock speeds of RISC processors.
The Absence of Direct Addressing: MIPS lacks a simple, dedicated direct addressing mode (where
the instruction contains the full 32-bit address). To load a word from a static address like
0x10008000
, it requires two instructions:
lui
at , 0x1000 ¿
0x10000000
intothe
at register using an I-Type variant).
lw
t0,0x8000¿
at
¿¿
0x8000
, tothebase
0x10000000$).
The absence of direct addressing in a single instruction is a direct consequence of the 16-bit
immediate constraint of the I-Type format. If the instruction needed to carry a full 32-bit address,
the instruction length would need to increase, violating the fixed 32-bit mandate, or the register
fields would need to shrink, violating the 32-register design.
Part VII: Conditional Branching and PC-Relative Address Calculation
The use of the 16-bit immediate for branching is critical, but requires a precise understanding of
PC-relative logic.
1. The Power of PC-Relative Addressing
PC-relative addressing is essential for creating position-independent code (PIC). The target
address is calculated relative to the current instruction, meaning the entire program code
segment can be moved in memory without having to re-link all the branch instructions. This is a
fundamental concept in modern operating systems.
2. The Branch Offset Calculation Details
The Control Unit must perform three steps on the 16-bit immediate during the instruction cycle:
Sign Extension: Convert the 16-bit offset into a 32-bit signed value.
Shift Left 2: Multiply the offset by 4 (shift left 2) to convert the word count into a byte count,
ensuring the address is word-aligned.
Addition: Add the resulting 32-bit displacement to the
PC+4
value.
Example: Branch Calculation
Assume the following:
beq
t0,
t1, Loop_Start is located at address
0x0040002016
.
Loop_Start is located 4 instructions (16 bytes) backward from the branch instruction.
The instruction following the branch is at
PC+4=0x0040002416
.
Desired Displacement (Instructions):
−4
words.
16-bit Immediate (Encoded):
−410 →1111 1111 111111002
.
Sign Extension and Shift: The CPU calculates
Sign-Extend(11111111 1111 1100)≪2
. This
results in a 32-bit displacement of
−1610
(or
FFFFFFF 016
).
Target Address Calculation:
New PC=0x0040002416 +(−1610 )New PC=0x0040002416 −0x0000001016 New PC=0x0040001416
The new PC is set to
0x0040001416
only if
t0=t1
, successfully completing the jump to the
desired memory location.
Part VIII: Architectural Trade-offs and Conclusion
The I-Type instruction is the workhorse of the MIPS architecture. It balances the high-
performance regularity of the fixed 32-bit instruction size with the necessity of accessing
constants and memory offsets.
1. The 16-bit Limitation
The main disadvantage of the I-Type is its 16-bit immediate field, which imposes three critical
range constraints:
Load/Store Range: Only offsets within
±32
KB from the base register are possible, which is
usually sufficient for data structures and stack access but prevents single-instruction access to
global variables far away.
Immediate Value Range: Only constants within
±32767
can be used in one instruction,
necessitating the use of lui (Load Upper Immediate) and ori (OR Immediate) to synthesize larger
32-bit constants.
Branch Range: Only jumps within
±256
KB (or
±215
instructions) are possible for conditional
branches, requiring long jumps (J-Type) or multiple branches for larger code blocks.
2. The I-Type and the Compiler
The regularity of the I-Type greatly simplifies the task of the compiler. Because memory access,
immediate operations, and conditional branches are all handled by this one uniform format, the
compiler can efficiently choose the correct instruction and reliably determine which fields to
populate, leading to simpler, faster code generation.
The MIPS I-Type instruction format is the perfect illustration of RISC design trade-offs. It sacrifices
the ability to perform complex, single-cycle operations (like memory-to-memory operations
common in CISC) in favor of regularity, speed, and simplicity. By dedicating 16 bits to the
immediate, it manages to support frequent arithmetic operations, all memory addressing, and all
conditional control flow, making it the most versatile and frequently used instruction type in the
entire MIPS Instruction Set Architecture. Mastery of its three distinct functional interpretations is
non-negotiable for success in COMP 222.
