VHDL assignment,one week dead line,if u have any doubts,plz let me know,even though i am unware of those,will take help from tutor

DADDR[15:0]

XADC_DO[15:0]

DISP_DATA[0..15]

BCD_DISP[0..3]

S E

L [0

.. 1

]

AN0(U2)

AN1(U4)

AN2(V4)

AN3(W4)

C A

(W 7 )

C B

(W 6 )

C C

(U 8

) C

D (V

8 )

C E

(U 5

) C

F (V

5 )

C G

(U 7

)

DP(V7)

Reset RESET(U18)

DEN

DRDY

BUSY

EOC

SC

Clk CLK100M(W5)

Vin

tr ig

g e r

~q1

q0

XADC

VAUXP[6] J3

VAUXN[6] K3

VAUXP[7] M2

VAUXN[7] M1

VAUXP[14] L3

VAUXN[14] M3

VAUXP[15] N2

VAUXN[15] N1

RESET CONVST

ALARM

EOS EOC

BUSY

DRDY DCLK DWE DEN

DO[0..15]

DI[0..15]

DADDR[0..6]

CHANNEL[0..4]

X1

XADC

0

DADDR selects ADC status (result) register

Address of Vauxp/n[6] result register is 7'h16

ADCCLK is DCLK divided by 4 = 25MHz

disp_cntr

clock

rst an1

an2

an3

an4

s e

l[0 ..1

]

U6 DISP_CNTR

bcd2seg

a b c d e f g b

cd in

[0 .. 3 ]

dispmux

s e

l[ 0

.. 1 ]

datain[0..15]

bcd_out[0..3]

Active-low cathodes

Active-low anodes

AN3 is most-significant digit (leftmost)

JXADC

VCC GND vauxp6

vauxn6

123456

789101112

vauxp14

vauxn14

vauxp7

vauxn7

vauxp15

vauxn15

VCC GND Timer

clk

reset

Pulse

XADC_Controller

tr ig

g e r

ADC_Data_out[0..15]

ADC_Data_in[0..15]

ADC_Address[0..6]

Data_En

Data_Rdy

ADC_Busy

ADC_EOC

ADC_SC Clk

Reset

R1

10k

R2

10k

R3

10k

R4

10k

R5

10k

R6

10k

R7

10k

R8

10k

R9 20k

R10 20k

R11 20k

R12 20k

R13 20k

R14 20k

R15 20k

R16 20k

SW7 SW-SPDT

SW6 SW-SPDT

SW5 SW -SPDT

SW4 SW-SPDT

SW3 SW -SPDT

SW2 SW-SPDT

SW1 SW-SPDT

SW0 SW-SPDT

V17V16W17W15V15 W16W14W13

BTND R17

10k

R18 10k

U17 ManConv

Use push-button OR Timer

CLK

D

Q

!Q RESET SET

U3

DTFF

CLK

D

Q

!Q RESET SET

U4

DTFF

Click ‘Next’ several times until you get to the ‘Default Part’ window (see next slide)

Project name: XADC_RTL Project location: a suitable folder on your U drive

Click ‘Next’ several times until you get to the ‘Default Part’ window (see next slide)

Project name: XADC_RTL Project location: a suitable folder on your U drive

Choose ‘Basys3’ board or ‘Artix-7 xc7a35tcpg236’ FPGA part.

Click ‘Next’ then ‘Finish’ to proceed

Go to ‘Course Documents - Workshop’ and Click on ‘XADC_RTL_v2017.zip’ and extract files to the project folder on your ‘U’ drive

Drag-and-drop (or extract) all files (*.SV, *.txt and *.XDC) into project folder

This file is used for simulation

These files are design sources and a test-module.

This file is a constraints file

Add all* sources to projects by category:

All ‘SV’ sources are design sources apart from ‘testbench.sv’, which is a simulation source.

The ‘Basys3_XADC_RTL.xdc’ source file is a constraints file.

Hierarchy of project should be the same as image at right.

XADC is not yet defined

*You do not need to add the ‘design3.txt’ file to the project.

Double-click to start XADC wizard

Go to the IP repository and locate: FPGA Features and Design → XADC →XADC Wizard

Take care to check and/or alter all fields below prior to clicking on OK

See next page

Setting up the analogue simulation file Contents of ‘design3.txt’

Copy and paste full path name of file: eg. ‘/home/ian/Documents/Vivado_projects/XADC_RTL_v2017’

(yours will be different)

TIME column is absolute time in ‘ns’. Other two columns specify analogue input voltage on VAUX[6] channel. These time/value pairs are set up to match test-bench. Inputs change at intervals of 200 clock cycles (100MHz).

All check boxes unchecked. Sequencer – Of Channel Averaging – None Click OK to proceed

All alarms of

Select analogue input channel – VAUXP[6], VAUXN[6]

Check summary before clicking on OK to proceed

Click on ‘Generate’ to produce outputs.

Among these will be a Verilog model of the XADC IP block named – ‘xadc_wiz_0.v’.

module XADC_RTL_Display( input logic RESET, input logic CLK100M, input logic VAUXP6, input logic VAUXN6, output logic CA, CB, CC, CD, CE CF, CG, DP, AN0, AN1, AN2, AN3, input logic [7:0] sw, output logic [7:0] JA ); logic DEN, SC; logic DRDY, BUSY, EOC;

logic [15:0] XADC_DO; logic [6:0] DADDR;

//display signals logic [15:0] DISP_DATA; logic [3:0] bcdin; logic [1:0] sel;

logic Clk, Reset, trigger;

assign Clk = CLK100M; assign Reset = RESET;

assign JA = sw; //connect switches to R-2R DAC

xadc_wiz_0 ADC1(.convst_in(SC),.daddr_in(DADDR), .dclk_in(Clk),.den_in(DEN),.di_in(), .dwe_in(1'b0),.reset_in(Reset), .vauxp6(VAUXP6),.vauxn6(VAUXN6), .busy_out(BUSY),.channel_out(), .do_out(XADC_DO),.drdy_out(DRDY), .eoc_out(EOC),.eos_out(), .alarm_out(),.vp_in(),.vn_in());

XADC_Controller CON1(.ADC_Busy(BUSY), .ADC_EOC(EOC), .Data_Rdy(DRDY), .Data_En(DEN), .ADC_SC(SC), .ADC_Data_in(XADC_DO), .ADC_Data_out(DISP_DATA), .ADC_Address(DADDR), .*);

Timer #(.NUMCLKS(200), .n(8)) //simulation values TMR1(.Pulse(trigger), .*);

assign DP = 1'b1;

bcd2seg BCD2SEG1(.*);

dispmux DMUX1(.datain(DISP_DATA), .bcd_out(bcdin), .*);

dispcntr #(.N(2)) DCNTR1(.*); endmodule

Instantiation of XADC

Set sample interval to 200 clocks (2 us)

Set length of display counter to 2

XADC_RTL_Display.sv

testbench.sv

Lines 15 to 19: generate a 100MHz clock signal.

Lines 21 to 27: resets the system then runs for 1500 clock cycles, this is equal to 15,000 ns. The last analogue input change occurs at 11,000 ns.

Line 29: Auto-connected instance of unit-under- test (UUT).

Run Simulation → Run Behavioural Simulation

VAUXP[6]

0.0 0.2

0.4 0.6

0.8 0.99

ADC Data = Vin/(1.0/4096)

Detail showing one conversion

XADC_Controller.sv

xadc_wiz_0 ADC1(.convst_in(SC),.daddr_in(DADDR), .dclk_in(Clk),.den_in(DEN),.di_in(), .dwe_in(1'b0),.reset_in(Reset), .vauxp6(VAUXP6),.vauxn6(VAUXN6), .busy_out(BUSY),.channel_out(), .do_out(XADC_DO),.drdy_out(DRDY), .eoc_out(EOC),.eos_out(), .alarm_out(),.vp_in(),.vn_in());

XADC_Controller CON1(.ADC_Busy(BUSY), .ADC_EOC(EOC), .Data_Rdy(DRDY), .Data_En(DEN), .ADC_SC(SC), .ADC_Data_in(XADC_DO), .ADC_Data_out(DISP_DATA), .ADC_Address(DADDR), .*);

Timer #(.NUMCLKS(1000000), .n(20)) //simulation values TMR1(.Pulse(trigger), .*);

assign DP = 1'b1;

bcd2seg BCD2SEG1(.*);

dispmux DMUX1(.datain(DISP_DATA), .bcd_out(bcdin), .*);

dispcntr #(.N(20)) DCNTR1(.*); endmodule

Instantiation of XADC

Set sample interval to 1000000 clocks (10 ms)

Set length of display counter to 20

Prepare design for Implementation

R-2R DAC input switches

RESET Manual Convert

Digital Display (HEX)

Vin

Gnd