digital designs
fahadhero
VHDLlibrary.ziplab3/.DS_Store
__MACOSX/lab3/._.DS_Store
lab3/DESIGN3.vhd
-- DESIGN3.vhd -------------------------------------------------------------------------- -------------------------------------------------------------------------- -------------------------------------------------------------------------- library IEEE,WORK; use IEEE.STD_LOGIC_1164.ALL; use WORK.ALL; entity DESIGN3 is --vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv-- port( A,B,C: in std_logic; F,G,H,I,J,K,L,M: out std_logic); --^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^-- end; architecture STRUCTURAL_ARCH of DESIGN3 is -- component declarative region component AND_3 port ( A,B,C : in std_logic ; Z : out std_logic ); end component; -- signal declarative region begin -- component instance and wiring region -- instances and wiring for circuit F CKT_F_G1 : AND_3 port map (A => A, B => B, C => C , Z => F); -- instances and wiring for circuit G -- instances and wiring for circuit H -- instances and wiring for circuit I -- instances and wiring for circuit J -- instances and wiring for circuit K -- instances and wiring for circuit L -- instances and wiring for circuit M end;
__MACOSX/lab3/._DESIGN3.vhd
lab3/EE 2000 lab 3.pdf
1
EE 2000 Lab 3
The main objective of this lab is for you to design and simulate logic circuits made of basic gates (AND, OR, NAND, NOR, XOR, XNOR, BUF and NOT gates). To do this, you will make use a library of basic gates and wire some of the gates together to implement the functions from lab 1. Note: in lab 1, you wrote out an equation using and, or, and not functions to implement the functions in the truth tables. This lab is similar to lab 2 except, you have additional gates you can use to minimize the number of literals in each equation. In lab2, you could only use AND, OR and NOT functions. For this lab you have the additional gates, NAND, NOR, XOR, and XNOR. For this lab, you will minimize the number of literals in the equations using any of the gates in the library. You will simulate your resulting circuits, and show they give the same results you got when simulating the truth tables in lab 1 and the AND, OR, NOT circuits from lab2. The TA will check you off when you have completed the lab. The library (LIB.vhd), design file (DESIGN3.vhd), and test bench file (tb_DESIGN3.vhd) are provided. You will simulate these the same way you simulated circuits in lab 0, lab 1 and lab2.
__MACOSX/lab3/._EE 2000 lab 3.pdf
lab3/LIB.vhd
-- Library for EE2000 Projects -- Included Gate List: -- BUF_1 -- INV_1 -- AND_2 -- AND_3 -- AND_4 -- AND_5 -- AND_6 -- OR_2 -- OR_3 -- OR_4 -- OR_5 -- OR_6 -- NAND_2 -- NAND_3 -- NAND_4 -- NOR_2 -- NOR_3 -- NOR_4 -- XOR_2 -- XNOR_2 --------------------------------- -- BUF_1 Gate Definition library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity BUF_1 is port(A : in std_logic; Z : out std_logic); end; architecture BEHAV of BUF_1 is begin Z <= not(not(A)); end; --------------------------------- -- INV_1 Gate Definition library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity INV_1 is port(A : in std_logic; Z : out std_logic); end; architecture BEHAV of INV_1 is begin Z <= not(A); end; --------------------------------- -- AND_2 Gate Definition library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity AND_2 is port(A,B : in std_logic; Z : out std_logic); end; architecture BEHAV of AND_2 is begin Z <= A and B; end; --------------------------------- -- AND_3 Gate Definition library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity AND_3 is port(A,B,C : in std_logic; Z : out std_logic); end; architecture BEHAV of AND_3 is begin Z <= A and B and C; end; --------------------------------- -- AND_4 Gate Definition library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity AND_4 is port(A,B,C,D : in std_logic; Z : out std_logic); end; architecture BEHAV of AND_4 is begin Z <= A and B and C and D; end; --------------------------------- -- AND_5 Gate Definition library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity AND_5 is port(A,B,C,D,E : in std_logic; Z : out std_logic); end; architecture BEHAV of AND_5 is begin Z <= A and B and C and D and E; end; --------------------------------- -- AND_6 Gate Definition library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity AND_6 is port(A,B,C,D,E,F : in std_logic; Z : out std_logic); end; architecture BEHAV of AND_6 is begin Z <= A and B and C and D and E and F; end; --------------------------------- -- OR_2 Gate Definition library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity OR_2 is port(A,B : in std_logic; Z : out std_logic); end; architecture BEHAV of OR_2 is begin Z <= A or B; end; --------------------------------- -- OR_3 Gate Definition library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity OR_3 is port(A,B,C : in std_logic; Z : out std_logic); end; architecture BEHAV of OR_3 is begin Z <= A or B or C; end; --------------------------------- -- OR_4 Gate Definition library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity OR_4 is port(A,B,C,D : in std_logic; Z : out std_logic); end; architecture BEHAV of OR_4 is begin Z <= A or B or C or D; end; --------------------------------- -- OR_5 Gate Definition library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity OR_5 is port(A,B,C,D,E : in std_logic; Z : out std_logic); end; architecture BEHAV of OR_5 is begin Z <= A or B or C or D or E; end; --------------------------------- -- OR_6 Gate Definition library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity OR_6 is port(A,B,C,D,E,F : in std_logic; Z : out std_logic); end; architecture BEHAV of OR_6 is begin Z <= A or B or C or D or E or F; end; --------------------------------- -- NAND_2 Gate Definition library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity NAND_2 is port(A,B : in std_logic; Z : out std_logic); end; architecture BEHAV of NAND_2 is begin Z <= not(A and B); end; --------------------------------- -- NAND_3 Gate Definition library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity NAND_3 is port(A,B,C : in std_logic; Z : out std_logic); end; architecture BEHAV of NAND_3 is begin Z <= not(A and B and C); end; --------------------------------- -- NAND_4 Gate Definition library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity NAND_4 is port(A,B,C,D : in std_logic; Z : out std_logic); end; architecture BEHAV of NAND_4 is begin Z <= not(A and B and C and D); end; --------------------------------- -- NOR_2 Gate Definition library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity NOR_2 is port(A,B : in std_logic; Z : out std_logic); end; architecture BEHAV of NOR_2 is begin Z <= not(A or B); end; --------------------------------- -- NOR_3 Gate Definition library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity NOR_3 is port(A,B,C : in std_logic; Z : out std_logic); end; architecture BEHAV of NOR_3 is begin Z <= not(A or B or C); end; --------------------------------- -- NOR_4 Gate Definition library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity NOR_4 is port(A,B,C,D : in std_logic; Z : out std_logic); end; architecture BEHAV of NOR_4 is begin Z <= not(A or B or C or D); end; --------------------------------- -- XOR_2 Gate Definition library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity XOR_2 is port(A,B : in std_logic; Z : out std_logic); end; architecture BEHAV of XOR_2 is begin Z <= A xor B; end; --------------------------------- -- XNOR_2 Gate Definition library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity XNOR_2 is port(A,B : in std_logic; Z : out std_logic); end; architecture BEHAV of XNOR_2 is begin Z <= not(A xor B); end; ---------------------------------
__MACOSX/lab3/._LIB.vhd
lab3/tb_DESIGN3.vhd
-- tb_DESIGN3.vhd library IEEE,STD,WORK; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; --use IEEE.STD_LOGIC_SIGNED.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.STD_LOGIC_TEXTIO.ALL; use STD.TEXTIO.ALL; use IEEE.MATH_REAL.ALL; entity TB_DESIGN3 is end ; architecture TB of TB_DESIGN3 is component DESIGN3 --vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv-- port(A,B,C: in std_logic; F,G,H,I,J,K,L,M: out std_logic); --^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^-- end component ; --vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv-- signal At,Bt,Ct,Ft,Gt,Ht,It,Jt,Kt,Lt,Mt:std_logic; --^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^-- begin CUT:DESIGN3 -- Circuit Under Test port map (A=>At,B=>Bt,C=>Ct,F=>Ft,G=>Gt,H=>Ht,I=>It,J=>Jt,K=>Kt,L=>Lt,M=>Mt); test_VECTOR : process begin -- exhuastive test for truth table function --vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv-- At <= '0'; Bt <= '0'; Ct <= '0'; wait for 1 ns; At <= '0'; Bt <= '0'; Ct <= '1'; wait for 1 ns; At <= '0'; Bt <= '1'; Ct <= '0'; wait for 1 ns; At <= '0'; Bt <= '1'; Ct <= '1'; wait for 1 ns; At <= '1'; Bt <= '0'; Ct <= '0'; wait for 1 ns; At <= '1'; Bt <= '0'; Ct <= '1'; wait for 1 ns; At <= '1'; Bt <= '1'; Ct <= '0'; wait for 1 ns; At <= '1'; Bt <= '1'; Ct <= '1'; wait for 1 ns; --^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^-- -- stop simulation using the following line: assert (false) report "sim done! :)" severity FAILURE; end process; end ; configuration CFG_TB of TB_DESIGN3 is for TB end for; end ;
