Computer Architecture Final Research Paper (4-6 pages) Final Senior Paper

CSC 468 Computer Architecture – Term Paper.

Research Paper: Deadline for Submission: Wednesday April 20, 2021 by Class Time (Graduating Students)

Other Students: Sunday May 01, 2022

The paper will deal with the evolution of computer technology.

Course Goal/Objective

From any available source(s) you can find, you will research and describe how any of the concepts or topics in the “LIST OF TOPICS” section of this assignment have evolved over the past 25 years to improve computer system performance.

Instructions

In this short research paper, you will investigate the evolution of and current trends in improving system performance with regards to any concept of your chosen but selected from the LIST OF TOPICS section herein.

In this paper, you must, carry out some original research in a group of two or three students to write a paper based on your investigation of an area within computer architecture (see LIST OF TOPICS section).

A minimum of four references are required for this paper (but could be more). At least one article should be from a peer-reviewed journal. If you use Web sites other than the article databases provided by Norfolk State Library in your research, be sure to evaluate the content you find there for authority, accuracy, coverage, and currency.

Submission of Paper (Deliverables)

Submit your paper as a Word document in your Term Paper Assignments folder in Blackboard.

I will pay a great deal of attention to your thesis statement, the concise but logical flow of your information, your conclusion, and your grammar and syntax.  

Submitted papers that show evidence of plagiarism will be sent to the Dean's office for review.

Your paper should have no spelling or grammatical mistakes, and the construction should be logical and easy to read. These are research papers, and should not contain colloquial or slang expressions. Use in-text citations where necessary and provide a reference list at the end of the paper. Use a minimum of four outside references.

Your papers are due by Wednesday April 20, 2021 by Class Time (Graduating Students)

Other Students: Sunday May 01, 2022

. Late papers will not be accepted, and no excuses!

Format and length

Your paper should be written using APA style. It should be no more than six pages long, but no less than four pages long (i.e. body of the paper excluding the Title and Reference pages). The font size should be 12 point, with one-inch margins and double spacing.

Oral Presentation

An oral presentation of your paper is required. We will schedule these towards the last day of class this semester. This should be viewed as an opportunity for presenting research results to your "peers" -- an important part of the research process that should be of interest to those wishing to pursue a Master’s degree in CS.

Grading Criteria

The total number of points for this activity will be set to 100. Elements of the paper will be assessed as follows and should be used as your guide while working on your topic and writing of your paper:

 The following Rubric will be used in evaluating the quality of your work.

 Name(s):___________________________________   

 

Points-->	4	3	2	1
Coverage of the assigned task; attention to requirements	Excellent coverage; many good insights	Good coverage; relevant topics addressed	Adequate; some gaps	Inadequate; important details missing
Development of ideas; persuasive of argument	Persuasive; good ideas and strong development	Good ideas but need better development	Some ideas, but evidence is weak	Some ideas stated, but not supported
Ability to distinguish pertinent from irrelevant information in source materials	Excellent focus on pertinent information	Selective, but some irrelevant information	Very little awareness evident	No distinction at all
Ability to synthesize previous readings and discuss in terms of new material	Excellent Synthesis	Some synthesis, but needs further development	Very little synthesis	No synthesis at all
Organization of the paper; manner of presentation	Excellent; ideas flow logically	Acceptable; not outstanding	Serious organizational problems	No organization
Wording and phrasing	Clear with precise wording	Clear, but some awkwardness	Frequently ambiguous or vague	Confused
Grammar and sentence structure	Very good	Adequate	Some errors	Poor
Mechanics: Spelling, typing, errors, punctuation, etc.	Very few errors	Some errors	Frequent errors	Careless
In-text Citations	Very few errors	Some errors	Frequent errors	Not Evident
Reference/Bibliography	Very few errors	Some errors	Frequent errors	Not Evident

 

Total Points Earned:                               __________________________

 

Percentage: (100%)                                        __________________________

 

General Comment:                                         ___________________________________________________

                                                           ___________________________________________________

 

___________________________________________________

 

LIST OF TOPICS

To help you with topics, a list of example research projects or topics are as follows.

Group 1:

· Micro-architectural techniques for reducing power consumption. Powering down (using clock and/or power gating) function units, cache banks, etc.

· Techniques for improving reliability and/or fault tolerance. Relevant papers describe Diva and Slipstream processors.

· Comparisons of different instruction level parallelism methods, for example, vectors versus superscalar; or VLIW versus superscalar,

· pipeline clocking and modeling, perhaps taking the granularity of pipeline stages into account.

· study new DRAM interfaces (e.g., Synchronous DRAM, RamBus and RamLink); consider their performance and how they might affect processor and system implementations.

· instruction set enhancements and their effect on performance (e.g., update-mode addressing, conditional register-to-register moves, and multiply-add instructions),

· Attempt to quantify how much of processor performance gain in the past decade has come from faster clocks and how much from ILP.

· methods for predicting multiple branches in a single cycle,

· cache implementations, especially non-blocking caches – design methods and performance,

· cache enhancements, including victim caches, stream buffers, and hash addressing,

· prefetching methods (hardware and/or software) and their impact on performance

· architectural characteristics of database workloads

· cache behavior of database (or other) applications or algorithms, with algorithm modification to exploit caches and memory hierarchies

· characterizing the execution behavior of applications (e.g., a database application) on an out-of-order superscalar processor

· predicated execution and its impact on performance

Other Possible Survey Topics

Group 2:

Describe, compare and contrast (generally broader than the above research topics):

· compiler transformations to improve pipeline/superscalar performance

· compiler transformations to improve memory behavior,

· new memory technologies and their potential impact on architecture

· the effect changing technology on architecture (e.g., flash memories and fiber optics),

· high-performance I/O (e.g., RAIDs and ATM networks),

· comparison of the ARM/LEG V8 with other instruction set architectures,

· the history of some aspect of computer architecture (e.g., stored-programs, caches, virtual memory, pipelining, microcode, protection, dataflow machines)

Other Possible Researchable Project Topics

Group 3:

· An implementation study of register renaming logic

· In-order vs out-of-order superscalar processors

· A study of dynamic branch prediction schemes for superscalar processors

· Performance study of two-level on-chip caches in a fixed area

· An analysis of hardware prefetching techniques

· Performance evaluation of caches using patchwrx instruction traces

· A survey of different approaches to achieve instruction level parallelism

· Skewed D-way K-column set associative caches

· The history and use of pipelining computer architecture

· The effect of context switching on history-based branch predictors

· Bounding worst-case performance for real-time applications

· Branch prediction methods and performance

· Performance of TLB implementations

· Trace-driven simulation of cache enhancements

· Timing analysis and caching for real-time systems

· A Survey of VLIW Processors

· Evaluating Caches with Multiple Caching Strategies

· Survey/Comparison of VLIW and Superscalar processors

· Comparison Study of Multimedia-Extended Microprocessors

· Synchronous DRAM

· Cache Performance Study of the SPEC95 Benchmark Suite

· An Investigation of Instruction Fetch Behavior in Microprocessors

· The Picojava I Microprocessor and Implementation Decisions

· Register Renaming in Java Microprocessors

· Optimizing Instruction Cache Performance with Profile-directed Code Layout

· Simulation of a Victim Cache for Spec95 Integer Benchmarks

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