Device Usage Page (usage_statistics_webtalk.html)

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software_version_and_target_device
betaFALSE build_version1756540
date_generatedTue Dec 08 00:15:49 2020 os_platformWIN64
product_versionVivado v2016.4 (64-bit) project_id333767c07429409e879d0c37344d8523
project_iteration22 random_iddb1b1cf2cf975a809c41605973f32b90
registration_iddb1b1cf2cf975a809c41605973f32b90 route_designTRUE
target_devicexc7a35t target_familyartix7
target_packagecpg236 target_speed-1
tool_flowVivado

user_environment
cpu_nameIntel(R) Core(TM) i7-7700HQ CPU @ 2.80GHz cpu_speed2808 MHz
os_nameMicrosoft Windows 8 or later , 64-bit os_releasemajor release (build 9200)
system_ram17.000 GB total_processors1

vivado_usage
java_command_handlers
addsources=22 closeproject=1 coreview=5 customizecore=7
debugwizardcmdhandler=2 editdelete=8 editpaste=1 editundo=2
newproject=1 openexample=1 openhardwaremanager=2 openproject=3
projectsettingscmdhandler=3 recustomizecore=3 reporttimingsummary=1 runbitgen=44
runimplementation=4 runsynthesis=18 savedesign=5 savefileproxyhandler=16
settargetconstrfile=1 showproductguide=2 showview=26 simulationbreak=19
simulationrelaunch=11 simulationrestart=19 simulationrun=8 simulationrunall=20
toolsoptions=1 toolstemplates=2 viewlayoutcmd=2 viewtaskprojectmanager=4
viewtaskrtlanalysis=1 viewtasksynthesis=3 waveformsaveconfiguration=3
other_data
guimode=16
project_data
constraintsetcount=1 core_container=false currentimplrun=impl_1 currentsynthesisrun=synth_1
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=2 export_simulation_ies=2
export_simulation_modelsim=2 export_simulation_questa=2 export_simulation_riviera=2 export_simulation_vcs=2
export_simulation_xsim=2 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=34 simulator_language=VHDL srcsetcount=13 synthesisstrategy=Vivado Synthesis Defaults
target_language=VHDL target_simulator=XSim totalimplruns=3 totalsynthesisruns=3

unisim_transformation
post_unisim_transformation
bufg=1 carry4=52 fdce=128 fdpe=2
fdre=106 gnd=12 ibuf=7 lut1=107
lut2=112 lut3=19 lut4=11 lut5=37
lut6=32 mmcme2_adv=1 muxf7=3 obuf=11
vcc=12 xadc=1
pre_unisim_transformation
bufg=1 carry4=52 fdce=128 fdpe=2
fdre=106 gnd=12 ibuf=7 lut1=107
lut2=112 lut3=19 lut4=11 lut5=37
lut6=32 mmcme2_adv=1 muxf7=3 obuf=11
vcc=12 xadc=1

power_opt_design
command_line_options_spo
-cell_types=default::all -clocks=default::[not_specified] -exclude_cells=default::[not_specified] -include_cells=default::[not_specified]
usage
bram_ports_augmented=0 bram_ports_newly_gated=0 bram_ports_total=2 flow_state=default
slice_registers_augmented=0 slice_registers_newly_gated=0 slice_registers_total=1783 srls_augmented=0
srls_newly_gated=0 srls_total=120

ip_statistics
clk_wiz_v5_3_3_0/1
clkin1_period=10.0 clkin2_period=10.0 clock_mgr_type=NA component_name=clk_wiz_0
core_container=NA enable_axi=0 feedback_source=FDBK_AUTO feedback_type=SINGLE
iptotal=1 manual_override=false num_out_clk=1 primitive=MMCM
use_dyn_phase_shift=false use_dyn_reconfig=false use_inclk_stopped=false use_inclk_switchover=false
use_locked=false use_max_i_jitter=false use_min_o_jitter=false use_phase_alignment=false
use_power_down=false use_reset=true
labtools_ila_v6_00_a/1
all_probe_same_mu=true all_probe_same_mu_cnt=1 c_adv_trigger=false c_data_depth=1024
c_en_strg_qual=false c_input_pipe_stages=0 c_num_of_probes=3 c_probe0_type=0
c_probe0_width=4 c_probe1_type=0 c_probe1_width=4 c_probe2_type=0
c_probe2_width=1 c_trigin_en=0 c_trigout_en=0 component_name=u_ila_0_CV
core_container=NA iptotal=1
labtools_xsdbm_v2_00_a/1
c_bscan_mode=false c_bscan_mode_with_core=false c_clk_input_freq_hz=300000000 c_enable_clk_divider=false
c_num_bscan_master_ports=0 c_two_prim_mode=false c_use_ext_bscan=false c_user_scan_chain=1
c_xsdb_num_slaves=1 component_name=dbg_hub_CV core_container=NA iptotal=1
xadc_wiz_v3_3_2/1
channel_averaging=None component_name=xadc_wiz_0 core_container=false dclk_frequency=100
enable_axi=false enable_axi4stream=false enable_busy=true enable_convst=false
enable_convstclk=false enable_dclk=true enable_drp=true enable_eoc=true
enable_eos=true enable_vbram_alaram=false enable_vccaux_alaram=falseenable_vccpaux_alaram=false enable_vccddro_alaram=false
enable_vccint_alaram=false enable_vccpint_alaram=false iptotal=1 ot_alaram=false
sequencer_mode=off startup_channel_selection=single_channel timing_mode=continuous user_temp_alaram=false

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified] -return_string=default::[not_specified]
-ruledecks=default::[not_specified] -upgrade_cw=default::[not_specified]
results
cfgbvs-1=1 rtstat-10=1

report_methodology
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified] -return_string=default::[not_specified]
results
pdrc-190=14 timing-18=17

report_power
command_line_options
-advisory=default::[not_specified] -append=default::[not_specified] -file=[specified] -format=default::text
-hier=default::power -l=default::[not_specified] -name=default::[not_specified] -no_propagation=default::[not_specified]
-return_string=default::[not_specified] -rpx=[specified] -verbose=default::[not_specified] -vid=default::[not_specified]
-xpe=default::[not_specified]
usage
airflow=250 (LFM) ambient_temp=25.0 (C) bi-dir_toggle=12.500000 bidir_output_enable=1.000000
board_layers=12to15 (12 to 15 Layers) board_selection=medium (10"x10") bram=0.000334 clocks=0.007591
confidence_level_clock_activity=High confidence_level_design_state=High confidence_level_device_models=High confidence_level_internal_activity=Medium
confidence_level_io_activity=Low confidence_level_overall=Low customer=TBD customer_class=TBD
devstatic=0.071986 die=xc7a35tcpg236-1 dsp_output_toggle=12.500000 dynamic=0.119067
effective_thetaja=5.0 enable_probability=0.990000 family=artix7 ff_toggle=12.500000
flow_state=routed heatsink=medium (Medium Profile) i/o=0.000882 input_toggle=12.500000
junction_temp=26.0 (C) logic=0.001229 mgtavcc_dynamic_current=0.000000 mgtavcc_static_current=0.000000
mgtavcc_total_current=0.000000 mgtavcc_voltage=1.000000 mgtavtt_dynamic_current=0.000000 mgtavtt_static_current=0.000000
mgtavtt_total_current=0.000000 mgtavtt_voltage=1.200000 mmcm=0.105861 netlist_net_matched=NA
off-chip_power=0.000000 on-chip_power=0.191054 output_enable=1.000000 output_load=5.000000
output_toggle=12.500000 package=cpg236 pct_clock_constrained=3.000000 pct_inputs_defined=14
platform=nt64 process=typical ram_enable=50.000000 ram_write=50.000000
read_saif=False set/reset_probability=0.000000 signal_rate=False signals=0.001230
simulation_file=None speedgrade=-1 static_prob=False temp_grade=commercial
thetajb=7.5 (C/W) thetasa=4.6 (C/W) toggle_rate=False user_board_temp=25.0 (C)
user_effective_thetaja=5.0 user_junc_temp=26.0 (C) user_thetajb=7.5 (C/W) user_thetasa=4.6 (C/W)
vccadc_dynamic_current=0.000800 vccadc_static_current=0.020000 vccadc_total_current=0.020800 vccadc_voltage=1.800000
vccaux_dynamic_current=0.058609 vccaux_io_dynamic_current=0.000000 vccaux_io_static_current=0.000000 vccaux_io_total_current=0.000000
vccaux_io_voltage=1.800000 vccaux_static_current=0.012631 vccaux_total_current=0.071239 vccaux_voltage=1.800000
vccbram_dynamic_current=0.000019 vccbram_static_current=0.000176 vccbram_total_current=0.000196 vccbram_voltage=1.000000
vccint_dynamic_current=0.011367 vccint_static_current=0.009775 vccint_total_current=0.021142 vccint_voltage=1.000000
vcco12_dynamic_current=0.000000 vcco12_static_current=0.000000 vcco12_total_current=0.000000 vcco12_voltage=1.200000
vcco135_dynamic_current=0.000000 vcco135_static_current=0.000000 vcco135_total_current=0.000000 vcco135_voltage=1.350000
vcco15_dynamic_current=0.000000 vcco15_static_current=0.000000 vcco15_total_current=0.000000 vcco15_voltage=1.500000
vcco18_dynamic_current=0.000000 vcco18_static_current=0.000000 vcco18_total_current=0.000000 vcco18_voltage=1.800000
vcco25_dynamic_current=0.000000 vcco25_static_current=0.000000 vcco25_total_current=0.000000 vcco25_voltage=2.500000
vcco33_dynamic_current=0.000226 vcco33_static_current=0.001000 vcco33_total_current=0.001226 vcco33_voltage=3.300000
version=2016.4 xadc=0.001940

report_utilization
clocking
bufgctrl_available=32 bufgctrl_fixed=0 bufgctrl_used=2 bufgctrl_util_percentage=6.25
bufhce_available=72 bufhce_fixed=0 bufhce_used=0 bufhce_util_percentage=0.00
bufio_available=20 bufio_fixed=0 bufio_used=0 bufio_util_percentage=0.00
bufmrce_available=10 bufmrce_fixed=0 bufmrce_used=0 bufmrce_util_percentage=0.00
bufr_available=20 bufr_fixed=0 bufr_used=0 bufr_util_percentage=0.00
mmcme2_adv_available=5 mmcme2_adv_fixed=0 mmcme2_adv_used=1 mmcme2_adv_util_percentage=20.00
plle2_adv_available=5 plle2_adv_fixed=0 plle2_adv_used=0 plle2_adv_util_percentage=0.00
dsp
dsps_available=90 dsps_fixed=0 dsps_used=0 dsps_util_percentage=0.00
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_ii=0
diff_hstl_ii_18=0 diff_hsul_12=0 diff_mobile_ddr=0 diff_sstl135=0
diff_sstl135_r=0 diff_sstl15=0 diff_sstl15_r=0 diff_sstl18_i=0
diff_sstl18_ii=0 hstl_i=0 hstl_i_18=0 hstl_ii=0
hstl_ii_18=0 hsul_12=0 lvcmos12=0 lvcmos15=0
lvcmos18=0 lvcmos25=0 lvcmos33=1 lvds_25=0
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl135=0 sstl135_r=0
sstl15=0 sstl15_r=0 sstl18_i=0 sstl18_ii=0
tmds_33=0
memory
block_ram_tile_available=50 block_ram_tile_fixed=0 block_ram_tile_used=0.5 block_ram_tile_util_percentage=1.00
ramb18_available=100 ramb18_fixed=0 ramb18_used=1 ramb18_util_percentage=1.00
ramb18e1_only_used=1 ramb36_fifo_available=50 ramb36_fifo_fixed=0 ramb36_fifo_used=0
ramb36_fifo_util_percentage=0.00
primitives
bscane2_functional_category=Others bscane2_used=1 bufg_functional_category=Clock bufg_used=2
carry4_functional_category=CarryLogic carry4_used=81 fdce_functional_category=Flop & Latch fdce_used=299
fdpe_functional_category=Flop & Latch fdpe_used=42 fdre_functional_category=Flop & Latch fdre_used=1433
fdse_functional_category=Flop & Latch fdse_used=9 ibuf_functional_category=IO ibuf_used=7
lut1_functional_category=LUT lut1_used=43 lut2_functional_category=LUT lut2_used=219
lut3_functional_category=LUT lut3_used=196 lut4_functional_category=LUT lut4_used=147
lut5_functional_category=LUT lut5_used=263 lut6_functional_category=LUT lut6_used=382
mmcme2_adv_functional_category=Clock mmcme2_adv_used=1 muxf7_functional_category=MuxFx muxf7_used=12
obuf_functional_category=IO obuf_used=11 ramb18e1_functional_category=Block Memory ramb18e1_used=1
ramd32_functional_category=Distributed Memory ramd32_used=36 rams32_functional_category=Distributed Memory rams32_used=12
srl16e_functional_category=Distributed Memory srl16e_used=54 srlc16e_functional_category=Distributed Memory srlc16e_used=2
srlc32e_functional_category=Distributed Memory srlc32e_used=64 xadc_functional_category=Others xadc_used=1
slice_logic
f7_muxes_available=16300 f7_muxes_fixed=0 f7_muxes_used=12 f7_muxes_util_percentage=0.07
f8_muxes_available=8150 f8_muxes_fixed=0 f8_muxes_used=0 f8_muxes_util_percentage=0.00
lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=24 lut_as_logic_available=20800 lut_as_logic_fixed=0
lut_as_logic_used=1094 lut_as_logic_util_percentage=5.26 lut_as_memory_available=9600 lut_as_memory_fixed=0
lut_as_memory_used=100 lut_as_memory_util_percentage=1.04 lut_as_shift_register_fixed=0 lut_as_shift_register_used=76
register_as_flip_flop_available=41600 register_as_flip_flop_fixed=0 register_as_flip_flop_used=1783 register_as_flip_flop_util_percentage=4.29
register_as_latch_available=41600 register_as_latch_fixed=0 register_as_latch_used=0 register_as_latch_util_percentage=0.00
slice_luts_available=20800 slice_luts_fixed=0 slice_luts_used=1194 slice_luts_util_percentage=5.74
slice_registers_available=41600 slice_registers_fixed=0 slice_registers_used=1783 slice_registers_util_percentage=4.29
fully_used_lut_ff_pairs_fixed=4.29 fully_used_lut_ff_pairs_used=76 lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=24
lut_as_logic_available=20800 lut_as_logic_fixed=0 lut_as_logic_used=1094 lut_as_logic_util_percentage=5.26
lut_as_memory_available=9600 lut_as_memory_fixed=0 lut_as_memory_used=100 lut_as_memory_util_percentage=1.04
lut_as_shift_register_fixed=0 lut_as_shift_register_used=76 lut_ff_pairs_with_one_unused_flip_flop_fixed=76 lut_ff_pairs_with_one_unused_flip_flop_used=455
lut_ff_pairs_with_one_unused_lut_output_fixed=455 lut_ff_pairs_with_one_unused_lut_output_used=512 lut_flip_flop_pairs_available=20800 lut_flip_flop_pairs_fixed=0
lut_flip_flop_pairs_used=635 lut_flip_flop_pairs_util_percentage=3.05 slice_available=8150 slice_fixed=0
slice_used=563 slice_util_percentage=6.91 slicel_fixed=0 slicel_used=404
slicem_fixed=0 slicem_used=159 unique_control_sets_used=125 using_o5_and_o6_fixed=125
using_o5_and_o6_used=44 using_o5_output_only_fixed=44 using_o5_output_only_used=4 using_o6_output_only_fixed=4
using_o6_output_only_used=28
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_used=1 bscane2_util_percentage=25.00
capturee2_available=1 capturee2_fixed=0 capturee2_used=0 capturee2_util_percentage=0.00
dna_port_available=1 dna_port_fixed=0 dna_port_used=0 dna_port_util_percentage=0.00
efuse_usr_available=1 efuse_usr_fixed=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_used=0 frame_ecce2_util_percentage=0.00
icape2_available=2 icape2_fixed=0 icape2_used=0 icape2_util_percentage=0.00
pcie_2_1_available=1 pcie_2_1_fixed=0 pcie_2_1_used=0 pcie_2_1_util_percentage=0.00
startupe2_available=1 startupe2_fixed=0 startupe2_used=0 startupe2_util_percentage=0.00
xadc_available=1 xadc_fixed=0 xadc_used=1 xadc_util_percentage=100.00

router
usage
actual_expansions=1397671 bogomips=0 bram18=1 bram36=0
bufg=0 bufr=0 congestion_level=0 ctrls=125
dsp=0 effort=2 estimated_expansions=1541832 ff=1783
global_clocks=2 high_fanout_nets=2 iob=18 lut=1252
movable_instances=3544 nets=3870 pins=19204 pll=0
router_runtime=0.000000 router_timing_driven=1 threads=2 timing_constraints_exist=1

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -directive=default::default -fanout_limit=default::10000 -flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto -gated_clock_conversion=default::off -generic=default::[not_specified] -include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified] -max_bram=default::-1 -max_bram_cascade_height=default::-1 -max_dsp=default::-1
-max_uram=default::-1 -max_uram_cascade_height=default::-1 -mode=default::default -name=default::[not_specified]
-no_lc=default::[not_specified] -no_srlextract=default::[not_specified] -no_timing_driven=default::[not_specified] -part=xc7a35tcpg236-1
-resource_sharing=default::auto -retiming=default::[not_specified] -rtl=default::[not_specified] -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] -seu_protect=default::none -shreg_min_size=default::3 -top=Basys3_Milestone2
-verilog_define=default::[not_specified]
usage
elapsed=00:00:24s hls_ip=0 memory_gain=415.691MB memory_peak=643.070MB

tclstore
usage
catalog_refresh_count=5

xsim
command_line_options
-sim_mode=behavioral -sim_type=default::