xpm_cdc.sv,systemverilog,xil_defaultlib,../../../home/DeXin/Workdir/EDATools/Vivado16_4/Vivado/2016.4/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../A7_Seg.srcs/sources_1/ip/clk_wiz_0"
xpm_VCOMP.vhd,vhdl,xpm,../../../home/DeXin/Workdir/EDATools/Vivado16_4/Vivado/2016.4/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../../A7_Seg.srcs/sources_1/ip/clk_wiz_0"
clk_wiz_0_sim_netlist.vhdl,vhdl,xil_defaultlib,../../../../A7_Seg.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl,incdir="../../../../A7_Seg.srcs/sources_1/ip/clk_wiz_0"
glbl.v,Verilog,xil_defaultlib,glbl.v
