Computer Engineering Question

CMPEN331  –  Quiz  4  (July  20th,  2018)  

Section:               Major:  

Name:               Email:    

1.   (20  points)  We  found  that  the  instruction  fetch  and  memory  stages  are  the  critical  path  of  our  5-­‐stage  pipelined   MIPS  CPU.  Therefore,  we  changed  the  IF  and  MEM  stages  to  take  two  cycles  while  increasing  the  clock  rate.  You   can  assume  that  the  register  file  is  written  at  the  falling  edge  of  the  clock.    

 

 

Assume  that  no  pipelining  optimizations  have  been  made,  and  that  branch  comparisons  are  made  by  the  ALU.  Here’s   how  our  pipeline  looks  when  executing  two  add  instructions:    

 

Clock  Cycle  #   1   2   3   4   5   6   7   8  

add $t0, $t1, $t2 IF1 IF2 ID EX MEM1 MEM2 WB

add $t3, $t4, $t5 IF1 IF2 ID EX MEM1 MEM2 WB

  Make  sure  you  take  a  careful  look  at  the  above  diagram  before  answering  the  following  questions:    

1.   (5  points)  How  many  stalls  would  a  data  hazard  between  back-­‐to-­‐back  instructions  require?      

 

 

 

 

2.   (5  points)  How  many  stalls  would  be  needed  after  a  branch  instruction?      

 

 

 

 

3.   Suppose  the  old  clock  period  was  150  ns  and  the  new  clock  period  is  now  100ns.  Would  our  processor  have  a   significant  speedup  executing  a  large  chunk  of  code…      

i.   (5  points)  Without  any  pipelining  hazards?  Explain  your  answer  in  1-­‐2  sentences.      

 

 

 

 

ii.   (5  points)  With  50%  of  the  code  containing  back-­‐to-­‐back  data  hazards?  Explain  your  answer  in  1-­‐2   sentences.