ECE171 Project

ECE 171

Spring 2018

Project 2

Build an 8-bit ripple carry Adder/Subtractor. It will have 2 8-bit wide addends (A, B) and 1 8-bit wide

result (F). It will have 1 1-bit wide select input (S) that determines whether the design should add (S=0)

or subtract (S=1). It will also still have 1-bit wide CarryIn and CarryOut bits. When Adding, the result will

be the sum of A + B + CI and the CO bit will be valid. When Subtracting, the machine simply provide the

result of A-B.

S F CO

0 A+B+CI valid

1 A-B Invalid (Don’t Care)

Design using dataflow and hierchary; you do not need to draw a schematic. First, make and exhaustively

test a single bit wide adder. Then instantiate the adder, along with some additional logic, to create the

8-bit wide Adder/Subtractor.

Use the testbench from the course web site to test it. Note how the testbench instantiates the 8- bit

comparator so that your module defines the ports correctly!

module AdderSubtractor (S, A, B, CarryIn, CarryOut, F)

input [7:0] A, B; input S, CarryIn; output [7:0] F; output CarryOut;

Your Verilog programs must be compiled and simulated. Save and print the simulator timing diagrams so

that you can include it in your final report.

This final report must include:

1. A brief problem description

a. The problem your circuit solves

b. Specific requirements

2. The project deliverables (exactly what you are generating)

3. Approach/methodology (the steps you will take to solve the problem)

4. Your design work (including black and grey boxes)

5. Verilog source code listings (for all designs and testbenches)

6. Timing diagrams

7. Show the simulation output produced by my testbench for your 8-bit model but do NOT submit

the timing diagram from simulating the 8-bit model.