Design a multi-cycle implementation of the reduced MIPS architecture
casi
sourcecodefromtext.zipsource_codes/c/endian_pointer.c
/************************************************ The C code example shown here is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ main () { // endian_pointer.c int n = 0x76543210; // a word if (*(unsigned char *)&n == 0x10) // char starting address printf("little endian\n"); // stored 0x10 else printf("big endian\n"); // stored 0x76 }
source_codes/c/endian_union.c
/************************************************ The C code example shown here is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ main() { // endian_union.c union { // union: int intword; // to assess a word unsigned char characters[sizeof (int)]; // with different names } u; // union u u.intword = 0x76543210; // access as an integer if (u.characters[sizeof (int) - 1] == 0x76) // access as array of byte printf("little endian\n"); // high byte in high address else printf("big endian\n"); // high byte in low address }
source_codes/c/f2i.c
/************************************************ The C code example shown here is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ #include <stdio.h> // f2i.c, x86 FPU float to int test #define Chop_disable_exception \ asm volatile("fldcw _RoundChop_disable_exception") // write control word int _RoundChop_disable_exception = 0x1c3f; // mask exceptions #define Read_fp_state_word \ asm volatile("fstsw _fp_state_word") // read state word int _fp_state_word; // FPU state #define Clear_exceptions_of_sw \ asm volatile("fclex") // clear state int main (void) { union { int intword; float floatword; } u; int d; while (1) { fprintf (stderr,"input a float number in hex format: "); fscanf (stdin,"%x",&u.intword); // read an fp number Chop_disable_exception; // mask exceptions Clear_exceptions_of_sw; // clear state d = u.floatword; // f2i fprintf (stderr,"f = %08x = %0.6f\n", u.intword, u.floatword); fprintf (stderr,"d = %08x = %08d\n", d, d); // display integer Read_fp_state_word; // read FPU state fprintf (stderr,"fp_state_word = %04X\n",_fp_state_word); } }
source_codes/c/fadd_test.c
/************************************************ The C code example shown here is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ #include <stdio.h> // fadd_test.c, rounding test #define Near asm volatile("fldcw _RoundNear") #define Down asm volatile("fldcw _RoundDown") #define Up asm volatile("fldcw _RoundUp") #define Chop asm volatile("fldcw _RoundChop") int _RoundNear = 0x103f; // round code = 00 round to nearest int _RoundDown = 0x143f; // round code = 01 round toward -infinity int _RoundUp = 0x183f; // round code = 10 round toward +infinity int _RoundChop = 0x1c3f; // round code = 11 round toward 0 int main(void){ union { int intword; float floatword; } u, v, s, t; while (1) { fprintf (stderr,"input 1st fp number in hex format: "); fscanf (stdin,"%x",&u.intword); fprintf (stderr,"input 2nd fp number in hex format: "); fscanf (stdin,"%x",&v.intword); Near; // round to nearest s.floatword = u.floatword + v.floatword; t.floatword = u.floatword - v.floatword; fprintf (stderr,"the sum of 2 fp numbers is (near): " "%08x\t%08x\n",s.intword,t.intword); Down; // round toward -infinity s.floatword = u.floatword + v.floatword; t.floatword = u.floatword - v.floatword; fprintf (stderr,"the sum of 2 fp numbers is (down): " "%08x\t%08x\n",s.intword,t.intword); Up; // round toward +infinity s.floatword = u.floatword + v.floatword; t.floatword = u.floatword - v.floatword; fprintf (stderr,"the sum of 2 fp numbers is ( up ): " "%08x\t%08x\n",s.intword,t.intword); Chop; // round toward 0 s.floatword = u.floatword + v.floatword; t.floatword = u.floatword - v.floatword; fprintf (stderr,"the sum of 2 fp numbers is (chop): " "%08x\t%08x\n",s.intword,t.intword); } }
source_codes/c/fmul_test.c
/************************************************ The C code example shown here is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ #include<stdio.h> // fmul_test.c, rounding test #define Near asm volatile("fldcw _RoundNear") #define Down asm volatile("fldcw _RoundDown") #define Up asm volatile("fldcw _RoundUp") #define Chop asm volatile("fldcw _RoundChop") int _RoundNear = 0x103f; // round code = 00 round to nearest int _RoundDown = 0x143f; // round code = 01 round toward -infinity int _RoundUp = 0x183f; // round code = 10 round toward +infinity int _RoundChop = 0x1c3f; // round code = 11 round toward 0 int main(void){ union { int intword; float floatword; } u, v, s; while (1) { fprintf (stderr,"input 1st f_p number in hex format: "); fscanf (stdin,"%x",&u.intword); fprintf (stderr,"input 2nd f_p number in hex format: "); fscanf (stdin,"%x",&v.intword); Near; // round to nearest s.floatword = u.floatword * v.floatword; fprintf (stderr,"the prod of 2 fp numbers is (near): " "%08x\n",s.intword); Down; // round toward -infinity s.floatword = u.floatword * v.floatword; fprintf (stderr,"the prod of 2 fp numbers is (down): " "%08x\n",s.intword); Up; // round toward +infinity s.floatword = u.floatword * v.floatword; fprintf (stderr,"the prod of 2 fp numbers is ( up ): " "%08x\n",s.intword); Chop; // round toward 0 s.floatword = u.floatword * v.floatword; fprintf (stderr,"the prod of 2 fp numbers is (chop): " "%08x\n",s.intword); } }
source_codes/c/font_show.c
/************************************************ The C code example shown here is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ #include <stdio.h> // display ascii font shape extern unsigned char Font[][8]; // 128 - 32 = 96 characters main() { int chars_per_line = 16; // fit to book text width int char_no; unsigned char char_row_bitmap; int row, col; int i; for (char_no = 0; char_no < 96; char_no += chars_per_line) { for (row = 0; row < 8; row++) { for (i = 0; i < chars_per_line; i++) { if ((char_no + i) < 96) { char_row_bitmap = Font[char_no + i][row]; for (col = 7; col >= 0; col--) { if (((char_row_bitmap >> col) & 1) == 1) { printf ("O"); // a dot } else { printf (" "); // blank } } } } printf ("\n"); // next row } } }
source_codes/c/font8.c
/************************************************ The C code example shown here is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ const unsigned char Font[][8] = { /* char ascii */ {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}, /* <SPACE> 20 */ {0x18,0x18,0x18,0x18,0x00,0x18,0x18,0x00}, /* ! 21 */ {0x6c,0x6c,0x48,0x00,0x00,0x00,0x00,0x00}, /* " 22 */ {0x6c,0x6c,0xfe,0x6c,0xfe,0x6c,0x6c,0x00}, /* # 23 */ {0x18,0x7e,0xd8,0x7e,0x1b,0x7e,0x18,0x00}, /* $ 24 */ {0x62,0x66,0x0c,0x18,0x30,0x66,0x46,0x00}, /* % 25 */ {0x38,0x6c,0x68,0x76,0xdc,0xcc,0x76,0x00}, /* & 26 */ {0x18,0x18,0x30,0x00,0x00,0x00,0x00,0x00}, /* ' 27 */ {0x0c,0x18,0x30,0x30,0x30,0x18,0x0c,0x00}, /* ( 28 */ {0x30,0x18,0x0c,0x0c,0x0c,0x18,0x30,0x00}, /* ) 29 */ {0x00,0x6c,0x38,0xfe,0x38,0x6c,0x00,0x00}, /* * 2a */ {0x00,0x18,0x18,0x7e,0x18,0x18,0x00,0x00}, /* + 2b */ {0x00,0x00,0x00,0x00,0x00,0x18,0x18,0x10}, /* , 2c */ {0x00,0x00,0x00,0x7e,0x00,0x00,0x00,0x00}, /* - 2d */ {0x00,0x00,0x00,0x00,0x00,0x18,0x18,0x00}, /* . 2e */ {0x02,0x06,0x0c,0x18,0x30,0x60,0x40,0x00}, /* / 2f */ {0x3c,0x66,0x6e,0x76,0x66,0x66,0x3c,0x00}, /* 0 30 */ {0x18,0x18,0x38,0x18,0x18,0x18,0x3c,0x00}, /* 1 31 */ {0x7c,0x06,0x06,0x3c,0x60,0x60,0x7c,0x00}, /* 2 32 */ {0x7c,0x06,0x06,0x3c,0x06,0x06,0x7c,0x00}, /* 3 33 */ {0x66,0x66,0x66,0x7e,0x06,0x06,0x06,0x00}, /* 4 34 */ {0x7e,0x60,0x60,0x7c,0x06,0x06,0x7c,0x00}, /* 5 35 */ {0x3c,0x60,0x60,0x7c,0x66,0x66,0x3c,0x00}, /* 6 36 */ {0x7e,0x06,0x0c,0x18,0x18,0x18,0x18,0x00}, /* 7 37 */ {0x3c,0x66,0x66,0x3c,0x66,0x66,0x3c,0x00}, /* 8 38 */ {0x3c,0x66,0x66,0x3e,0x06,0x06,0x3c,0x00}, /* 9 39 */ {0x00,0x18,0x18,0x00,0x18,0x18,0x00,0x00}, /* : 3a */ {0x00,0x00,0x18,0x18,0x00,0x18,0x18,0x10}, /* ; 3b */ {0x0c,0x18,0x30,0x60,0x30,0x18,0x0c,0x00}, /* < 3c */ {0x00,0x00,0x7e,0x00,0x7e,0x00,0x00,0x00}, /* = 3d */ {0x30,0x18,0x0c,0x06,0x0c,0x18,0x30,0x00}, /* > 3e */ {0x3c,0x66,0x06,0x1c,0x18,0x00,0x18,0x00}, /* ? 3f */ {0x3c,0x66,0x6e,0x6a,0x6e,0x60,0x3e,0x00}, /* @ 40 */ {0x3c,0x66,0x66,0x7e,0x66,0x66,0x66,0x00}, /* A 41 */ {0x7c,0x66,0x66,0x7c,0x66,0x66,0x7c,0x00}, /* B 42 */ {0x3c,0x66,0x60,0x60,0x60,0x66,0x3c,0x00}, /* C 43 */ {0x7c,0x66,0x66,0x66,0x66,0x66,0x7c,0x00}, /* D 44 */ {0x7e,0x60,0x60,0x7c,0x60,0x60,0x7e,0x00}, /* E 45 */ {0x7e,0x60,0x60,0x7c,0x60,0x60,0x60,0x00}, /* F 46 */ {0x3c,0x66,0x60,0x6e,0x66,0x66,0x3c,0x00}, /* G 47 */ {0x66,0x66,0x66,0x7e,0x66,0x66,0x66,0x00}, /* H 48 */ {0x3c,0x18,0x18,0x18,0x18,0x18,0x3c,0x00}, /* I 49 */ {0x3e,0x0c,0x0c,0x0c,0x0c,0x6c,0x38,0x00}, /* J 4a */ {0x66,0x6c,0x78,0x70,0x78,0x6c,0x66,0x00}, /* K 4b */ {0x60,0x60,0x60,0x60,0x60,0x60,0x7e,0x00}, /* L 4c */ {0xc6,0xee,0xfe,0xd6,0xc6,0xc6,0xc6,0x00}, /* M 4d */ {0x66,0x66,0x76,0x7e,0x6e,0x66,0x66,0x00}, /* N 4e */ {0x3c,0x66,0x66,0x66,0x66,0x66,0x3c,0x00}, /* O 4f */ {0x7c,0x66,0x66,0x7c,0x60,0x60,0x60,0x00}, /* P 50 */ {0x3c,0x66,0x66,0x66,0x6e,0x66,0x3e,0x00}, /* Q 51 */ {0x7c,0x66,0x66,0x7c,0x66,0x66,0x66,0x00}, /* R 52 */ {0x3e,0x60,0x60,0x3c,0x06,0x06,0x7c,0x00}, /* S 53 */ {0x7e,0x18,0x18,0x18,0x18,0x18,0x18,0x00}, /* T 54 */ {0x66,0x66,0x66,0x66,0x66,0x66,0x3c,0x00}, /* U 55 */ {0x66,0x66,0x66,0x66,0x3c,0x3c,0x18,0x00}, /* V 56 */ {0xc6,0xc6,0xd6,0xd6,0xfe,0xee,0x44,0x00}, /* W 57 */ {0x66,0x66,0x3c,0x18,0x3c,0x66,0x66,0x00}, /* X 58 */ {0x66,0x66,0x66,0x3c,0x18,0x18,0x18,0x00}, /* Y 59 */ {0x7e,0x06,0x0c,0x18,0x30,0x60,0x7e,0x00}, /* Z 5a */ {0x3c,0x30,0x30,0x30,0x30,0x30,0x3c,0x00}, /* [ 5b */ {0x40,0x60,0x30,0x18,0x0c,0x06,0x02,0x00}, /* \ 5c */ {0x3c,0x0c,0x0c,0x0c,0x0c,0x0c,0x3c,0x00}, /* ] 5d */ {0x10,0x38,0x6c,0x00,0x00,0x00,0x00,0x00}, /* ^ 5e */ {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xff}, /* _ 5f */ {0x18,0x18,0x0c,0x00,0x00,0x00,0x00,0x00}, /* ` 60 */ {0x00,0x00,0x3c,0x06,0x3e,0x66,0x3a,0x00}, /* a 61 */ {0x60,0x60,0x7c,0x66,0x66,0x66,0x7c,0x00}, /* b 62 */ {0x00,0x00,0x3c,0x66,0x60,0x66,0x3c,0x00}, /* c 63 */ {0x06,0x06,0x3e,0x66,0x66,0x66,0x3e,0x00}, /* d 64 */ {0x00,0x00,0x3c,0x66,0x7c,0x60,0x3c,0x00}, /* e 65 */ {0x0e,0x18,0x18,0x3e,0x18,0x18,0x18,0x00}, /* f 66 */ {0x00,0x00,0x3e,0x66,0x66,0x3e,0x06,0x3c}, /* g 67 */ {0x60,0x60,0x7c,0x66,0x66,0x66,0x66,0x00}, /* h 68 */ {0x18,0x00,0x18,0x18,0x18,0x18,0x18,0x00}, /* i 69 */ {0x18,0x00,0x18,0x18,0x18,0x18,0x18,0x70}, /* j 6a */ {0x60,0x60,0x66,0x6c,0x78,0x6c,0x66,0x00}, /* k 6b */ {0x30,0x30,0x30,0x30,0x30,0x30,0x1c,0x00}, /* l 6c */ {0x00,0x00,0xcc,0xfe,0xd6,0xc6,0xc6,0x00}, /* m 6d */ {0x00,0x00,0x7c,0x66,0x66,0x66,0x66,0x00}, /* n 6e */ {0x00,0x00,0x3c,0x66,0x66,0x66,0x3c,0x00}, /* o 6f */ {0x00,0x00,0x7c,0x66,0x66,0x7c,0x60,0x60}, /* p 70 */ {0x00,0x00,0x3e,0x66,0x66,0x3e,0x06,0x06}, /* q 71 */ {0x00,0x00,0x36,0x38,0x30,0x30,0x30,0x00}, /* r 72 */ {0x00,0x00,0x3e,0x60,0x3c,0x06,0x7c,0x00}, /* s 73 */ {0x18,0x18,0x3c,0x18,0x18,0x18,0x0c,0x00}, /* t 74 */ {0x00,0x00,0x66,0x66,0x66,0x66,0x3c,0x00}, /* u 75 */ {0x00,0x00,0x66,0x66,0x66,0x3c,0x18,0x00}, /* v 76 */ {0x00,0x00,0xc6,0xd6,0xd6,0x7c,0x28,0x00}, /* w 77 */ {0x00,0x00,0x66,0x3c,0x18,0x3c,0x66,0x00}, /* x 78 */ {0x00,0x00,0x66,0x66,0x66,0x3e,0x06,0x7c}, /* y 79 */ {0x00,0x00,0x7e,0x0c,0x18,0x30,0x7e,0x00}, /* z 7a */ {0x1c,0x30,0x30,0x60,0x30,0x30,0x1c,0x00}, /* { 7b */ {0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x00}, /* | 7c */ {0x38,0x0c,0x0c,0x06,0x0c,0x0c,0x38,0x00}, /* } 7d */ {0x00,0x32,0x4c,0x00,0x00,0x00,0x00,0x00}, /* ~ 7e */ {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff} /* <DEL> 7f */ };
source_codes/c/function_call.c
/************************************************ The C code example shown here is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ int sum(int *array, int n) { // subroutine_call.c int i; int total = 0; for (i = 0; i < n; i++) { total += array[i]; // sum of n array elements } return(total); // return sum } int main() { int a[] = {1, 2, 3}; // initialize the array printf ("The sum is %d\n", sum(a, 3)); // call subroutine return(0); }
source_codes/c/gen_font_table_v.c
/************************************************ The C code example shown here is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ #include <stdio.h> // gen_font_table_v.c, generate font table (verilog HDL) extern unsigned char Font[][8]; main() { unsigned char char_row_bitmap; int addr = 0; int char_no, i, j; printf ("module font_table (a,d);\n"); printf (" input [12:0] a; // 8*8*128=2^3*2^3*2^7\n"); printf (" output d; // font dot\n"); printf (" wire rom [0:8191];\n"); printf (" assign d = rom[a];\n\n"); for (char_no = 0; char_no < 128; char_no++) { for (i = 0; i < 8; i++) { // 8 rows per char if (char_no >= 0x20) { // <space> char_row_bitmap = Font[char_no - 0x20][i]; } else { char_row_bitmap = 0; } for (j = 7; j >= 0; j--) { // 8 pixels per row printf (" assign rom[13'h%04x] = ", addr++); if (((char_row_bitmap >> j) & 1) == 1) { printf ("1;\n"); // a dot } else { printf ("0;\n"); // blank } } } } printf ("endmodule\n"); }
source_codes/c/mul_by_shift.c
/************************************************ The C code example shown here is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ #include <stdio.h> // mul_by_shift.c unsigned int mul16 (unsigned int x, unsigned int y) { // mul by shift unsigned int a, b, c; // c = a * b unsigned int i; // counter a = x; // multiplicand b = y; // multiplier c = 0; // product for (i = 0; i < 16; i++) { // for 16 bits if ((b & 1) == 1) { // LSB of b is 1 c += a; // c = c + a } a = a << 1; // shift a 1-bit left b = b >> 1; // shift b 1-bit right } return(c); // return product } main() { unsigned int x,y; fprintf(stderr,"input 1st 16-bit unsigned integer in hex: "); fscanf(stdin,"%x",&x); fprintf(stderr,"input 2nd 16-bit unsigned integer in hex: "); fscanf(stdin,"%x",&y); x &= 0xffff; // 16 bits y &= 0xffff; // 16 bits fprintf(stderr,"%04x * %04x = %08x\n", x, y, mul16(x, y)); }
source_codes/c/pointer.c
/************************************************ The C code example shown here is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ main() { // pointer.c int num; // an integer variable num int *ptr; // a pointer variable ptr pointing to num num = 1; // let the value of num be a 1 ptr = # // let the value of ptr be the address of num printf ("The address of num is %p\n", ptr); // print ptr out }
source_codes/c/root_nonrestoring.c
/************************************************ The C code example shown here is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ // Non-Restoring Square Root, Copyright by Yamin Li, [email protected] #include <stdio.h> // root_nonrestoring.c unsigned squart(unsigned d, int *remainder) { unsigned q = 0; // q: 16-bit root int r = 0; // r: 17-bit remainder int i; for (i = 15; i >= 0; i-- ) { printf("%02d: q=%04x ",i,q); if (r >= 0) { r = ((r << 2) | ((d >> (i+i)) & 3)) - ((q << 2) | 1); // -q01 printf("r=((r<<2)|((d>>(i+i))&3))-((q<<2)|1)=%08x ",r); } else { r = ((r << 2) | ((d >> (i+i)) & 3)) + ((q << 2) | 3); // +q11 printf("r=((r<<2)|((d>>(i+i))&3))+((q<<2)|3)=%08x ",r); } if (r >= 0) {q = (q << 1) | 1; printf("q=q*2+1=%04x\n",q);} else {q = (q << 1) | 0; printf("q=q*2+0=%04x\n",q);} } if (r < 0) {r = r + ((q << 1) | 1);} // remainder adjusting *remainder = r; // return remainder return(q); // return root } int main(void){ unsigned radicand, root; int remainder; printf("Input an unsigned integer in hex (ex. c0000000): d = "); scanf("%x", &radicand); // read a radicand root = squart(radicand, & remainder); printf("hex: q = %08x, r = %08x, d = q*q + r = %08x\n", root,remainder,root*root + remainder); printf("dec: q = %08d, r = %08d, d = q*q + r = %08u\n", root,remainder,root*root + remainder); }
source_codes/c/subroutine_call.c
/************************************************ The C code example shown here is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ int sum(int *array, int n) { // subroutine_call.c int i; int total = 0; for (i = 0; i < n; i++) { total += array[i]; // sum of n array elements } return(total); // return sum } int main() { int a[] = {1, 2, 3}; // initialize the array printf ("The sum is %d\n", sum(a, 3)); // call subroutine return(0); }
source_codes/hex/cpu_cache_tlb_0.hex
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source_codes/hex/cpu_cache_tlb_1.hex
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source_codes/hex/cpu_cache_tlb_2.hex
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source_codes/hex/cpu_cache_tlb_3.hex
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source_codes/hex/data_mem.hex
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source_codes/hex/inst_mem.hex
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source_codes/hex/mcmem.hex
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source_codes/hex/scd_intr.hex
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source_codes/hex/sci_intr.hex
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source_codes/java/logic.java
source_codes/java/logic.java
/*****************************************************
The Java code example shown here is from the book
Computer Principles and Design in Verilog HDL
by Yamin Li, published by A JOHN WILEY & SONS
*****************************************************/
// javac logic.java
// java logic
class
logic
{
public
static
void
main
(
String
[]
args
)
{
int
a
=
0x5
;
int
b
=
0xc
;
int
f_and
=
a
&
b
;
int
f_or
=
a
|
b
;
int
f_not
=
~
a
;
int
f_nand
=
~
(
a
&
b
);
int
f_nor
=
~
(
a
|
b
);
int
f_xor
=
a
^
b
;
int
f_xnor
=
~
(
a
^
b
);
System
.
out
.
format
(
"a = 0x%08x\n"
,
a
);
System
.
out
.
format
(
"b = 0x%08x\n"
,
b
);
System
.
out
.
format
(
"f_and = 0x%08x\n"
,
f_and
);
System
.
out
.
format
(
"f_or = 0x%08x\n"
,
f_or
);
System
.
out
.
format
(
"f_not = 0x%08x\n"
,
f_not
);
System
.
out
.
format
(
"f_nand = 0x%08x\n"
,
f_nand
);
System
.
out
.
format
(
"f_nor = 0x%08x\n"
,
f_nor
);
System
.
out
.
format
(
"f_xor = 0x%08x\n"
,
f_xor
);
System
.
out
.
format
(
"f_xnor = 0x%08x\n"
,
f_xnor
);
}
}
source_codes/mif/cpu_cache_tlb_0.mif
%****************************************************% % The MIF code example shown here is from the book % % Computer Principles and Design in Verilog HDL % % by Yamin Li, published by A JOHN WILEY & SONS % %****************************************************% DEPTH = 128; % Memory depth and width are required % WIDTH = 32; % Enter a decimal number % ADDRESS_RADIX = HEX; % Address and value radixes are optional % DATA_RADIX = HEX; % Enter BIN, DEC, HEX, or OCT; unless % CONTENT % otherwise specified, radixes = HEX % BEGIN % physical address = 0x0000_0000 % % reset entry, va = 0x8000_0000 % 0: 08000070; %(80000000) j initialize_itlb # jump to init itlb % 1: 00000000; %(80000004) nop % % exc_base: # exception handlerentry % 2: 401a6800; %(80000008) mfc0 $26, c0_cause # read cp0 cause reg % 3: 335a001c; %(8000000c) andi $26, $26, 0x1c # get exccode, 3 bits % 4: 3c1b8000; %(80000010) lui $27, 0x8000 # % 5: 037ad825; %(80000014) or $27, $27, $26 # % 6: 8f7b0040; %(80000018) lw $27, j_table($27)# get addr from j table % 7: 00000000; %(8000001c) nop # % 8: 03600008; %(80000020) jr $27 # jump to that address % 9: 00000000; %(80000024) nop # % [a..f]: 0; % j_table: # address table for exception and interrupt % 10: 80000000; %(80000040) int_entry # 0. address for interrupt % 11: 80000000; %(80000044) sys_entry # 1. address for syscall % 12: 80000000; %(80000048) uni_entry # 2. address for unimpl. inst. % 13: 80000000; %(8000004c) ovf_entry # 3. address for overflow % 14: 800000c0; %(80000050) itlb_entry # 4. address for itlb miss % 15: 80000140; %(80000054) dtlb_entry # 5. address for dtlb miss % 16: 80000000; %(80000058) % 17: 80000000; %(8000005c) % [18..2f]: 0; % itlb_entry: % 30: 3c1b8000; %(800000c0) lui $27, 0x8000 # 0x800001f8: counter % 31: 8f7a01f8; %(800000c4) lw $26, 0x1f8($27) # load itlb index counter % 32: 235a0001; %(800000c8) addi $26, $26, 1 # index + 1 % 33: 335a0007; %(800000cc) andi $26, $26, 7 # 3-bit index % 34: af7a01fc; %(800000d0) sw $26, 0x1fc($27) # store index % 35: 3c1b0000; %(800000d4) lui $27, 0x0000 # itlb tag % 36: 037ad025; %(800000d8) or $26, $27, $26 # itlb tag and index % 37: 409a0000; %(800000dc) mtc0 $26, c0_index # move to cp0 index % 38: 401b2000; %(800000e0) mfc0 $27, c0_context # address of pte % 39: 8f7a0000; %(800000e4) lw $26, 0x0($27) # pte % 3a: 409a1000; %(800000e8) mtc0 $26, c0_entry_lo # move to cp0 entry_lo % 3b: 001bd280; %(800000ec) sll $26, $27, 10 # get bad vpn % 3c: 001ad302; %(800000f0) srl $26, $26, 12 # for cp0 entry_hi % 3d: 409a4800; %(800000f4) mtc0 $26, c0_entry_hi # move to entry_hi % 3e: 42000002; %(800000f8) tlbwi # update itlb % 3f: 42000018; %(800000fc) eret # return from exception % 40: 00000000; %(80000100) nop # % [41..4f]: 0; % dtlb_entry: % 50: 3c1b8000; %(80000140) lui $27, 0x8000 # 0x800001fc: counter % 51: 8f7a01fc; %(80000144) lw $26, 0x1fc($27) # load dtlb index counter % 52: 235a0001; %(80000148) addi $26, $26, 1 # index + 1 % 53: 335a0007; %(8000014c) andi $26, $26, 7 # 3-bit index % 54: af7a01fc; %(80000150) sw $26, 0x1fc($27) # store index % 55: 3c1b4000; %(80000154) lui $27, 0x4000 # dtlb tag % 56: 037ad025; %(80000158) or $26, $27, $26 # dtlb tag and index % 57: 409a0000; %(8000015c) mtc0 $26, c0_index # move to cp0 index % 58: 401b2000; %(80000160) mfc0 $27, c0_context # address of pte % 59: 8f7a0000; %(80000164) lw $26, 0x0($27) # pte % 5a: 409a1000; %(80000168) mtc0 $26, c0_entry_lo # move to cp0 entry_lo % 5b: 001bd280; %(8000016c) sll $26, $27, 10 # get bad vpn % 5c: 001ad302; %(80000170) srl $26, $26, 12 # for cp0 entry_hi % 5d: 409a4800; %(80000174) mtc0 $26, c0_entry_hi # move to entry_hi % 5e: 42000002; %(80000178) tlbwi # update dtlb % 5f: 42000018; %(8000017c) eret # return from exception % 60: 00000000; %(80000180) nop # % [61..6f]: 0; % initialize_itlb: % 70: 40800000; %(800001c0) mtc0 $0, c0_index # c0_index <-- 0 (itlb[0]) % 71: 3c1b9000; %(800001c4) lui $27, 0x9000 # page table base % 72: 8f7a0000; %(800001c8) lw $26, 0x0($27) # 1st entry of page table % 73: 409a1000; %(800001cc) mtc0 $26, c0_entry_lo # c0_entrylo <-- v,d,c,pfn % 74: 3c1a0000; %(800001d0) lui $26, 0x0 # va (=0) for c0_entry_hi % 75: 409a4800; %(800001d4) mtc0 $26, c0_entry_hi # c0_entry_hi <-- vpn (0) % 76: 42000002; %(800001d8) tlbwi # write itlb for user prog % 77: 409b2000; %(800001dc) mtc0 $27, c0_context # c0_context <-- ptebase % 78: 341a003f; %(800001e0) ori $26, $0, 0x3f # enable exceptions % 79: 409a6000; %(800001e4) mtc0 $26, c0_status # c0_status <-- 0..0111111 % 7a: 3c010000; %(800001e8) lui $1, 0x0 # va = 0x0000_0000 % 7b: 00200008; %(800001ec) jr $1 # jump to user program % 7c: 00000000; %(800001f0) nop # % 7d: 00000000; %(800001f4) nop # % 7e: 00000000; %(800001f8) .data 0 # itlb index counter % 7f: 00000000; %(800001fc) .data 0 # dtlb index counter % END ;
source_codes/mif/cpu_cache_tlb_1.mif
%****************************************************% % The MIF code example shown here is from the book % % Computer Principles and Design in Verilog HDL % % by Yamin Li, published by A JOHN WILEY & SONS % %****************************************************% DEPTH = 128; % Memory depth and width are required % WIDTH = 32; % Enter a decimal number % ADDRESS_RADIX = HEX; % Address and value radixes are optional % DATA_RADIX = HEX; % Enter BIN, DEC, HEX, or OCT; unless % CONTENT % otherwise specified, radixes = HEX % BEGIN % physical address = 0x1000_0000 % % page table, va = 0x9000_0000 % 0: 00820000; %(90000000) va: 00000000 --> pa: 20000000; 1 of 8: valid bit % 1: 00820002; %(90000004) va: 00001000 --> pa: 20002000; 1 of 8: valid bit % 2: 00820001; %(90000008) va: 00002000 --> pa: 20001000; 1 of 8: valid bit % 3: 008200f0; %(9000000c) va: 00003000 --> pa: 200f0000; 1 of 8: valid bit % [4..7f]: 00000000; END ;
source_codes/mif/cpu_cache_tlb_2.mif
%****************************************************% % The MIF code example shown here is from the book % % Computer Principles and Design in Verilog HDL % % by Yamin Li, published by A JOHN WILEY & SONS % %****************************************************% DEPTH = 128; % Memory depth and width are required % WIDTH = 32; % Enter a decimal number % ADDRESS_RADIX = HEX; % Address and value radixes are optional % DATA_RADIX = HEX; % Enter BIN, DEC, HEX, or OCT; unless % CONTENT % otherwise specified, radixes = HEX % BEGIN % physical address = 0x2000_0000 % % test program va = 0x0000_0000 % 0: 20011100; %(00000000) addi $1, $0,0x1100 # address of data[0] % 1: c4200000; %(00000004) lwc1 f0, 0x0($1) # load fp data % 2: c4210050; %(00000008) lwc1 f1, 0x50($1) # load fp data % 3: c4220054; %(0000000c) lwc1 f2, 0x54($1) # load fp data % 4: c4230058; %(00000010) lwc1 f3, 0x58($1) # load fp data % 5: c424005c; %(00000014) lwc1 f4, 0x5c($1) # load fp data % 6: 46002100; %(00000018) add.s f4, f4, f0 # f4: stall 1 % 7: 460418c1; %(0000001c) sub.s f3, f3, f4 # f4: stall 2 % 8: 46022082; %(00000020) mul.s f2, f4, f2 # mul % 9: 46040842; %(00000024) mul.s f1, f1, f4 # mul % a: e4210070; %(00000028) swc1 f1, 0x70($1) # f1: stall 1 % b: e4220074; %(0000002c) swc1 f2, 0x74($1) # store fp data % c: e4230078; %(00000030) swc1 f3, 0x78($1) # store fp data % d: e424007c; %(00000034) swc1 f4, 0x7c($1) # store fp data % e: 20020004; %(00000038) addi $2, $0, 4 # counter % f: c4230000; %(0000003c)l3: lwc1 f3, 0x0($1) # load fp data % 10: c4210050; %(00000040) lwc1 f1, 0x50($1) # load fp data % 11: 46030840; %(00000044) add.s f1, f1, f3 # stall 1 % 12: 46030841; %(00000048) sub.s f1, f1, f3 # stall 2 % 13: e4210030; %(0000004c) swc1 f1, 0x30($1) # stall 1 % 14: c4051104; %(00000050) lwc1 f5,0x1104($0) # load fp data % 15: c4061108; %(00000054) lwc1 f6,0x1108($0) # load fp data % 16: c408110c; %(00000058) lwc1 f8,0x110c($0) # load fp data % 17: 460629c3; %(0000005c) div.s f7, f5, f6 # div % 18: 46004244; %(00000060) sqrt.s f9, f8 # sqrt % 19: 46004a84; %(00000064) sqrt.s f10, f9 # sqrt % 1a: 2042ffff; %(00000068) addi $2, $2, -1 # counter - 1 % 1b: 1440fff3; %(0000006c) bne $2, $0, l3 # finish? % 1c: 20210004; %(00000070) addi $1, $1, 4 # address+4, delay slot % 1d: 3c010000; %(00000074)iu_test: lui $1, 0 # address of data[0] % 1e: 34241150; %(00000078) ori $4, $1, 0x1150 # address of data[0] % 1f: 0c000038; %(0000007c)call: jal sum # call function % 20: 20050004; %(00000080)dslot1: addi $5,$0,4 # delyed slot(ds) % 21: ac820000; %(00000084)return: sw $2, 0($4) # store result % 22: 8c890000; %(00000088) lw $9, 0($4) # check sw % 23: 01244022; %(0000008c) sub $8, $9, $4 # sub: $8 <-- $9 - $4 % 24: 20050003; %(00000090) addi $5, $0, 3 # counter % 25: 20a5ffff; %(00000094)loop2: addi $5,$5,-1 # counter - 1 % 26: 34a8ffff; %(00000098) ori $8, $5, 0xffff # zero-extend: 0000ffff % 27: 39085555; %(0000009c) xori $8, $8, 0x5555 # zero-extend: 0000aaaa % 28: 2009ffff; %(000000a0) addi $9, $0, -1 # sign-extend: ffffffff % 29: 312affff; %(000000a4) andi $10, $9,0xffff # zero-extend: 0000ffff % 2a: 01493025; %(000000a8) or $6, $10, $9 # or: ffffffff % 2b: 01494026; %(000000ac) xor $8, $10, $9 # xor: ffff0000 % 2c: 01463824; %(000000b0) and $7, $10, $6 # and: 0000ffff % 2d: 10a00003; %(000000b4) beq $5, $0, shift # if $5 = 0, goto shift % 2e: 00000000; %(000000b8)dslot2: nop # ds % 2f: 08000025; %(000000bc) j loop2 # jump loop2 % 30: 00000000; %(000000c0)dslot3: nop # ds % 31: 2005ffff; %(000000c4)shift: addi $5,$0,-1 # $5 = ffffffff % 32: 000543c0; %(000000c8) sll $8, $5, 15 # << 15 = ffff8000 % 33: 00084400; %(000000cc) sll $8, $8, 16 # << 16 = 80000000 % 34: 00084403; %(000000d0) sra $8, $8, 16 # >>> 16 = ffff8000 % 35: 00084c32; %(000000d4) srl $8, $8, 15 # >> 15 = 0001ffff % 36: 08000036; %(000000d8)finish: j finish # dead loop % 37: 00000000; %(000000dc)dslot4: nop # ds % 38: 00004020; %(000000e0)sum: add $8, $0, $0 # sum % 39: 8c890000; %(000000e4)loop: lw $9, 0($4) # load data % 3a: 01094020; %(000000e8) add $8, $8, $9 # sum % 3b: 20a5ffff; %(000000ec) addi $5, $5, -1 # counter - 1 % 3c: 14a0fffc; %(000000f0) bne $5, $0, loop # finish? % 3d: 20840004; %(000000f4)dslot5: addi $4, $4, 4 # address + 4, ds % 3e: 03e00008; %(000000f8) jr $31 # return % 3f: 00081000; %(000000fc)dslot6: sll $2, $8, 0 # move res. to v0, ds % [40..7f]: 0; END ;
source_codes/mif/cpu_cache_tlb_3.mif
%****************************************************% % The MIF code example shown here is from the book % % Computer Principles and Design in Verilog HDL % % by Yamin Li, published by A JOHN WILEY & SONS % %****************************************************% DEPTH = 128; % Memory depth and width are required % WIDTH = 32; % Enter a decimal number % ADDRESS_RADIX = HEX; % Address and value radixes are optional % DATA_RADIX = HEX; % Enter BIN, DEC, HEX, or OCT; unless % CONTENT % otherwise specified, radixes = HEX % BEGIN % physical address = 0x2000_2000 % % test data va = 0x0000_2000 % [0..3f]: 0; %(00002000..200020fc) 0 % 40: bf800000; %(00002100) 1 01111111 00..0 fp -1 % 41: 40800000; %(00002104) % 42: 40000000; %(00002108) % 43: 41100000; %(0000210c) % [44..53]: 0; %(00002110..2000214c) 0 % 54: 40c00000; %(00002150) 0 10000001 10..0 data[0] 4.5 % 55: 41c00000; %(00002154) 0 10000011 10..0 data[1] % 56: 43c00000; %(00002158) 0 10000111 10..0 data[2] % 57: 47c00000; %(0000215c) 0 10001111 10..0 data[3] % [58..7f]: 0; %(00002160..200021fc) 0 % END ;
source_codes/mif/data_mem.mif
%****************************************************% % The MIF code example shown here is from the book % % Computer Principles and Design in Verilog HDL % % by Yamin Li, published by A JOHN WILEY & SONS % %****************************************************% DEPTH = 32; % Memory depth and width are required % WIDTH = 32; % Enter a decimal number % ADDRESS_RADIX = HEX; % Address and value radixes are optional % DATA_RADIX = HEX; % Enter BIN, DEC, HEX, or OCT; unless % % otherwise specified, radixes = HEX % CONTENT BEGIN [0..1f] : 00000000; % Range--Every address from 0 to 1f = 00000000 % 0 : bf800000; % (00) 1 01111111 00..0 fp -1 % 1 : 40800000; % (04) % 2 : 40000000; % (08) % 3 : 41100000; % (0c) % 14 : 40c00000; % (50) 0 10000001 10..0 data[0] 4.5 % 15 : 41c00000; % (54) 0 10000011 10..0 data[1] % 16 : 43c00000; % (58) 0 10000111 10..0 data[2] % 17 : 47c00000; % (5c) 0 10001111 10..0 data[3] % END ;
source_codes/mif/inst_mem.mif
%****************************************************% % The MIF code example shown here is from the book % % Computer Principles and Design in Verilog HDL % % by Yamin Li, published by A JOHN WILEY & SONS % %****************************************************% DEPTH = 64; % Memory depth and width are required % WIDTH = 32; % Enter a decimal number % ADDRESS_RADIX = HEX; % Address and value radixes are optional % DATA_RADIX = HEX; % Enter BIN, DEC, HEX, or OCT; unless % % otherwise specified, radixes = HEX % CONTENT BEGIN [0..3f] : 00000000; % Range--Every address from 0 to 3f = 00000000 % 0 : 00000820; % (00) add $1, $0, $0 # address of data[0] % 1 : c4200000; % (04) lwc1 f0, 0($1) # load fp data % 2 : c4210050; % (08) lwc1 f1, 80($1) # load fp data % 3 : c4220054; % (0c) lwc1 f2, 84($1) # load fp data % 4 : c4230058; % (10) lwc1 f3, 88($1) # load fp data % 5 : c424005c; % (14) lwc1 f4, 92($1) # load fp data % 6 : 46002100; % (18) add.s f4, f4, f0 # f4: stall 1 % 7 : 460418c1; % (1c) sub.s f3, f3, f4 # f4: stall 2 % 8 : 46022082; % (20) mul.s f2, f4, f2 # mul % 9 : 46040842; % (24) mul.s f1, f1, f4 # mul % a : e4210070; % (28) swc1 f1, 112($1) # f1: stall 1 % b : e4220074; % (2c) swc1 f2, 116($1) # store fp data % c : e4230078; % (30) swc1 f3, 120($1) # store fp data % d : e424007c; % (34) swc1 f4, 124($1) # store fp data % e : 20020004; % (38) addi $2, $0, 4 # counter % f : c4230000; % (3c) l3: lwc1 f3, 0($1) # load fp data % 10 : c4210050; % (40) lwc1 f1, 80($1) # load fp data % 11 : 46030840; % (44) add.s f1, f1, f3 # stall 1 % 12 : 46030841; % (48) sub.s f1, f1, f3 # stall 2 % 13 : e4210030; % (4c) swc1 f1, 48($1) # stall 1 % 14 : c4050004; % (50) lwc1 f5, 04($0) # load fp data % 15 : c4060008; % (54) lwc1 f6, 08($0) # load fp data % 16 : c408000c; % (58) lwc1 f8, 12($0) # load fp data % 17 : 460629c3; % (5c) div.s f7, f5, f6 # div % 18 : 46004244; % (60) sqrt.s f9, f8 # sqrt % 19 : 46004a84; % (64) sqrt.s f10, f9 # sqrt % 1a : 2042ffff; % (68) addi $2, $2, -1 # counter - 1 % 1b : 1440fff3; % (6c) bne $2, $0, l3 # finish? % 1c : 20210004; % (70) addi $1, $1, 4 # address+4, delay slot % 1d : 3c010000; % (74) iu_test:lui $1, 0 # address of data[0] % 1e : 34240050; % (78) ori $4, $1, 80 # address of data[0] % 1f : 0c000038; % (7c) call: jal sum # call function % 20 : 20050004; % (80) dslot1: addi $5, $0, 4 # delyed slot(ds) % 21 : ac820000; % (84) return: sw $2, 0($4) # store result % 22 : 8c890000; % (88) lw $9, 0($4) # check sw % 23 : 01244022; % (8c) sub $8, $9, $4 # sub: $8 <-- $9 - $4 % 24 : 20050003; % (90) addi $5, $0, 3 # counter % 25 : 20a5ffff; % (94) loop2: addi $5, $5, -1 # counter - 1 % 26 : 34a8ffff; % (98) ori $8, $5, 0xffff # zero-extend: 0000ffff % 27 : 39085555; % (9c) xori $8, $8, 0x5555 # zero-extend: 0000aaaa % 28 : 2009ffff; % (a0) addi $9, $0, -1 # sign-extend: ffffffff % 29 : 312affff; % (a4) andi $10, $9, 0xffff# zero-extend: 0000ffff % 2a : 01493025; % (a8) or $6, $10, $9 # or: ffffffff % 2b : 01494026; % (ac) xor $8, $10, $9 # xor: ffff0000 % 2c : 01463824; % (b0) and $7, $10, $6 # and: 0000ffff % 2d : 10a00003; % (b4) beq $5, $0, shift # if $5 = 0, goto shift % 2e : 00000000; % (b8) dslot2: nop # ds % 2f : 08000025; % (bc) j loop2 # jump loop2 % 30 : 00000000; % (c0) dslot3: nop # ds % 31 : 2005ffff; % (c4) shift: addi $5, $0, -1 # $5 = ffffffff % 32 : 000543c0; % (c8) sll $8, $5, 15 # << 15 = ffff8000 % 33 : 00084400; % (cc) sll $8, $8, 16 # << 16 = 80000000 % 34 : 00084403; % (d0) sra $8, $8, 16 # >>> 16 = ffff8000 % 35 : 000843c2; % (d4) srl $8, $8, 15 # >> 15 = 0001ffff % 36 : 08000036; % (d8) finish: j finish # dead loop % 37 : 00000000; % (dc) dslot4: nop # ds % 38 : 00004020; % (e0) sum: add $8, $0, $0 # sum % 39 : 8c890000; % (e4) loop: lw $9, 0($4) # load data % 3a : 01094020; % (e8) add $8, $8, $9 # sum % 3b : 20a5ffff; % (ec) addi $5, $5, -1 # counter - 1 % 3c : 14a0fffc; % (f0) bne $5, $0, loop # finish? % 3d : 20840004; % (f4) dslot5: addi $4, $4, 4 # address + 4, ds % 3e : 03e00008; % (f8) jr $31 # return % 3f : 00081000; % (fc) dslot6: sll $2, $8, 0 # move res. to v0, ds % END ;
source_codes/mif/mcmem.mif
%****************************************************% % The MIF code example shown here is from the book % % Computer Principles and Design in Verilog HDL % % by Yamin Li, published by A JOHN WILEY & SONS % %****************************************************% DEPTH = 64; % Memory depth and width are required % WIDTH = 32; % Enter a decimal number % ADDRESS_RADIX = HEX; % Address and value radixes are optional % DATA_RADIX = HEX; % Enter BIN, DEC, HEX, or OCT; unless % % otherwise specified, radixes = HEX % CONTENT BEGIN [0..3f] : 00000000; % Range--Every address from 0 to 3f = 00000000 % 0 : 3c010000; % (00) main: lui $1, 0 # address of data[0] % 1 : 34240080; % (04) ori $4, $1, 0x80 # address of data[0] % 2 : 20050004; % (08) addi $5, $0, 4 # counter % 3 : 0c000018; % (0c) call: jal sum # call function % 4 : ac820000; % (10) sw $2, 0($4) # store result % 5 : 8c890000; % (14) lw $9, 0($4) # check sw % 6 : 01244022; % (18) sub $8, $9, $4 # sub: $8 <-- $9 - $4 % 7 : 20050003; % (1c) addi $5, $0, 3 # counter % 8 : 20a5ffff; % (20) loop2: addi $5, $5, -1 # counter - 1 % 9 : 34a8ffff; % (24) ori $8, $5, 0xffff # zero-extend: 0000ffff % a : 39085555; % (28) xori $8, $8, 0x5555 # zero-extend: 0000aaaa % b : 2009ffff; % (2c) addi $9, $0, -1 # sign-extend: ffffffff % c : 312affff; % (30) andi $10, $9,0xffff # zero-extend: 0000ffff % d : 01493025; % (34) or $6, $10, $9 # or: ffffffff % e : 01494026; % (38) xor $8, $10, $9 # xor: ffff0000 % f : 01463824; % (3c) and $7, $10, $6 # and: 0000ffff % 10 : 10a00001; % (40) beq $5, $0, shift # if $5 = 0, goto shift % 11 : 08000008; % (44) j loop2 # jump loop2 % 12 : 2005ffff; % (48) shift: addi $5, $0, -1 # $5 = ffffffff % 13 : 000543c0; % (4c) sll $8, $5, 15 # <<15 = ffff8000 % 14 : 00084400; % (50) sll $8, $8, 16 # <<16 = 80000000 % 15 : 00084403; % (54) sra $8, $8, 16 # >>16 = ffff8000(arith) % 16 : 000843c2; % (58) srl $8, $8, 15 # >>15 = 0001ffff(logic) % 17 : 08000017; % (5c) finish: j finish # dead loop % 18 : 00004020; % (60) sum: add $8, $0, $0 # sum % 19 : 8c890000; % (64) loop: lw $9, 0($4) # load data % 1a : 20840004; % (68) addi $4, $4, 4 # address + 4 % 1b : 01094020; % (6c) add $8, $8, $9 # sum % 1c : 20a5ffff; % (70) addi $5, $5, -1 # counter - 1 % 1d : 14a0fffb; % (74) bne $5, $0, loop # finish? % 1e : 00081000; % (78) sll $2, $8, 0 # move result to v0 % 1f : 03e00008; % (7c) jr $31 # return % 20 : 000000a3; % (80) data[0] 0 + a3 = a3 % 21 : 00000027; % (84) data[1] a3 + 27 = ca % 22 : 00000079; % (88) data[2] ca + 79 = 143 % 23 : 00000115; % (8c) data[3] 143 + 115 = 258 % 24 : 00000000; % (90) sum, should be = 0x00000258, stored by sw % END ;
source_codes/mif/scd_intr.mif
%****************************************************% % The MIF code example shown here is from the book % % Computer Principles and Design in Verilog HDL % % by Yamin Li, published by A JOHN WILEY & SONS % %****************************************************% DEPTH = 32; % Memory depth and width are required % WIDTH = 32; % Enter a decimal number % ADDRESS_RADIX = HEX; % Address and value radixes are optional % DATA_RADIX = HEX; % Enter BIN, DEC, HEX, or OCT; unless % % otherwise specified, radixes = HEX % CONTENT BEGIN [0..1f] : 00000000; % Range--Every address from 0 to 1f = 00000000 % % address table for internal exceptions and external interrupt % 8 : 00000030; % (20) int_entry # 0. address for interrupt % 9 : 0000003c; % (24) sys_entry # 1. address for system call % a : 00000054; % (28) uni_entry # 2. address for unimpl. instruction % b : 00000068; % (2c) ovf_entry # 3. address for signed overflow % 12 : 00000002; % (48) for testing overflow % 13 : 7fffffff; % (4c) 2 + max_int -> overflow % 14 : 000000a3; % (50) data[0] 0 + a3 = a3 % 15 : 00000027; % (54) data[1] a3 + 27 = ca % 16 : 00000079; % (58) data[2] ca + 79 = 143 % 17 : 00000115; % (5c) data[3] 143 + 115 = 258 % END ;
source_codes/mif/sci_intr.mif
%****************************************************% % The MIF code example shown here is from the book % % Computer Principles and Design in Verilog HDL % % by Yamin Li, published by A JOHN WILEY & SONS % %****************************************************% DEPTH = 64; % Memory depth and width are required % WIDTH = 32; % Enter a decimal number % ADDRESS_RADIX = HEX; % Address and value radixes are optional % DATA_RADIX = HEX; % Enter BIN, DEC, HEX, or OCT; unless % % otherwise specified, radixes = HEX % CONTENT BEGIN [0..3f] : 00000000; % Range--Every address from 0 to 3f = 00000000 % % reset: % 0: 0800001d; % (00) j start # entry on reset % 1: 00000000; % (04) nop # % % exc_base: # exception handler % 2: 401a6800; % (08) mfc0 $26, c0_cause # read cp0 cause reg % 3: 335b000c; % (0c) andi $27, $26, 0xc # get exccode, 2 bits here % 4: 8f7b0020; % (10) lw $27, j_table($27) # get address from table % 5: 00000000; % (14) nop # % 6: 03600008; % (18) jr $27 # jump to that address % 7: 00000000; % (1c) nop # % % int_entry: # 0. interrupt handler % c: 00000000; % (30) nop # deal with interrupt here % d: 42000018; % (34) eret # retrun from interrupt % e: 00000000; % (38) nop # % % sys_entry: # 1. syscall handler % f: 00000000; % (3c) nop # do something here % % epc_plus4: # % 10: 401a7000; % (40) mfc0 $26, c0_epc # get epc % 11: 235a0004; % (44) addi $26, $26, 4 # epc + 4 % 12: 409a7000; % (48) mtc0 $26, c0_epc # epc <- epc + 4 % 13: 42000018; % (4c) eret # retrun from exception % 14: 00000000; % (50) nop # % % uni_entry: # 2. unimpl. inst. handler % 15: 00000000; % (54) nop # do something here % 16: 08000010; % (58) j epc_plus4 # return % 17: 00000000; % (5c) nop # % % ovf_entry: # 3. overflow handler % 1a: 00000000; % (68) nop # do something here % 1b: 08000010; % (6c) j epc_plus4 # return % 1c: 00000000; % (70) nop # % % start: # % 1d: 2008000f; % (74) addi $8, $0, 0xf # im[3:0] <- 1111 % 1e: 40886000; % (78) mtc0 $8, c0_status # exc/intr enable % 1f: 8c080048; % (7c) lw $8, 0x48($0) # try overflow exception % 20: 8c09004c; % (80) lw $9, 0x4c($0) # caused by add % % ov: # % 21: 01094020; % (84) add $9, $9, $8 # overflow % 22: 00000000; % (88) nop # % % sys: # % 23: 0000000c; % (8c) syscall # system call % 24: 00000000; % (90) nop # % % unimpl: # % 25: 0128001a; % (94) div $9, $8 # div, but not implemented % 26: 00000000; % (98) nop # % % int: # % 27: 34040050; % (9c) ori $4, $1, 0x50 # address of data[0] % 28: 20050004; % (a0) addi $5, $0, 4 # counter % 29: 00004020; % (a4) add $8, $0, $0 # sum <- 0 % % loop: # % 2a: 8c890000; % (a8) lw $9, 0($4) # load data % 2b: 20840004; % (ac) addi $4, $4, 4 # address + 4 % 2c: 01094020; % (b0) add $8, $8, $9 # sum % 2d: 20a5ffff; % (b4) addi $5, $5, -1 # counter - 1 % 2e: 14a0fffb; % (b8) bne $5, $0, loop # finish? % 2f: 00000000; % (bc) nop # % % finish: # % 30: 08000030; % (c0) j finish # dead loop % END ;
source_codes/s/asmsim_examples.s/asmsim.jar
META-INF/MANIFEST.MF
Manifest-Version: 1.0 Created-By: 1.8.0_25 (Oracle Corporation) Main-Class: asm
alteramif.class
public synchronized class alteramif extends java.awt.Frame { private static final long serialVersionUID = 8531245739641223373; public static java.awt.TextArea txt; public void alteramif(String); public static void generate(); }
alteramif32.class
public synchronized class alteramif32 extends java.awt.Frame { public static java.awt.TextArea txt; public void alteramif32(String); public static void generate(); }
alteramifhex.class
public synchronized class alteramifhex extends java.awt.Frame { public static java.awt.TextArea txt; public void alteramifhex(String); public static void generate(); public static String dasm(int); }
applet_doubleBuffering.class
public synchronized class applet_doubleBuffering extends java.applet.Applet implements java.awt.event.MouseMotionListener { java.awt.Graphics bufferGraphics; java.awt.Image offscreen; java.awt.Dimension dim; int curX; int curY; public void applet_doubleBuffering(); public void init(); public void paint(java.awt.Graphics); public void update(java.awt.Graphics); public void mouseMoved(java.awt.event.MouseEvent); public void mouseDragged(java.awt.event.MouseEvent); }
asm$1.class
final synchronized class asm$1 extends java.awt.event.WindowAdapter { void asm$1(); public void windowClosing(java.awt.event.WindowEvent); }
asm$2.class
synchronized class asm$2 extends java.awt.event.MouseAdapter { void asm$2(asm); public void mouseClicked(java.awt.event.MouseEvent); }
asm$3.class
synchronized class asm$3 extends java.awt.event.MouseAdapter { void asm$3(asm); public void mouseClicked(java.awt.event.MouseEvent); }
asm.class
public synchronized class asm extends javax.swing.JPanel implements javax.swing.event.ListSelectionListener, java.awt.event.ActionListener, Runnable { public static javax.swing.JList list; public static javax.swing.JList reglist; public static javax.swing.JList memlist; public static javax.swing.JButton edit; public static javax.swing.JButton step; public static javax.swing.JButton go; public static javax.swing.JButton restart; public static javax.swing.JButton run; public static javax.swing.JButton stop; public static javax.swing.JButton quit; public static javax.swing.JButton inst; public static javax.swing.JButton ascii; public static javax.swing.JButton xilinx; public static javax.swing.JButton altera; public static javax.swing.DefaultListModel model; public static javax.swing.DefaultListModel regmodel; public static javax.swing.DefaultListModel memmodel; public static editBuffer programEditBuffer; public static instFormat instFormat; public static xilinxcoe xilinxcoe; public static alteramif alteramif; public static alteramifhex alteramifhex; public static console console; public static int timer; public static boolean startSleep; Thread thread; public void asm(); public static void main(String[]); public void init(); public void run(); public void asciiShow(); public void actionPerformed(java.awt.event.ActionEvent); public void keyPressed(java.awt.event.KeyEvent); public void keyReleased(java.awt.event.KeyEvent); public void keyTyped(java.awt.event.KeyEvent); public void valueChanged(javax.swing.event.ListSelectionEvent); static void <clinit>(); }
assemble.class
public synchronized class assemble extends asm { public static int posLineEnd; public static java.util.Hashtable symbolTable; public static java.util.Hashtable addressTable; public static int defaultStartAddress; public static int pos; public static int errLineNumber; public static boolean labelNoInst; public static String programLine; public static String newStr; public static String str; public static String instName; public static String regName; public static int rd; public static int rs; public static int rt; public static int sa; public static int imm; public static int addr; public static int instCode32; public static String instCodeHex; public static String pcHex; public static int[] instLineNo; public static int dataAddr; public static int dataAddrMax; public static int pcMax; public static boolean coding; public static boolean dating; public static boolean had_inst; public static boolean had_data; public static boolean missingEndCodeWarningDone; public static boolean missingEndDataWarningDone; public static int codeListIndexLowBound; public static int codeListIndexUpBound; public static int listElementIndex; public static boolean thisInstOk; public static boolean success; public static int errCounter; public static int codeStartAddr; public static int dataStartAddr; public static int pass; public static int interruptEntry; public static boolean hadCode; public static boolean hadData; public static boolean single_memory_module; public static int[] errIndices; public static int freeMemoryPointer; public static int _Video_RAM; public static boolean had_dot_text; public static boolean had_dot_data; public static int return_val; public void assemble(); public static void createHashtable(); public static void loadFile(); public static void preprocessing(); public static void assembleFile(); public static void doAssemble(); public static void add_dot_text(); public static void dot_text(); public static void add_dot_data(); public static void dot_data(); public static void assembleInstruction(); public static void getWord(); public static void getCommLabel(); public static void getCommSize(); public static void addType(int); public static void sllvType(int); public static void sllType(int); public static void jrType(int); public static void syscallType(int); public static void addiType(int); public static void lwType(int); public static void beqType(int); public static void bzType(int); public static void luiType(int); public static void jType(int); public static void jalType(int); public static void liType(int); public static void moveType(int); public static void nopType(int); public static void lahiType(int); public static void laloType(int); public static void lihiType(int); public static void liloType(int); public static void mulType(int); public static void multType(int); public static void mvfType(int); public static void mvtType(int); public static void eretType(int); public static int getRegWithComma(char); public static void addInstToList(); public static int getRegWithoutComma(); public static int getImm(String); public static void displayError(String); static void <clinit>(); }
canvas.class
synchronized class canvas extends java.awt.Canvas { java.awt.Image displayBuffer; java.awt.Graphics drawingBuffer; void canvas(); public void paint(java.awt.Graphics); public void update(java.awt.Graphics); }
caret.class
synchronized class caret implements Runnable { public static boolean clockIsOne; void caret(); public void run(); static void <clinit>(); }
closeWindow.class
public synchronized class closeWindow extends java.awt.event.WindowAdapter { public void closeWindow(); public void windowClosing(java.awt.event.WindowEvent); }
console$1.class
synchronized class console$1 extends java.awt.event.MouseAdapter { void console$1(console); public void mouseMoved(java.awt.event.MouseEvent); }
console$2.class
synchronized class console$2 extends java.awt.event.MouseAdapter { void console$2(console); public void mouseExited(java.awt.event.MouseEvent); }
console.class
public synchronized class console extends javax.swing.JFrame implements java.awt.event.KeyListener { public static javax.swing.JTextArea output; public static mycanvas canvas; public static String str; public static String preDebugStr; public static String preCommdStr; public static String s; public static String strLine; public static String displayText; public static char c; public static int extKeyCode; public static int c2i; public static javax.swing.text.Highlighter h; public static boolean c2iIsReady; public static boolean extKeyCodeIsReady; public static boolean pleaseGoToInterruptServiceRoutine; public static int keyCode; public static int theCommand; public static boolean controlKeyPressed; private static final int _HELLO = 1; private static final int _PRINTF = 2; private static final int _SCANF = 3; private static final int _GETCHAR = 4; private static final int _PUTCHAR = 5; private static final int _SPRINTF = 6; private static final int _GETRANDOM = 7; private static final int _GETTIMER = 8; private static final int _GETARROW = 9; private static final int _GETCAL = 10; private static final int _GETCALS = 11; private static final int _SLEEP = 12; private static final int _FIBONACCI = 13; private static final int _GRAPHICS = 14; private static final int _KEY_EVENT = 15; private static final int _LINKEDLIST = 16; private static final int _RECURSIVE = 17; private static final int _MALLOC = 18; private static final int _DFS = 19; private static final int _BFS = 20; private static final int _VRAM = 21; private static final int _FONTS = 22; private static final int _KANJI = 23; private static final int _PICTURE = 24; private static final int _SUBROUTINE = 25; private static final int _POINTER = 26; private static final int _SQUART = 27; private static final int _TEMPLATE = 99; public static final javax.swing.text.Highlighter$HighlightPainter highlightPainter; public void console(); public void initialize(); public void keyPressed(java.awt.event.KeyEvent); public void help(String); public void keyReleased(java.awt.event.KeyEvent); public void keyTyped(java.awt.event.KeyEvent); public void displayAscii(String); public void processStrLine(String); public void append(String); public void quit(String); static void <clinit>(); }
cpu.class
synchronized class cpu { public static int pc; public static int npc; public static int epc; public static int hi; public static int lo; public static int[] reg; public static int[] instmem; public static int[] datamem; public static int[] textram; public static int instmemSize; public static int datamemSize; void cpu(); static void <clinit>(); }
display.class
public synchronized class display extends java.awt.Frame { public static java.awt.TextArea txt; public void display(String); }
editBuffer$1.class
synchronized class editBuffer$1 implements javax.swing.event.DocumentListener { void editBuffer$1(editBuffer); public void insertUpdate(javax.swing.event.DocumentEvent); public void removeUpdate(javax.swing.event.DocumentEvent); public void changedUpdate(javax.swing.event.DocumentEvent); }
editBuffer$2.class
synchronized class editBuffer$2 implements Runnable { void editBuffer$2(editBuffer); public void run(); }
editBuffer$3.class
synchronized class editBuffer$3 implements Runnable { void editBuffer$3(editBuffer); public void run(); }
editBuffer.class
public synchronized class editBuffer extends javax.swing.JFrame implements java.awt.event.ActionListener, java.awt.event.KeyListener, java.awt.event.MouseListener { public static javax.swing.JTextPane textpane; public static javax.swing.JTextPane numpane; public static javax.swing.JTextField searchfield; public static String searchPattern; javax.swing.JButton b_asm; javax.swing.JPanel b_panel; javax.swing.JScrollPane scrollpane; javax.swing.text.StyledDocument doc; javax.swing.text.StyledDocument numdoc; javax.swing.text.SimpleAttributeSet planeCode; javax.swing.text.SimpleAttributeSet planeData; javax.swing.text.SimpleAttributeSet attrComm; javax.swing.text.SimpleAttributeSet attrInst; javax.swing.text.SimpleAttributeSet attrDire; javax.swing.text.SimpleAttributeSet numStyle; javax.swing.text.SimpleAttributeSet attrSearch; javax.swing.text.SimpleAttributeSet attrFocus; public static int caretPosition; public static int caretReturn; String text; String textrest; public static int numLines; public static int currentLineNumber; public static boolean insert; public static boolean controlKeyPressing; public static boolean searchMode; int searchStartPosition; char p3char; char p2char; char p1char; char sc; boolean went; public static boolean searchCharRemoved; public static boolean continueSearch; public static boolean isFirstCtrlS; public static boolean previousIsFirstCtrlS; public static int preSearchFountPos; public static int preSearchLength; public static boolean reachLast; public static final String[] keywords; public static final String[] directives; public void editBuffer(String); public void actionPerformed(java.awt.event.ActionEvent); void setHighlight(); void invokeSetHighlight(); public void setLineNumberRange(); public void setLineNumber(); public String getNumText(); public void keyPressed(java.awt.event.KeyEvent); public void keyReleased(java.awt.event.KeyEvent); public void keyTyped(java.awt.event.KeyEvent); public void mousePressed(java.awt.event.MouseEvent); public void mouseReleased(java.awt.event.MouseEvent); public void mouseEntered(java.awt.event.MouseEvent); public void mouseExited(java.awt.event.MouseEvent); public void mouseClicked(java.awt.event.MouseEvent); static void <clinit>(); }
hello.class
synchronized class hello { public static String programBuffer; public static String tempBuffer; public static String sampleCode; void hello(); static void <clinit>(); }
help.class
public synchronized class help extends java.awt.Frame { java.awt.TextArea textarea; public void help(String); }
instFormat.class
public synchronized class instFormat extends java.awt.Frame { java.awt.TextArea textarea; public void instFormat(String); }
integer.class
synchronized class integer { void integer(); public static String toHexString(int, int, boolean); }
mycanvas.class
public synchronized class mycanvas extends java.awt.Canvas { public static java.awt.Graphics g; public static java.awt.Graphics bufferGraphics; public static java.awt.image.BufferedImage bufImage; public void mycanvas(); public void paint(java.awt.Graphics); public void update(java.awt.Graphics); public void redraw(); public static void createBufferedImage(); public static void init(); public static void setColor(int); public static void drawLine(int, int, int, int, int); public static void drawString(int, int, int, int, String); public static void drawRect(int, int, int, int, int); public static void draw3DRect(int, int, int, int, int); public static void fillRect(int, int, int, int, int); public static void fill3DRect(int, int, int, int, int); public static void drawOval(int, int, int, int, int); public static void fillOval(int, int, int, int, int); public static void clear(int); public java.awt.Dimension getPreferredSize(); static void <clinit>(); }
myInteger.class
public synchronized class myInteger { public void myInteger(); public static int parseInt(String, int); }
mySleep.class
public synchronized class mySleep extends asm { public static int sleepTime; public void mySleep(); public static void trySleep(int); public static int getSleepTime(); public static void woken(); static void <clinit>(); }
opcode.class
synchronized class opcode { public static final String[] name; public static final String[] regname; public static final int[] func; public static final int[] op; void opcode(); static void <clinit>(); }
regFrame.class
public synchronized class regFrame extends java.awt.Frame { java.awt.TextArea textarea; public void regFrame(String); }
simulator.class
public synchronized class simulator extends assemble { public static final int NORMAL = 0; public static final int BREAKSET = 1; public static final int GOTO = 2; public static final int STOPPED = 4; public static final int WAITINPUT = 8; public static final int GOTOABORT = 16; public static final int QUITED = 32; public static final int SLEEPING = 64; public static final int INTERRUPTING = 128; public static final int SYSCALL = 256; private static final String[] days; private static final String[] months; public static int state; public static int breakPoint; public static boolean checkState; public static boolean gotInt; public static String mem8wordStr; public static int memWordIndex; public static int memListIndex; public static String memLineAddress; public static boolean interruptEnabled; public static int sysCallType; public static boolean printfing; public static int ppc; public static String sprintfStr; public static boolean refresh_vga_auto; public static boolean vram_640_480; public void simulator(); public static void step(); public static void executeOneInstruction(); public static void jumpAndLink(); public static void _scanf(); public static String getString(int); public static void sappend(String); public static int _sprintf(boolean); public static void go(); public static void focusList(); public static void clear(); public static void restart(); public static void listSelectedIndex(); public static void displayAndStop(String); public static void enableButtons(); public static void datamemWrite(int, int); public static int datamemRead(int, int); public static void updateEPCList(); public static void updateRegList(int); public static void updateLoHiList(int); public static void updateDatamemList(int); public static void updateAllList(); public static void append(String); public static void showAscii(String); static void <clinit>(); }
sourceCode.class
synchronized class sourceCode { public static String programBuffer; public static String tempBuffer; public static String sampleCode; public static String temp; public static String picture_0; public static String picture_1; public static String picture_2; public static String picture_3; public static String picture_4; public static String picture; public static String kanji_00; public static String kanji_a1; public static String kanji_a2; public static String kanji_a3; public static String kanji_a4; public static String kanji_a5; public static String kanji_b0; public static String kanji_b1; public static String kanji; public static String fonts; public static String vram; public static String bfs; public static String dfs; public static String malloc; public static String recursive; public static String sprintf; public static String linked_list; public static String sleep; public static String gettimer; public static String getcals; public static String getcal; public static String getarrow; public static String getrandom; public static String printf; public static String getchar; public static String hello; public static String scanf; public static String graphics; public static String key_event; public static String subroutine_call; public static String pointer; public static String root_nonrestoring; void sourceCode(); static void <clinit>(); }
xilinxcoe.class
public synchronized class xilinxcoe extends java.awt.Frame { public static java.awt.TextArea txt; public void xilinxcoe(String); public static void generate(); }
xilinxcoehex.class
public synchronized class xilinxcoehex extends java.awt.Frame { public static java.awt.TextArea txt; public void xilinxcoehex(String); public static void generate(); public static String dasm(int); }
source_codes/s/asmsim_examples.s/bfs.s
/* * bfs.s * Breadth First Search (BFS): * The graph is given in an adjacent (linked) list. * The starting node is v1. From v1, we print out all the * nodes in the visited order based on the BFS algorithm * shown in the VGA. You may try to show the queue status and * draw the graph dynamically in the VGA. And you may also try * to use scanf() and malloc() to build a dynamic adjacent list. */ `define NULL 0x0 .text # code segment main: # program entry subi $sp, $sp, 64 # reserve stack space sw $ra, 60($sp) # save return address sw $fp, 56($sp) # save frame pointer move $fp, $sp # new frame pointer user_main: la $4, g_bgcolor # draw bfs algorithm jal fillrect # draw bfs algorithm la $4, t # draw bfs algorithm jal drawstring # draw bfs algorithm la $4, l0 # draw bfs algorithm jal drawstring # draw bfs algorithm la $4, l1 # draw bfs algorithm jal drawstring # draw bfs algorithm la $4, l2 # draw bfs algorithm jal drawstring # draw bfs algorithm la $4, l3 # draw bfs algorithm jal drawstring # draw bfs algorithm la $4, l4 # draw bfs algorithm jal drawstring # draw bfs algorithm la $4, l5 # draw bfs algorithm jal drawstring # draw bfs algorithm la $4, l6 # draw bfs algorithm jal drawstring # draw bfs algorithm la $4, l7 # draw bfs algorithm jal drawstring # draw bfs algorithm la $4, l8 # draw bfs algorithm jal drawstring # draw bfs algorithm la $4, l9 # draw bfs algorithm jal drawstring # draw bfs algorithm jal paint # draw bfs algorithm ori $26, $0, 0 # queue read pointer ori $27, $0, 0 # queue write pointer move $28, $gp # queue base pointer subi $28, $28, 256 # queue size = 256 bytes la $4, v1 # $4 = v1 enqueue_the_first_node(s): addi $27, $27, 4 # queue write pointer andi $27, $27, 0xff # circulated queue add $25, $27, $28 # queue write pointer sw $4, 0($25) # enqueue the node q_empty?: # check the queue status beq $26, $27, return_to_caller(os) # queue is empty dequeue: # queue is not empty addi $26, $26, 4 # queue read pointer andi $26, $26, 0xff # circulated queue add $25, $26, $28 # queue read pointer lw $2, 0($25) # dequeue the node sw $2, 48($fp) # store the dequeued node lw $5, 8($2) # was it visited ? bne $5, $0, q_empty? # yes, go checking queue the_dequeued_node_was_not_yet_visited: ori $5, $0, 1 # mark the node visited sw $5, 8($2) # store the mark lw $4, 48($fp) # load the dequeued node lw $5, 0($4) # for getting node value la $4, dec # %d for printing out jal printf # print the node value lw $4, 48($fp) # load the dequeued node check_its_all_adjacents_in_list: lw $4, 4($4) # load the pointer beq $4, $0, q_empty? # pointer == NULL? get_a_neighbor: # no lw $5, 0($4) # get the value (a node) lw $6, 8($5) # was the node visited ? bne $6, $0, visited # yes, check next enqueue_the_neighbor: # no addi $27, $27, 4 # queue write pointer andi $27, $27, 0xff # circulated queue add $25, $27, $28 # queue write pointer sw $5, 0($25) # enqueue the node visited: j check_its_all_adjacents_in_list return_to_caller(os): # exit() move $sp, $fp # restore stack pointer lw $fp, 56($sp) # restore frame pointer lw $ra, 60($sp) # restore return address addi $sp, $sp, 64 # release stack space jr $ra # return to operating system .data # data segment v1: .word 1, p1 # value, pointer .word 0 # visited or not p1: .word v1, p2 # value, pointer p2: .word v4, p3 # value, pointer p3: .word v2, NULL # value, pointer v2: .word 2, p4 # value, pointer .word 0 # visited or not p4: .word v3, p5 # value, pointer p5: .word v5, NULL # value, pointer v3: .word 3, p6 # value, pointer .word 0 # visited or not p6: .word v1, p7 # value, pointer p7: .word v2, p8 # value, pointer p8: .word v5, NULL # value, pointer v4: .word 4, p9 # value, pointer .word 0 # visited or not p9: .word v3, p10 # value, pointer p10: .word v5, NULL # value, pointer v5: .word 5, p11 # value, pointer .word 0 # visited or not p11: .word v4, NULL # value, pointer dec: .ascii "v%d\n" g_bgcolor: .word 0x000000 # color .word 0 # x .word 0 # y .word 640 # w .word 480 # h t: .word 0x00d000 # color .word 25 # x .word 40 # y .word 0x020118 # font name_type_size .ascii "Breadth First Search (BFS):" l0: .word 0xffd000 # color .word 25 # x .word 100 # y .word 0x020118 # font name_type_size .ascii "forall (x in V) visited[x] = false;" l1: .word 0xffd000 # color .word 25 # x .word 140 # y .word 0x020118 # font name_type_size .ascii "enqueue(s);" l2: .word 0xffd000 # color .word 25 # x .word 180 # y .word 0x020118 # font name_type_size .ascii "while (!queue_empty()) {" l3: .word 0xffd000 # color .word 25 # x .word 220 # y .word 0x020118 # font name_type_size .ascii " x = dequeue();" l4: .word 0xffd000 # color .word 25 # x .word 260 # y .word 0x020118 # font name_type_size .ascii " if (!visited[x]) {" l5: .word 0xffd000 # color .word 25 # x .word 300 # y .word 0x020118 # font name_type_size .ascii " visited[x] = true;" l6: .word 0xffd000 # color .word 25 # x .word 340 # y .word 0x020118 # font name_type_size .ascii " forall (w in adj[x])" l7: .word 0xffd000 # color .word 25 # x .word 380 # y .word 0x020118 # font name_type_size .ascii " if (!visited[w]) enqueue(w);" l8: .word 0xffd000 # color .word 25 # x .word 420 # y .word 0x020118 # font name_type_size .ascii " }" l9: .word 0xffd000 # color .word 25 # x .word 460 # y .word 0x020118 # font name_type_size .ascii "}" .end
source_codes/s/asmsim_examples.s/dfs.s
/* * dfs.s * Depth First Search (DFS): * The graph is given in an adjacent (linked) list. * The starting node is v1. From v1, we print out all the * nodes in the visited order based on the DFS algorithm * shown in the VGA. You may try to show the queue status and * draw the graph dynamically in the VGA. And you may also try * to use scanf() and malloc() to build a dynamic adjacent list. */ `define NULL 0x0 .text # code segment main: # program entry subi $sp, $sp, 64 # reserve stack space sw $ra, 60($sp) # save return address sw $fp, 56($sp) # save frame pointer move $fp, $sp # new frame pointer user_main: sw $sp, 52($fp) # for checking stack empty la $4, g_bgcolor # draw dfs algorithm jal fillrect # draw dfs algorithm la $4, t # draw dfs algorithm jal drawstring # draw dfs algorithm la $4, l0 # draw dfs algorithm jal drawstring # draw dfs algorithm la $4, l1 # draw dfs algorithm jal drawstring # draw dfs algorithm la $4, l2 # draw dfs algorithm jal drawstring # draw dfs algorithm la $4, l3 # draw dfs algorithm jal drawstring # draw dfs algorithm la $4, l4 # draw dfs algorithm jal drawstring # draw dfs algorithm la $4, l5 # draw dfs algorithm jal drawstring # draw dfs algorithm la $4, l6 # draw dfs algorithm jal drawstring # draw dfs algorithm la $4, l7 # draw dfs algorithm jal drawstring # draw dfs algorithm la $4, l8 # draw dfs algorithm jal drawstring # draw dfs algorithm la $4, l9 # draw dfs algorithm jal drawstring # draw dfs algorithm jal paint # draw dfs algorithm la $4, v1 # $4 = v1 push_the_first_node(s): sw $4, 0($sp) # push the node onto stack subi $sp, $sp, 4 # update $sp s_empty?: # check the stack status lw $4, 52($fp) # $4: original $sp beq $sp, $4, return_to_caller(os) # stack is empty pop: # stack is not empty addi $sp, $sp, 4 # update $sp lw $2, 0($sp) # pop a node from stack sw $2, 48($fp) # store the popped node lw $5, 8($2) # was it visited ? bne $5, $0, s_empty? # yes, go checking stack the_popped_node_was_not_yet_visited: ori $5, $0, 1 # mark the node visited sw $5, 8($2) # store the mark lw $4, 48($fp) # load the popped node lw $5, 0($4) # for getting node value la $4, dec # %d for printing out jal printf # print the node value lw $4, 48($fp) # load the popped node check_its_all_adjacents_in_list: lw $4, 4($4) # load the pointer beq $4, $0, s_empty? # pointer == NULL? get_a_neighbor: # no lw $5, 0($4) # get the value (a node) lw $6, 8($5) # was the node visited ? bne $6, $0, visited # yes, check next push_the_neighbor: # no sw $5, 0($sp) # push the node onto stack subi $sp, $sp, 4 # update $sp visited: j check_its_all_adjacents_in_list return_to_caller(os): # exit() move $sp, $fp # restore stack pointer lw $fp, 56($sp) # restore frame pointer lw $ra, 60($sp) # restore return address addi $sp, $sp, 64 # release stack space jr $ra # return to operating system .data # data segment v1: .word 1, p1 # value, pointer .word 0 # visited or not p1: .word v1, p2 # value, pointer p2: .word v2, p3 # value, pointer p3: .word v4, NULL # value, pointer v2: .word 2, p4 # value, pointer .word 0 # visited or not p4: .word v5, p5 # value, pointer p5: .word v3, NULL # value, pointer v3: .word 3, p6 # value, pointer .word 0 # visited or not p6: .word v1, p7 # value, pointer p7: .word v2, p8 # value, pointer p8: .word v5, NULL # value, pointer v4: .word 4, p9 # value, pointer .word 0 # visited or not p9: .word v5, p10 # value, pointer p10: .word v3, NULL # value, pointer v5: .word 5, p11 # value, pointer .word 0 # visited or not p11: .word v4, NULL # value, pointer dec: .ascii "v%d\n" g_bgcolor: .word 0x000000 # color .word 0 # x .word 0 # y .word 640 # w .word 480 # h t: .word 0x00d000 # color .word 25 # x .word 40 # y .word 0x020118 # font name_type_size .ascii "Depth First Search (DFS):" l0: .word 0xffd000 # color .word 25 # x .word 100 # y .word 0x020118 # font name_type_size .ascii "forall (x in V) visited[x] = false;" l1: .word 0xffd000 # color .word 25 # x .word 140 # y .word 0x020118 # font name_type_size .ascii "push(s);" l2: .word 0xffd000 # color .word 25 # x .word 180 # y .word 0x020118 # font name_type_size .ascii "while (!stack_empty()) {" l3: .word 0xffd000 # color .word 25 # x .word 220 # y .word 0x020118 # font name_type_size .ascii " x = pop();" l4: .word 0xffd000 # color .word 25 # x .word 260 # y .word 0x020118 # font name_type_size .ascii " if (!visited[x]) {" l5: .word 0xffd000 # color .word 25 # x .word 300 # y .word 0x020118 # font name_type_size .ascii " visited[x] = true;" l6: .word 0xffd000 # color .word 25 # x .word 340 # y .word 0x020118 # font name_type_size .ascii " forall (w in adj[x])" l7: .word 0xffd000 # color .word 25 # x .word 380 # y .word 0x020118 # font name_type_size .ascii " if (!visited[w]) push(w);" l8: .word 0xffd000 # color .word 25 # x .word 420 # y .word 0x020118 # font name_type_size .ascii " }" l9: .word 0xffd000 # color .word 25 # x .word 460 # y .word 0x020118 # font name_type_size .ascii "}" .end
source_codes/s/asmsim_examples.s/fonts.s
/* * fonts.s * Displays text on VGA (using a user-defined font_table) * The font_table stores characters' fonts (8x8 pixels for each) */ `define _Video_RAM 0xd0000000 # 0xd0000000 - 0xd007ffff # 1024(640) * 512(480) = 2^{10} * 2^{9} = 2^{19} # character: 32-bit: 24-bit RGB, 0, 7-bit ASCII .text # code segment main: # program entry subi $sp, $sp, 64 # reserve stack space sw $ra, 60($sp) # save return address sw $fp, 56($sp) # save frame pointer move $fp, $sp # new frame pointer user_main: jal refresh_vga_manu # refresh VGA manually # jal refresh_vga_auto # refresh automatically lui $6, 0xffff # char color = white ori $6, $6, 0xff00 # char color = white li $7, 0xa7233500 # for changing color fill_text: ori $5, $0, 0x20 # char = <Space> write_a_char: or $4, $6, $5 # color,ascii jal display_char # put pixels to video_ram addi $5, $5, 1 # next char andi $8, $5, 0x7f # if (ascii != 0x80) bne $8, $0, write_a_char coffee_break: jal paint # update VGA manually li $4, 100 # sleep time (ms) jal sleep # ZZZ...zzz... full_fill: sub $6, $6, $7 # change color la $4, text_row # address of row pointer lw $5, 0($4) # text row pointer subi $8, $5, 60 # if (text_row < 60) bltz $8, fill_text # continue return_to_caller(os): # exit(); move $sp, $fp # restore stack pointer lw $fp, 56($sp) # restore frame pointer lw $ra, 60($sp) # restore return address addi $sp, $sp, 64 # release stack space jr $ra # return to operating system display_char: # on vram, $4: {color,ascii} subi $sp, $sp, 64 # reserve stack space sw $ra, 60($sp) # save return address sw $fp, 56($sp) # save frame pointer sw $5, 52($sp) # save $5 sw $6, 48($sp) # save $6 sw $7, 44($sp) # save $7 sw $8, 40($sp) # save $8 sw $9, 36($sp) # save $9 sw $10, 32($sp) # save $10 sw $11, 28($sp) # save $11 sw $12, 24($sp) # save $12 sw $13, 20($sp) # save $13 sw $14, 16($sp) # save $14 sw $15, 12($sp) # save $15 move $fp, $sp # new frame pointer la $5, text_row lw $6, 0($5) # $6: text_row pointer lw $7, 4($5) # $7: text_col pointer andi $15, $4, 0x7f # get ascii, mask color subi $15, $15, 0x20 # - <Space> sll $15, $15, 3 # 8-byte fonts per char la $10, font_table # font_table address add $10, $10, $15 # font address of this char lw $11, 0($10) # get the 1st 32-bit fonts get_char_font: addi $8, $0, 0 # font_row = 0 font_row: addi $9, $0, 0 # font_col = 0 font_col: andi $14, $8, 3 # the last 2 bits of font_row sll $14, $14, 3 # 8 pixels per font row add $14, $14, $9 # {font_row[1:0],font_col}: 0 - 31 addi $15, $0, 31 # change to sub $14, $15, $14 # 31 - 0 for shift srlv $14, $11, $14 # $14 <- ($11 >>> $14) andi $14, $14, 1 # check LSB of shifted font beq $14, $0, to_write # if (LSB == 1) srl $14, $4, 8 # use char color; else black to_write: sll $12, $6, 3 # text_row * 8 add $12, $12, $8 # vram_row = text_row * 8 + font_row sll $13, $7, 3 # text_col * 8 add $13, $13, $9 # vram_col = text_col * 8 + font_col sll $15, $12, 10 # vram_row << 10 or $15, $15, $13 # + vram_col la $12, _Video_RAM # + vram base address add $15, $15, $12 # = vram address sw $14, 0($15) # write pixel to vram font_col_go_on: addi $9, $9, 1 # font_col++ subi $14, $9, 8 # if (font_col < 8) bltz $14, font_col # goto next font column font_row_go_on: addi $8, $8, 1 # font_row++ addi $14, $0, 4 # need 2nd half fonts? bne $14, $8, row_continue lw $11, 4($10) # get the 2nd 32-bit fonts row_continue: subi $14, $8, 8 # if (font_row < 8) bltz $14, font_row # goto next font row addi $7, $7, 1 # col++ ori $11, $0, 80 # if (text_col < 80) bne $11, $7, update_col # goto next column addi $6, $6, 1 # row++ sw $6, 0($5) # update text_row pointer addi $7, $0, 0 # col = 0 update_col: sw $7, 4($5) # update text_row pointer return_to_caller: # return move $sp, $fp # restore stack pointer lw $5, 52($sp) # restore $5 lw $6, 48($sp) # restore $6 lw $7, 44($sp) # restore $7 lw $8, 40($sp) # restore $8 lw $9, 36($sp) # restore $9 lw $10, 32($sp) # restore $10 lw $11, 28($sp) # restore $11 lw $12, 24($sp) # restore $12 lw $13, 20($sp) # restore $13 lw $14, 16($sp) # restore $14 lw $15, 12($sp) # restore $15 lw $fp, 56($sp) # restore frame pointer lw $ra, 60($sp) # restore return address addi $sp, $sp, 64 # release stack space jr $ra # return .data # data segment text_row: .word 0 # text row pointer text_col: .word 0 # text col pointer font_table: .word 0x00000000,0x00000000 # <SPACE> 20 .word 0x18181818,0x00181800 # ! 21 .word 0x6c6c4800,0x00000000 # " 22 .word 0x6c6cfe6c,0xfe6c6c00 # # 23 .word 0x187ed87e,0x1b7e1800 # $ 24 .word 0x62660c18,0x30664600 # % 25 .word 0x386c6876,0xdccc7600 # & 26 .word 0x18183000,0x00000000 # ' 27 .word 0x0c183030,0x30180c00 # ( 28 .word 0x30180c0c,0x0c183000 # ) 29 .word 0x006c38fe,0x386c0000 # * 2a .word 0x0018187e,0x18180000 # + 2b .word 0x00000000,0x00181810 # , 2c .word 0x0000007e,0x00000000 # - 2d .word 0x00000000,0x00181800 # . 2e .word 0x02060c18,0x30604000 # / 2f .word 0x3c666e76,0x66663c00 # 0 30 .word 0x18183818,0x18183c00 # 1 31 .word 0x7c06063c,0x60607c00 # 2 32 .word 0x7c06063c,0x06067c00 # 3 33 .word 0x6666667e,0x06060600 # 4 34 .word 0x7e60607c,0x06067c00 # 5 35 .word 0x3c60607c,0x66663c00 # 6 36 .word 0x7e060c18,0x18181800 # 7 37 .word 0x3c66663c,0x66663c00 # 8 38 .word 0x3c66663e,0x06063c00 # 9 39 .word 0x00181800,0x18180000 # : 3a .word 0x00001818,0x00181810 # ; 3b .word 0x0c183060,0x30180c00 # < 3c .word 0x00007e00,0x7e000000 # = 3d .word 0x30180c06,0x0c183000 # > 3e .word 0x3c66061c,0x18001800 # ? 3f .word 0x3c666e6a,0x6e603e00 # @ 40 .word 0x3c66667e,0x66666600 # A 41 .word 0x7c66667c,0x66667c00 # B 42 .word 0x3c666060,0x60663c00 # C 43 .word 0x7c666666,0x66667c00 # D 44 .word 0x7e60607c,0x60607e00 # E 45 .word 0x7e60607c,0x60606000 # F 46 .word 0x3c66606e,0x66663c00 # G 47 .word 0x6666667e,0x66666600 # H 48 .word 0x3c181818,0x18183c00 # I 49 .word 0x3e0c0c0c,0x0c6c3800 # J 4a .word 0x666c7870,0x786c6600 # K 4b .word 0x60606060,0x60607e00 # L 4c .word 0xc6eefed6,0xc6c6c600 # M 4d .word 0x6666767e,0x6e666600 # N 4e .word 0x3c666666,0x66663c00 # O 4f .word 0x7c66667c,0x60606000 # P 50 .word 0x3c666666,0x6e663e00 # Q 51 .word 0x7c66667c,0x66666600 # R 52 .word 0x3e60603c,0x06067c00 # S 53 .word 0x7e181818,0x18181800 # T 54 .word 0x66666666,0x66663c00 # U 55 .word 0x66666666,0x3c3c1800 # V 56 .word 0xc6c6d6d6,0xfeee4400 # W 57 .word 0x66663c18,0x3c666600 # X 58 .word 0x6666663c,0x18181800 # Y 59 .word 0x7e060c18,0x30607e00 # Z 5a .word 0x3c303030,0x30303c00 # [ 5b .word 0x40603018,0x0c060200 # \ 5c .word 0x3c0c0c0c,0x0c0c3c00 # ] 5d .word 0x10386c00,0x00000000 # ^ 5e .word 0x00000000,0x000000ff # _ 5f .word 0x18180c00,0x00000000 # ` 60 .word 0x00003c06,0x3e663a00 # a 61 .word 0x60607c66,0x66667c00 # b 62 .word 0x00003c66,0x60663c00 # c 63 .word 0x06063e66,0x66663e00 # d 64 .word 0x00003c66,0x7c603c00 # e 65 .word 0x0e18183e,0x18181800 # f 66 .word 0x00003e66,0x663e063c # g 67 .word 0x60607c66,0x66666600 # h 68 .word 0x18001818,0x18181800 # i 69 .word 0x18001818,0x18181870 # j 6a .word 0x6060666c,0x786c6600 # k 6b .word 0x30303030,0x30301c00 # l 6c .word 0x0000ccfe,0xd6c6c600 # m 6d .word 0x00007c66,0x66666600 # n 6e .word 0x00003c66,0x66663c00 # o 6f .word 0x00007c66,0x667c6060 # p 70 .word 0x00003e66,0x663e0606 # q 71 .word 0x00003638,0x30303000 # r 72 .word 0x00003e60,0x3c067c00 # s 73 .word 0x18183c18,0x18180c00 # t 74 .word 0x00006666,0x66663c00 # u 75 .word 0x00006666,0x663c1800 # v 76 .word 0x0000c6d6,0xd67c2800 # w 77 .word 0x0000663c,0x183c6600 # x 78 .word 0x00006666,0x663e067c # y 79 .word 0x00007e0c,0x18307e00 # z 7a .word 0x1c303060,0x30301c00 # { 7b .word 0x18181818,0x18181800 # | 7c .word 0x380c0c06,0x0c0c3800 # } 7d .word 0x00324c00,0x00000000 # ~ 7e .word 0xffffffff,0xffffffff # <DEL> 7f .end
source_codes/s/asmsim_examples.s/getarrow.s
/* * getarrow.s * getarrow(): gets pressed arrow key info. * Output: $2: key code: * 0x8000: Up * 0x8100: Left * 0x8200: Down * 0x8300: Right * 0xff00: Esc * 0x00xx: ASCII */ .text # code segment main: # program entry subi $sp, $sp, 64 # reserve stack space sw $ra, 60($sp) # save return address sw $fp, 56($sp) # save frame pointer move $fp, $sp # new frame pointer user_main: la $4, arrow_msg # address of message jal printf # print out message wait_for_pressing_an_arrow_key: jal getarrow # get an arrow key code store_key_code: la $4, arrow_code # address of arrow key code sw $2, 0($4) # store arrow key code print_bey_code: la $4, print_msg # address of message la $5, arrow_code # address of arrow key code lw $5, 0($5) # load arrow key code jal printf # print out message return_to_caller(os): # exit(); move $sp, $fp # restore stack pointer lw $fp, 56($sp) # restore frame pointer lw $ra, 60($sp) # restore return address addi $sp, $sp, 64 # release stack space jr $ra # return to operating system .data # data segment arrow_msg: .ascii "Press an arrow key: " arrow_code: # word address .word 0 # word print_msg: .ascii "The key code is: 0x%x\n" .end
source_codes/s/asmsim_examples.s/getcal.s
/* * getcal.s * getcals(): gets calendar in integer format * Input: $4: the pointer to the beginning of an * integer array where the month, data, year, day, * hour, minute, and second are stored in sequence. */ .text # code segment main: # program entry subi $sp, $sp, 64 # reserve stack space sw $ra, 60($sp) # save return address sw $fp, 56($sp) # save frame pointer move $fp, $sp # new frame pointer user_main: la $4, calendar # address of calendar jal getcal # get calendar print_calendar: la $3, calendar # address of calendar la $4, calendar_msg # address of parameter lw $5, 0x00($3) # load month lw $6, 0x04($3) # load date lw $7, 0x08($3) # load year lw $2, 0x10($3) # load hour sw $2, 16($sp) # put into stack lw $2, 0x14($3) # load minute sw $2, 20($sp) # put into stack lw $2, 0x18($3) # load second sw $2, 24($sp) # put into stack lw $2, 0x0c($3) # load day sw $2, 28($sp) # put into stack jal printf # printf out calendar return_to_caller(os): # exit(); move $sp, $fp # restore stack pointer lw $fp, 56($sp) # restore frame pointer lw $ra, 60($sp) # restore return address addi $sp, $sp, 64 # release stack space jr $ra # return to operating system .data # data segment calendar: .word 0 # month .word 0 # date .word 0 # year .word 0 # day .word 0 # hour .word 0 # minute .word 0 # second calendar_msg: .asciiz "%d %d %d %02d:%02d:%02d [%d]\n" .end
source_codes/s/asmsim_examples.s/getcals.s
/* * getcals.s * getcals(): gets calendar in string format * Input: $4: the address of buffer to store string */ .text # code segment main: # program entry subi $sp, $sp, 64 # reserve stack space sw $ra, 60($sp) # save return address sw $fp, 56($sp) # save frame pointer move $fp, $sp # new frame pointer user_main: la $4, g_cals # for getting cal string jal getcals # get calendar string la $4, g_cals # for getting cal string jal printf # print out message return_to_caller(os): # exit(); move $sp, $fp # restore stack pointer lw $fp, 56($sp) # restore frame pointer lw $ra, 60($sp) # restore return address addi $sp, $sp, 64 # release stack space jr $ra # return to operating system .data # data segment g_cals: .ascii "Dec 03 2011 Sat 23:46:53\n" .end
source_codes/s/asmsim_examples.s/getchar.s
/* * getchar.s * getchar(): gets a character from STDIN * Output: $2: the ASCII of the character */ .text # code segment main: # program entry subi $sp, $sp, 64 # reserve stack space sw $ra, 60($sp) # save return address sw $fp, 56($sp) # save frame pointer move $fp, $sp # new frame pointer user_main: la $4, input_char_msg # address of message jal printf # print out message jal getchar # input a character la $4, a_word # address of word sw $2, 0($4) # store the character print_out_the_string: la $4, output_msg # output message address jal printf # print out message move $4, $2 # prepare to print jal putchar # print out character la $4, enter # the place of the string [enter] jal printf # print out message return_to_caller(os): # exit(); move $sp, $fp # restore stack pointer lw $fp, 56($sp) # restore frame pointer lw $ra, 60($sp) # restore return address addi $sp, $sp, 64 # release stack space jr $ra # return to operating system .data # data segment input_char_msg: .ascii "Input a character (no need to press [Enter] key): " a_word: # the word address .word 0 # the word output_msg: .ascii "The character you inputted is " enter: .ascii "\n" # the character [enter] .end
source_codes/s/asmsim_examples.s/getrandom.s
/* * getrandom.s * getrandom(): gets a random integer number in [0, <range>) * Input: $4: the <range> * Output: $2: the number */ .text # code segment main: # program entry subi $sp, $sp, 64 # reserve stack space sw $ra, 60($sp) # save return address sw $fp, 56($sp) # save frame pointer move $fp, $sp # new frame pointer user_main: li $4, 100 # a random number 0 -- 99 jal getrandom # get a number 0 <= r < 100 la $4, a_word # address of a word sw $2, 0($4) # restore randow print_out_the_random_number: la $4, a_string # prepare to print out la $6, a_word # address of the word lw $5, 0($6) # load the word jal printf # print out return_to_caller(os): # exit(); move $sp, $fp # restore stack pointer lw $fp, 56($sp) # restore frame pointer lw $ra, 60($sp) # restore return address addi $sp, $sp, 64 # release stack space jr $ra # return to operating system .data # data segment a_string: # the string address .ascii "The random number in [0, 100) is %d\n" a_word: # the word address .word 0 # the word .end
source_codes/s/asmsim_examples.s/gettimer.s
/* * gettimer.s * gettimer(): gets the system timer in ms * Output: $2: the timer */ .text # code segment main: # program entry subi $sp, $sp, 64 # reserve stack space sw $ra, 60($sp) # save return address sw $fp, 56($sp) # save frame pointer move $fp, $sp # new frame pointer user_main: jal gettimer # gettimer la $4, timer # adrress of timer sw $2, 0($4) # restore timer la $4, timer_msg # adrress of timer message la $5, timer # adrress of timer lw $5, 0($5) # load timer jal printf # print out timer return_to_caller(os): # exit(); move $sp, $fp # restore stack pointer lw $fp, 56($sp) # restore frame pointer lw $ra, 60($sp) # restore return address addi $sp, $sp, 64 # release stack space jr $ra # return to operating system .data # data segment timer: .word 0 timer_msg: .ascii "The current timer shows %d\n" .end
source_codes/s/asmsim_examples.s/graphics.s
/* * graphics.s * Draws and fills graphics objects on VGA. Currently supports: * drawline() * drawoval() * drawrect() * drawrect3d() * drawstring() * filloval() * fillrect() * fillrect3d() * paint() * Note that only paint() paints VGA, others do in off-screen buffer * The parameters of each function call can be found in this example */ .text # code segment main: # program entry subi $sp, $sp, 64 # reserve stack space sw $ra, 60($sp) # save return address sw $fp, 56($sp) # save frame pointer move $fp, $sp # new frame pointer user_main: la $4, g_bgcolor # back ground color jal fillrect # fill rectangle draw_line: # draw in off-screen buffer la $4, g_drawline # draw a line parameters jal drawline # draw a line draw_oval: la $4, g_drawoval # draw a oval parameters jal drawoval # draw a oval draw_rect: la $4, g_drawrect # draw a rect parameters jal drawrect # draw a rect draw_3d_rect: la $4, g_drawrect3d # draw a rect parameters jal drawrect3d # draw a rect fill_oval: la $4, g_filloval # fill a oval parameters jal filloval # fill a oval fill_rect: la $4, g_fillrect # fill a rect parameters jal fillrect # fill a rect fill_3d_rect: la $4, g_fillrect3d # fill a rect parameters jal fillrect3d # fill a rect draw_my_canvas_string: la $4, g_drawstring # draw the string parameters jal drawstring # draw the string paint_on_canvas: jal paint # paint off-screen buffer return_to_caller(os): # exit(); move $sp, $fp # restore stack pointer lw $fp, 56($sp) # restore frame pointer lw $ra, 60($sp) # restore return address addi $sp, $sp, 64 # release stack space jr $ra # return to operating system .data # data segment g_bgcolor: .word 0xefafaf # color .word 0 # x .word 0 # y .word 640 # w .word 480 # h g_drawline: .word 0xff0000 # color .word 0 # x1 .word 0 # y1 .word 639 # x2 .word 479 # y2 g_drawoval: .word 0x004400 # color .word 410 # x .word 110 # y .word 150 # w .word 100 # h g_drawrect: .word 0x0000ff # color .word 400 # x .word 390 # y .word 80 # w .word 50 # h g_drawstring: .word 0x000000 # color .word 230 # x .word 80 # y .word 0x020128 # font name_type_size .ascii "myCanvas" # string g_filloval: .word 0x00ffff # color .word 10 # x .word 110 # y .word 150 # w .word 100 # h g_drawrect3d: .word 0xffff00 # color .word 250 # x .word 220 # y .word 50 # w .word 80 # h g_fillrect: .word 0xff00ff # color .word 50 # x .word 350 # y .word 80 # w .word 50 # h g_fillrect3d: .word 0x007f00 # color .word 350 # x .word 220 # y .word 80 # w .word 50 # h .end
source_codes/s/asmsim_examples.s/hello.s
/* * hello.s * Getting started, prints "Hello, World!" to STDOUT * Input: $4: the string address */ .text # code segment main: # program entry subi $sp, $sp, 24 # reserve stack space sw $ra, 20($sp) # save return address sw $fp, 16($sp) # save frame pointer move $fp, $sp # new frame pointer user_main: la $4, hello_msg # hello message address jal printf # print out message return_to_caller(os): # exit() move $sp, $fp # restore stack pointer lw $fp, 16($sp) # restore frame pointer lw $ra, 20($sp) # restore return address addi $sp, $sp, 24 # release stack space jr $ra # return to operating system .data # data segment hello_msg: # the string address .ascii "Hello, World!\n" # the string .end
source_codes/s/asmsim_examples.s/kanji.s
/* * kanji.s * Displays kanji on VGA (using a user-defined font_table) * The font_table stores kanji fonts (16x16 pixels for each) * 640/16 * 480/16 = 40 * 30 = 1200 kanji */ `define _Video_RAM 0xd0000000 # 0xd0000000 - 0xd007ffff # 1024(640) * 512(480) = 2^{10} * 2^{9} = 2^{19} # character: 32-bit: 16-bit color (R5,G6,B5), 16-bit kanji code .text # code segment main: # program entry subi $sp, $sp, 64 # reserve stack space sw $ra, 60($sp) # save return address sw $fp, 56($sp) # save frame pointer move $fp, $sp # new frame pointer user_main: jal refresh_vga_manu # refresh VGA manually # jal refresh_vga_auto # refresh automatically lui $6, 0xffff # char color = white lui $7, 54 # change color: 65536/1200 ori $9, $0, 0 # count = 0 write_a_kanji: ori $5, $0, 0 # kanji code = 0 write_continue: or $4, $6, $5 # color,kanji jal display_kanji # put pixels to video_ram addi $5, $5, 1 # next char addi $9, $9, 1 # count++ jal paint # update VGA manually li $4, 5 # sleep time (ms) jal sleep # ZZZ...zzz... sub $6, $6, $7 # change color next_text: subi $8, $9, 1200 # 30*40 bgez $8, return_to_caller(os) subi $8, $5, 639 # if (kanji < (94+94+94+83+86+94+94)) bltz $8, write_continue j write_a_kanji # continue return_to_caller(os): # exit(); move $sp, $fp # restore stack pointer lw $fp, 56($sp) # restore frame pointer lw $ra, 60($sp) # restore return address addi $sp, $sp, 64 # release stack space jr $ra # return to operating system display_kanji: # on vram, $4: {color,kanji} subi $sp, $sp, 64 # reserve stack space sw $ra, 60($sp) # save return address sw $fp, 56($sp) # save frame pointer sw $5, 52($sp) # save $5 sw $6, 48($sp) # save $6 sw $7, 44($sp) # save $7 sw $8, 40($sp) # save $8 sw $9, 36($sp) # save $9 sw $10, 32($sp) # save $10 sw $11, 28($sp) # save $11 sw $12, 24($sp) # save $12 sw $13, 20($sp) # save $13 sw $14, 16($sp) # save $14 sw $15, 12($sp) # save $15 move $fp, $sp # new frame pointer la $5, text_row lw $6, 0($5) # $6: text_row pointer lw $7, 4($5) # $7: text_col pointer andi $15, $4, 0xffff # get kanji, mask color sll $15, $15, 5 # 32-byte fonts per kanji la $10, font_table # font_table address add $10, $10, $15 # font address of this kanji lw $11, 0($10) # get the 1st 32-bit fonts addi $10, $10, 4 # address of next font word get_char_font: addi $8, $0, 0 # font_row = 0..15 font_row: addi $9, $0, 0 # font_col = 0..15 font_col: andi $14, $8, 1 # the LSB of font_row sll $14, $14, 4 # 16 pixels per font row add $14, $14, $9 # {font_row[0],font_col}: 0 - 31 addi $15, $0, 31 # change to sub $14, $15, $14 # 31 - 0 for shift srlv $14, $11, $14 # $14 <- ($11 >>> $14) andi $14, $14, 1 # check LSB of shifted font beq $14, $0, to_write # if == 0, black red: srl $12, $4, 27 # 5-bit red sll $13, $12, 8 sub $12, $13, $12 # * 255 addi $13, $0, 31 divu $12, $13 # / 31 mflo $12 sll $14, $12, 16 # red green: srl $12, $4, 21 # green andi $12, $12, 0x3f # 6-bit sll $13, $12, 8 sub $12, $13, $12 # * 255 addi $13, $0, 63 divu $12, $13 # / 63 mflo $12 sll $12, $12, 8 # green or $14, $14, $12 # red,green blue: srl $12, $4, 16 # blue andi $12, $12, 0x1f # 5-bit sll $13, $12, 8 sub $12, $13, $12 # * 255 addi $13, $0, 31 divu $12, $13 # / 31 mflo $12 or $14, $14, $12 # red,green,blue to_write: sll $12, $6, 4 # text_row * 16 add $12, $12, $8 # vram_row = text_row * 16 + font_row sll $13, $7, 4 # text_col * 16 add $13, $13, $9 # vram_col = text_col * 16 + font_col sll $15, $12, 10 # vram_row << 10 or $15, $15, $13 # + vram_col la $12, _Video_RAM # + vram base address add $15, $15, $12 # = vram address sw $14, 0($15) # write pixel to vram font_col_go_on: addi $9, $9, 1 # font_col++ subi $14, $9, 16 # if (font_col < 16) bltz $14, font_col # goto next font column font_row_go_on: addi $8, $8, 1 # font_row++ andi $14, $8, 1 # need next font word? bne $14, $0, row_continue lw $11, 0($10) # get the next 32-bit fonts addi $10, $10, 4 # address of next font word row_continue: subi $14, $8, 16 # if (font_row < 16) bltz $14, font_row # goto next font row addi $7, $7, 1 # col++ ori $11, $0, 40 # if (text_col < 40) bne $11, $7, update_col # goto next column addi $6, $6, 1 # row++ sw $6, 0($5) # update text_row pointer addi $7, $0, 0 # col = 0 update_col: sw $7, 4($5) # update text_row pointer return_to_caller: # return move $sp, $fp # restore stack pointer lw $5, 52($sp) # restore $5 lw $6, 48($sp) # restore $6 lw $7, 44($sp) # restore $7 lw $8, 40($sp) # restore $8 lw $9, 36($sp) # restore $9 lw $10, 32($sp) # restore $10 lw $11, 28($sp) # restore $11 lw $12, 24($sp) # restore $12 lw $13, 20($sp) # restore $13 lw $14, 16($sp) # restore $14 lw $15, 12($sp) # restore $15 lw $fp, 56($sp) # restore frame pointer lw $ra, 60($sp) # restore return address addi $sp, $sp, 64 # release stack space jr $ra # return .data # data segment text_row: .word 0 # text row pointer text_col: .word 0 # text col pointer font_table: # 16x16 font: http://www12.ocn.ne.jp/~imamura/jisx0213.html .word 0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000 # euc_jp encoding a1a1 .word 0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00006000,0x30001000 # euc_jp encoding a1a2 .word 0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x60009000,0x90006000 # euc_jp encoding a1a3 .word 0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x60006000,0x20004000 # euc_jp encoding a1a4 .word 0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x60006000,0x00000000 # euc_jp encoding a1a5 .word 0x00000000,0x00000000,0x00000000,0x00000180,0x01800000,0x00000000,0x00000000,0x00000000 # euc_jp encoding a1a6 .word 0x00000000,0x00000000,0x00000000,0x01800180,0x00000000,0x00000000,0x01800180,0x00000000 # euc_jp encoding a1a7 .word 0x00000000,0x00000000,0x00000000,0x01800180,0x00000000,0x00000000,0x01800180,0x00800100 # euc_jp encoding a1a8 .word 0x000007e0,0x08101008,0x10080808,0x003000c0,0x01000100,0x00000000,0x01800180,0x00000000 # euc_jp encoding a1a9 .word 0x00000180,0x01800180,0x01800180,0x01000100,0x01000100,0x00000000,0x01800180,0x00000000 # euc_jp encoding a1aa .word 0x50005000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000 # euc_jp encoding a1ab .word 0x00000000,0x60009000,0x90006000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000 # euc_jp encoding a1ac .word 0x00c00080,0x01000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000 # euc_jp encoding a1ad .word 0x03000100,0x00800000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000 # euc_jp encoding a1ae .word 0x06600660,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000 # euc_jp encoding a1af .word 0x01800660,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000 # euc_jp encoding a1b0 .word 0xffff0000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000 # euc_jp encoding a1b1 .word 0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x0000ffff # euc_jp encoding a1b2 .word 0x00000000,0x00000000,0x06000300,0x018000c0,0x00600020,0x00300010,0x00000000,0x00000000 # euc_jp encoding a1b3 .word 0x00000000,0x00000050,0x0c500600,0x03000180,0x00c00040,0x00600020,0x00000000,0x00000000 # euc_jp encoding a1b4 .word 0x00000000,0x00000800,0x0c000600,0x030001c0,0x00600030,0x006001c0,0x03000000,0x00000000 # euc_jp encoding a1b5 .word 0x00000000,0x00000828,0x0c280600,0x030001c0,0x00600030,0x006001c0,0x03000000,0x00000000 # euc_jp encoding a1b6 .word 0x00000000,0x00000420,0x04200420,0x04200420,0x04200420,0x08400840,0x10800000,0x00000000 # euc_jp encoding a1b7 .word 0x01000380,0x06c00c60,0x1830301c,0xe0070000,0x3ffc0100,0x01000100,0x01000100,0xffff0000 # euc_jp encoding a1b8 .word 0x00000200,0x02000200,0x07f80408,0x0c180810,0x18303360,0x01c00060,0x00300010,0x00000000 # euc_jp encoding a1b9 .word 0x00000006,0x000c0018,0x073009e0,0x10c011e0,0x33302600,0x2c002800,0x38003000,0x60000000 # euc_jp encoding a1ba .word 0x00000000,0x07e01c38,0x300c2004,0x60064002,0x40026006,0x2004300c,0x1c3807e0,0x00000000 # euc_jp encoding a1bb .word 0x00000000,0x00000000,0x00000000,0x40003ffe,0x00000000,0x00000000,0x00000000,0x00000000 # euc_jp encoding a1bc .word 0x00000000,0x00000000,0x00000000,0x0000ffff,0x00000000,0x00000000,0x00000000,0x00000000 # euc_jp encoding a1bd .word 0x00000000,0x00000000,0x00000000,0x000007e0,0x00000000,0x00000000,0x00000000,0x00000000 # euc_jp encoding a1be .word 0x00010002,0x00040008,0x00100020,0x00400080,0x01000200,0x04000800,0x10002000,0x40008000 # euc_jp encoding a1bf .word 0x80004000,0x20001000,0x08000400,0x02000100,0x00800040,0x00200010,0x00080004,0x00020001 # euc_jp encoding a1c0 .word 0x00000000,0x00000000,0x00000000,0x3c004301,0x80c2003c,0x00000000,0x00000000,0x00000000 # euc_jp encoding a1c1 .word 0x04400440,0x04400440,0x04400440,0x04400440,0x04400440,0x04400440,0x04400440,0x04400440 # euc_jp encoding a1c2 .word 0x01000100,0x01000100,0x01000100,0x01000100,0x01000100,0x01000100,0x01000100,0x01000100 # euc_jp encoding a1c3 .word 0x00000000,0x00000000,0x00000000,0x0000618c,0x618c0000,0x00000000,0x00000000,0x00000000 # euc_jp encoding a1c4 .word 0x00000000,0x00000000,0x00000000,0x00001818,0x18180000,0x00000000,0x00000000,0x00000000 # euc_jp encoding a1c5 .word 0x00080010,0x00180018,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000 # euc_jp encoding a1c6 .word 0x18001800,0x08001000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000 # euc_jp encoding a1c7 .word 0x00240048,0x006c006c,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000 # euc_jp encoding a1c8 .word 0x36003600,0x12002400,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000 # euc_jp encoding a1c9 .word 0x00080010,0x00300020,0x00600040,0x00400040,0x00400040,0x00400060,0x00200030,0x00100008 # euc_jp encoding a1ca .word 0x10000800,0x0c000400,0x06000200,0x02000200,0x02000200,0x02000600,0x04000c00,0x08001000 # euc_jp encoding a1cb .word 0x00080030,0x00c00080,0x00800080,0x00800080,0x00800080,0x00800080,0x008000c0,0x00300008 # euc_jp encoding a1cc .word 0x10000c00,0x03000100,0x01000100,0x01000100,0x01000100,0x01000100,0x01000300,0x0c001000 # euc_jp encoding a1cd .word 0x00f80080,0x00800080,0x00800080,0x00800080,0x00800080,0x00800080,0x00800080,0x008000f8 # euc_jp encoding a1ce .word 0x1f000100,0x01000100,0x01000100,0x01000100,0x01000100,0x01000100,0x01000100,0x01001f00 # euc_jp encoding a1cf .word 0x00080010,0x00200020,0x00200020,0x00200040,0x00200020,0x00200020,0x00200020,0x00100008 # euc_jp encoding a1d0 .word 0x10000800,0x04000400,0x04000400,0x04000200,0x04000400,0x04000400,0x04000400,0x08001000 # euc_jp encoding a1d1 .word 0x00080010,0x00100020,0x00400040,0x00800100,0x01000080,0x00400040,0x00200010,0x00100008 # euc_jp encoding a1d2 .word 0x10000800,0x08000400,0x02000200,0x01000080,0x00800100,0x02000200,0x04000800,0x08001000 # euc_jp encoding a1d3 .word 0x00120024,0x00240048,0x00900090,0x01200240,0x02400120,0x00900090,0x00480024,0x00240012 # euc_jp encoding a1d4 .word 0x48002400,0x24001200,0x09000900,0x04800240,0x02400480,0x09000900,0x12002400,0x24004800 # euc_jp encoding a1d5 .word 0x00f80080,0x00800080,0x00800080,0x00800080,0x00800080,0x00800000,0x00000000,0x00000000 # euc_jp encoding a1d6 .word 0x00000000,0x00000000,0x00000100,0x01000100,0x01000100,0x01000100,0x01000100,0x01001f00 # euc_jp encoding a1d7 .word 0x01f80108,0x01780140,0x01400140,0x01400140,0x01400140,0x01c00000,0x00000000,0x00000000 # euc_jp encoding a1d8 .word 0x00000000,0x00000000,0x00000380,0x02800280,0x02800280,0x02800280,0x02801e80,0x10801f80 # euc_jp encoding a1d9 .word 0x00f800f0,0x00e000c0,0x00c00080,0x00800080,0x00800080,0x008000c0,0x00c000e0,0x00f000f8 # euc_jp encoding a1da .word 0x1f000f00,0x07000300,0x03000100,0x01000100,0x01000100,0x01000300,0x03000700,0x0f001f00 # euc_jp encoding a1db .word 0x00000000,0x01000100,0x01000100,0x01003ffc,0x01000100,0x01000100,0x01000100,0x00000000 # euc_jp encoding a1dc .word 0x00000000,0x00000000,0x00000000,0x00003ffc,0x00000000,0x00000000,0x00000000,0x00000000 # euc_jp encoding a1dd .word 0x00000000,0x01000100,0x01000100,0x3ffc0100,0x01000100,0x01000000,0x00003ffc,0x00000000 # euc_jp encoding a1de .word 0x00000000,0x00001008,0x08100420,0x02400180,0x01800240,0x04200810,0x10080000,0x00000000 # euc_jp encoding a1df .word 0x00000000,0x00000180,0x01800000,0x00003ffc,0x00000000,0x01800180,0x00000000,0x00000000 # euc_jp encoding a1e0 .word 0x00000000,0x00000000,0x00003ffc,0x00000000,0x00003ffc,0x00000000,0x00000000,0x00000000 # euc_jp encoding a1e1 .word 0x00000000,0x00400040,0x00803ffc,0x00800100,0x01003ffc,0x01000200,0x02000000,0x00000000 # euc_jp encoding a1e2 .word 0x00000006,0x00180060,0x01800600,0x18006000,0x18000400,0x030000c0,0x00200018,0x00060000 # euc_jp encoding a1e3 .word 0x00006000,0x18000600,0x01800060,0x00180006,0x00180020,0x00c00300,0x04001800,0x60000000 # euc_jp encoding a1e4 .word 0x00000000,0x001c00e0,0x07003800,0x070000e0,0x001c0000,0x3ffc0000,0x00003ffc,0x00000000 # euc_jp encoding a1e5 .word 0x00000000,0x38000700,0x00e0001c,0x00e00700,0x38000000,0x3ffc0000,0x00003ffc,0x00000000 # euc_jp encoding a1e6 .word 0x00000000,0x00000000,0x1c382244,0x41824182,0x41824182,0x22441c38,0x00000000,0x00000000 # euc_jp encoding a1e7 .word 0x00000000,0x00000180,0x01800000,0x00000000,0x00000000,0x0000300c,0x300c0000,0x00000000 # euc_jp encoding a1e8 .word 0x000000fe,0x0006000a,0x00120022,0x00421e82,0x21004080,0x40804080,0x40802100,0x1e000000 # euc_jp encoding a1e9 .word 0x000003c0,0x04200810,0x08100810,0x08100420,0x03c00100,0x1ff80100,0x01000100,0x01000100 # euc_jp encoding a1ea .word 0x00003000,0x48004800,0x30000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000 # euc_jp encoding a1eb .word 0x00000800,0x18003000,0x20000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000 # euc_jp encoding a1ec .word 0x00001100,0x33006600,0x44000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000 # euc_jp encoding a1ed .word 0x000060f2,0x930a9606,0x64020c02,0x08000800,0x08000c00,0x04020606,0x030c00f0,0x00000000 # euc_jp encoding a1ee .word 0x00007c3e,0x10081008,0x08107ffe,0x04200440,0x02807ffe,0x01000100,0x01000100,0x07c00000 # euc_jp encoding a1ef .word 0x00000100,0x07e00930,0x11181100,0x09000700,0x01e00110,0x01081108,0x19100fe0,0x01000000 # euc_jp encoding a1f0 .word 0x00000000,0x00000000,0x00000020,0x03c00460,0x08900880,0x09000900,0x061003e0,0x04000000 # euc_jp encoding a1f1 .word 0x000001f0,0x02080404,0x04000400,0x04000400,0x7ff00200,0x02003a00,0x46024584,0x38780000 # euc_jp encoding a1f2 .word 0x00003802,0x44044408,0x44104420,0x44403880,0x011c0222,0x04220822,0x10222022,0x401c0000 # euc_jp encoding a1f3 .word 0x02100210,0x02100210,0x1ffc1ffc,0x04200420,0x04200420,0x3ff83ff8,0x08400840,0x08400840 # euc_jp encoding a1f4 .word 0x00000f00,0x18801080,0x11801b00,0x0e7c0c10,0x1e303320,0x61e040c0,0x41e22336,0x1e1c0000 # euc_jp encoding a1f5 .word 0x00000000,0x00000000,0x01001930,0x0d6007c0,0x010007c0,0x0d601930,0x01000000,0x00000000 # euc_jp encoding a1f6 .word 0x00000000,0x03c00c30,0x100811a8,0x22642444,0x244424c8,0x13701004,0x0c1803e0,0x00000000 # euc_jp encoding a1f7 .word 0x000007c0,0x0c700c30,0x0e000780,0x0ce00830,0x0c100730,0x01e00070,0x0c300e30,0x03e00000 # euc_jp encoding a1f8 .word 0x00000100,0x02800280,0x04400440,0x7c7c2008,0x10100820,0x08201110,0x12902c68,0x30180000 # euc_jp encoding a1f9 .word 0x00000100,0x01000380,0x038007c0,0x7ffc3ff8,0x1ff00fe0,0x0fe01ef0,0x1c703838,0x20080000 # euc_jp encoding a1fa .word 0x000003c0,0x0c301008,0x20042004,0x40024002,0x40024002,0x20042004,0x10080c30,0x03c00000 # euc_jp encoding a1fb .word 0x000003c0,0x0ff01ff8,0x3ffc3ffc,0x7ffe7ffe,0x7ffe7ffe,0x3ffc3ffc,0x1ff80ff0,0x03c00000 # euc_jp encoding a1fc .word 0x000003c0,0x0c301008,0x23c42424,0x48124812,0x48124812,0x242423c4,0x10080c30,0x03c00000 # euc_jp encoding a1fd .word 0x01800240,0x04200810,0x10082004,0x40028001,0x80014002,0x20041008,0x08100420,0x02400180 # euc_jp encoding a1fe .word 0x018003c0,0x07e00ff0,0x1ff83ffc,0x7ffeffff,0xffff7ffe,0x3ffc1ff8,0x0ff007e0,0x03c00180 # euc_jp encoding a2a1 .word 0x00007ffe,0x40024002,0x40024002,0x40024002,0x40024002,0x40024002,0x40024002,0x7ffe0000 # euc_jp encoding a2a2 .word 0x00007ffe,0x7ffe7ffe,0x7ffe7ffe,0x7ffe7ffe,0x7ffe7ffe,0x7ffe7ffe,0x7ffe7ffe,0x7ffe0000 # euc_jp encoding a2a3 .word 0x00000000,0x01000280,0x02800440,0x04400820,0x08101010,0x10082008,0x20047ffe,0x00000000 # euc_jp encoding a2a4 .word 0x00000000,0x01000380,0x038007c0,0x07e00fe0,0x0ff01ff0,0x1ff83ffc,0x3ffc7ffe,0x00000000 # euc_jp encoding a2a5 .word 0x00000000,0x7ffe2004,0x20081008,0x10100810,0x08200440,0x04400280,0x02800100,0x00000000 # euc_jp encoding a2a6 .word 0x00000000,0x7ffe3ffc,0x3ffc1ff8,0x1ff00ff0,0x0fe007e0,0x07c00380,0x03800100,0x00000000 # euc_jp encoding a2a7 .word 0x00000000,0x21841188,0x08100420,0x0240318c,0x318c0240,0x04200810,0x11882184,0x00000000 # euc_jp encoding a2a8 .word 0x00007ffe,0x7ffe0000,0x00007ffe,0x7ffe0180,0x01800180,0x01800180,0x01800180,0x01800000 # euc_jp encoding a2a9 .word 0x00000000,0x00000000,0x00000008,0x0004ffff,0x00040008,0x00000000,0x00000000,0x00000000 # euc_jp encoding a2aa .word 0x00000000,0x00000000,0x00001000,0x2000ffff,0x20001000,0x00000000,0x00000000,0x00000000 # euc_jp encoding a2ab .word 0x01000100,0x03800540,0x01000100,0x01000100,0x01000100,0x01000100,0x01000100,0x01000100 # euc_jp encoding a2ac .word 0x01000100,0x01000100,0x01000100,0x01000100,0x01000100,0x01000100,0x05400380,0x01000100 # euc_jp encoding a2ad .word 0x00000000,0x7ffe7ffe,0x7ffe7ffe,0x00000000,0x00007ffe,0x7ffe7ffe,0x7ffe0000,0x00000000 # euc_jp encoding a2ae .word 0x01c001c0,0x00800080,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000 # euc_jp encoding a2af .word 0x07700770,0x02200220,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000 # euc_jp encoding a2b0 .word 0x00000000,0x00000000,0x00000000,0x000007e0,0x07e00000,0x00000000,0x00000000,0x00000000 # euc_jp encoding a2b1 .word 0x00000710,0x08e00000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000 # euc_jp encoding a2b2 .word 0x00000000,0x00000000,0x00001c00,0x070001c0,0x00600030,0x0018000c,0x00060003,0x00000000 # euc_jp encoding a2b3 .word 0x00000600,0x0c000180,0x03001c00,0x07000180,0x00600030,0x0018000c,0x00060003,0x00000000 # euc_jp encoding a2b4 .word 0x00000000,0x00000000,0x00000018,0x007000c0,0x03800600,0x0c003800,0x6000c000,0x00000000 # euc_jp encoding a2b5 .word 0x00000000,0x03000180,0x00c00060,0x01800200,0x03000180,0x00c00060,0x00300000,0x00000000 # euc_jp encoding a2b6 .word 0x00007ffe,0x4006400a,0x40124022,0x40424082,0x41024202,0x44024802,0x50026002,0x7ffe0000 # euc_jp encoding a2b7 .word 0x00000000,0x1ff80008,0x00080008,0x00080008,0x00080008,0x00080008,0x00080008,0x00080000 # euc_jp encoding a2b8 .word 0x00800080,0x018001f8,0x03000200,0x020002f0,0x07180408,0x0c080808,0x18181330,0x11e00000 # euc_jp encoding a2b9 .word 0x00000000,0x000007f8,0x08001000,0x10001ff8,0x10001000,0x080007f8,0x00000000,0x00000000 # euc_jp encoding a2ba .word 0x00000000,0x00001fe0,0x00100008,0x00081ff8,0x00080008,0x00101fe0,0x00000000,0x00000000 # euc_jp encoding a2bb .word 0x00000000,0x0ffc1000,0x20002000,0x20002000,0x10000ffc,0x00000000,0x3ffc0000,0x00000000 # euc_jp encoding a2bc .word 0x00000000,0x3ff00008,0x00040004,0x00040004,0x00083ff0,0x00000000,0x3ffc0000,0x00000000 # euc_jp encoding a2bd .word 0x00000000,0x000007fc,0x08001000,0x20002000,0x20002000,0x10000800,0x07fc0000,0x00000000 # euc_jp encoding a2be .word 0x00000000,0x00003fe0,0x00100008,0x00040004,0x00040004,0x00080010,0x3fe00000,0x00000000 # euc_jp encoding a2bf .word 0x00000000,0x10081008,0x10081008,0x10081008,0x10081008,0x10080810,0x042003c0,0x00000000 # euc_jp encoding a2c0 .word 0x00000000,0x03c00420,0x08101008,0x10081008,0x10081008,0x10081008,0x10081008,0x00000000 # euc_jp encoding a2c1 .word 0x00000000,0x000807fc,0x08101020,0x20202040,0x20802100,0x11000a00,0x07fc0400,0x00000000 # euc_jp encoding a2c2 .word 0x00000000,0x00203fe0,0x00500088,0x00840104,0x02040404,0x04080810,0x3fe01000,0x00000000 # euc_jp encoding a2c3 .word 0x00000000,0x0ffc1000,0x20002000,0x20002000,0x10000ffc,0x00400040,0x3ffc0080,0x01000100 # euc_jp encoding a2c4 .word 0x00000000,0x3ff00008,0x00040004,0x00040004,0x00083ff0,0x00400040,0x3ffc0080,0x01000100 # euc_jp encoding a2c5 .word 0x00000080,0x008007f8,0x08801080,0x10801ff8,0x10801080,0x088007f8,0x00800080,0x00000000 # euc_jp encoding a2c6 .word 0x00000000,0x000403c8,0x04300830,0x10481088,0x11081208,0x0c100c20,0x13c02000,0x00000000 # euc_jp encoding a2c7 .word 0x00000000,0x00000000,0x00003ffc,0x01800240,0x04200810,0x10082004,0x00000000,0x00000000 # euc_jp encoding a2c8 .word 0x00000000,0x00003ffc,0x00000000,0x3ffc0180,0x02400420,0x08101008,0x20040000,0x00000000 # euc_jp encoding a2c9 .word 0x00000000,0x01000100,0x02800280,0x04400440,0x08200820,0x10101010,0x20082008,0x00000000 # euc_jp encoding a2ca .word 0x00000000,0x20082008,0x10101010,0x08200820,0x04400440,0x02800280,0x01000100,0x00000000 # euc_jp encoding a2cb .word 0x00000000,0x00000000,0x00000000,0x3ffc0004,0x00040004,0x00040000,0x00000000,0x00000000 # euc_jp encoding a2cc .word 0x00000000,0x00000010,0x0008fffc,0x00020001,0x0002fffc,0x00080010,0x00000000,0x00000000 # euc_jp encoding a2cd .word 0x00000000,0x00000810,0x10083ffc,0x40028001,0x40023ffc,0x10080810,0x00000000,0x00000000 # euc_jp encoding a2ce .word 0x00004004,0x40042008,0x20081ff0,0x10100820,0x08200440,0x04400280,0x02800100,0x01000000 # euc_jp encoding a2cf .word 0x00000000,0x1ff00010,0x00100010,0x00101ff0,0x00100010,0x00100010,0x1ff00000,0x00000000 # euc_jp encoding a2d0 .word 0x000003c0,0x0c301108,0x21042104,0x41025ffa,0x41024102,0x21042104,0x11080c30,0x03c00000 # euc_jp encoding a2d1 .word 0x000003c0,0x0c301008,0x20042004,0x40025ffa,0x40024002,0x20042004,0x10080c30,0x03c00000 # euc_jp encoding a2d2 .word 0x000003c0,0x0c301008,0x28142424,0x42424182,0x41824242,0x24242814,0x10080c30,0x03c00000 # euc_jp encoding a2d3 .word 0x00400084,0x00840108,0x01080210,0x02100420,0x04200840,0x08401080,0x10802100,0x21000200 # euc_jp encoding a2d4 .word 0x00400084,0x00841108,0x09080610,0x02100520,0x04a00840,0x08601090,0x10882100,0x21000200 # euc_jp encoding a2d5 .word 0x00440088,0x01100110,0x02200220,0x02200220,0x02200220,0x02200220,0x01100110,0x00880044 # euc_jp encoding a2d6 .word 0x22001100,0x08800880,0x04400440,0x04400440,0x04400440,0x04400440,0x08800880,0x11002200 # euc_jp encoding a2d7 .word 0x001c0060,0x018c0130,0x01200120,0x01200120,0x01200120,0x01200120,0x0130018c,0x0060001c # euc_jp encoding a2d8 .word 0x38000600,0x31800c80,0x04800480,0x04800480,0x04800480,0x04800480,0x0c803180,0x06003800 # euc_jp encoding a2d9 .word 0x01fc0108,0x01100120,0x01200140,0x01400140,0x01400140,0x01400120,0x01200110,0x010801fc # euc_jp encoding a2da .word 0x3f801080,0x08800480,0x04800280,0x02800280,0x02800280,0x02800480,0x04800880,0x10803f80 # euc_jp encoding a2db .word 0x00000000,0x00080010,0x00200040,0x00800100,0x02000400,0x08001000,0x3ffc0000,0x00000000 # euc_jp encoding a2dc .word 0x00000000,0x01000100,0x01000100,0x01000100,0x01000100,0x01000100,0x3ffc0000,0x00000000 # euc_jp encoding a2dd .word 0x07e0381c,0xc0030000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000 # euc_jp encoding a2de .word 0x000001e0,0x03300410,0x00100010,0x03b00460,0x08201860,0x104010c0,0x19800f00,0x00000000 # euc_jp encoding a2df .word 0x00007ffe,0x3004300c,0x18081818,0x0c100c30,0x06200660,0x034003c0,0x01800180,0x00000000 # euc_jp encoding a2e0 .word 0x00000000,0x00003ffc,0x00000000,0x00003ffc,0x00000000,0x00003ffc,0x00000000,0x00000000 # euc_jp encoding a2e1 .word 0x00000000,0x18001800,0x00003ffc,0x00000000,0x00003ffc,0x00000018,0x00180000,0x00000000 # euc_jp encoding a2e2 .word 0x00000042,0x00840318,0x042018c0,0x21004200,0x21001080,0x08400630,0x01080084,0x00420000 # euc_jp encoding a2e3 .word 0x00004200,0x210018c0,0x04200318,0x00840042,0x00840108,0x02100c60,0x10802100,0x42000000 # euc_jp encoding a2e4 .word 0x00ff0080,0x00800100,0x01000100,0x01000200,0x02000200,0x22007400,0xb4001c00,0x18000800 # euc_jp encoding a2e5 .word 0x00000000,0x00000000,0x1c382044,0x40824082,0x41024102,0x22041c38,0x00000000,0x00000000 # euc_jp encoding a2e6 .word 0x00000000,0x00000000,0x1c382244,0x41804180,0x41804180,0x22441c38,0x00000000,0x00000000 # euc_jp encoding a2e7 .word 0x00000000,0x0000300c,0x300c0000,0x00000000,0x00000000,0x00000180,0x01800000,0x00000000 # euc_jp encoding a2e8 .word 0x01c00240,0x02000200,0x03000300,0x01000180,0x01800080,0x00c000c0,0x00400040,0x02400380 # euc_jp encoding a2e9 .word 0x0e381248,0x10401040,0x18601860,0x08200c30,0x0c300410,0x06180618,0x02080208,0x12481c70 # euc_jp encoding a2ea .word 0x00200020,0x00407ffe,0x00400080,0x00807ffe,0x01000100,0x02007ffe,0x02000400,0x04000000 # euc_jp encoding a2eb .word 0x00000000,0x00001c02,0x230240c4,0x40380000,0x00000000,0x7ffe0000,0x00000000,0x00000000 # euc_jp encoding a2ec .word 0x00000000,0x00001c02,0x230240c4,0x40380000,0x00007ffe,0x00000000,0x7ffe0000,0x00000000 # euc_jp encoding a2ed .word 0x00000000,0x00000000,0x1e022182,0x40444038,0x1e022102,0x40c44038,0x00000000,0x00000000 # euc_jp encoding a2ee .word 0x0000001c,0x00e00700,0x38000700,0x00e0381c,0x070000e0,0x001c00e0,0x07003800,0x00000000 # euc_jp encoding a2ef .word 0x00003800,0x070000e0,0x001c00e0,0x0700381c,0x00e00700,0x38000700,0x00e0001c,0x00000000 # euc_jp encoding a2f0 .word 0x00000000,0x00000000,0x00001008,0x2004ffff,0x20041008,0x00000000,0x00000000,0x00000000 # euc_jp encoding a2f1 .word 0x01800240,0x02400180,0x00000100,0x02800280,0x04400420,0x0ff00810,0x10087c3e,0x00000000 # euc_jp encoding a2f2 .word 0x00003040,0x48404880,0x49004900,0x4a003400,0x058c0a52,0x12521252,0x22524252,0x418c0000 # euc_jp encoding a2f3 .word 0x00200420,0x0420043c,0x07fc3fe0,0x3c200420,0x0420043c,0x07fc3fe0,0x3c200420,0x04200400 # euc_jp encoding a2f4 .word 0x04000400,0x04000400,0x04000400,0x05e00630,0x04300430,0x04300460,0x04c00500,0x06000400 # euc_jp encoding a2f5 .word 0x00800080,0x00c000e0,0x00b00098,0x008c0084,0x00840088,0x00900080,0x0f801f80,0x1f000e00 # euc_jp encoding a2f6 .word 0x01000380,0x09201ff0,0x09200100,0x07c00380,0x03800380,0x03800380,0x01000100,0x01000100 # euc_jp encoding a2f7 .word 0x01000380,0x09201ff0,0x09200380,0x03800100,0x01000380,0x03800920,0x1ff00920,0x03800100 # euc_jp encoding a2f8 .word 0x000007e0,0x0f201f20,0x1f201f20,0x0f200720,0x01200120,0x01200120,0x01200120,0x01200120 # euc_jp encoding a2f9 .word 0x00000400,0x04000400,0x047007f0,0x07900410,0x04100410,0x04f007f0,0x07100010,0x00100010 # euc_jp encoding a2fa .word 0x070007e0,0x07fc04fc,0x041c0404,0x04040404,0x04040404,0x3c047c04,0x783c307c,0x00780030 # euc_jp encoding a2fb .word 0x078007f0,0x047c070c,0x07e404fc,0x041c0404,0x04040404,0x3c047c04,0x783c307c,0x00780030 # euc_jp encoding a2fc .word 0x00800080,0x00800080,0x00800080,0x00800080,0x00800080,0x00800080,0x0f801f80,0x1f000e00 # euc_jp encoding a2fd .word 0x03c00c30,0x10082004,0x40024002,0x80018001,0x80018001,0x40024002,0x20041008,0x0c3003c0 # euc_jp encoding a2fe .word 0x00002000,0x38002600,0x21802060,0x20182004,0x20182060,0x20802300,0x2c003000,0x20000000 # euc_jp encoding a3a1 .word 0x00002000,0x38003e00,0x3f803fe0,0x3ff83ffc,0x3ff83fe0,0x3fc03f00,0x3c003800,0x20000000 # euc_jp encoding a3a2 .word 0x00000004,0x001c0064,0x01840604,0x18042004,0x18040604,0x010400c4,0x0034000c,0x00040000 # euc_jp encoding a3a3 .word 0x00000004,0x001c007c,0x01fc07fc,0x1ffc3ffc,0x1ffc07fc,0x03fc00fc,0x003c001c,0x00040000 # euc_jp encoding a3a4 .word 0x00000000,0x00040078,0x00180028,0x00480080,0x01000200,0x04000800,0x10002000,0x00000000 # euc_jp encoding a3a5 .word 0x00000000,0x20001000,0x08000400,0x02000100,0x00800048,0x00280018,0x00780004,0x00000000 # euc_jp encoding a3a6 .word 0x00000000,0x20001e00,0x18001400,0x12000100,0x00800040,0x00200010,0x00080004,0x00000000 # euc_jp encoding a3a7 .word 0x00000000,0x00040008,0x00100020,0x00400080,0x01001200,0x14001800,0x1e002000,0x00000000 # euc_jp encoding a3a8 .word 0x00000000,0x00080004,0xffff0004,0x00080000,0x10002000,0xffff2000,0x10000000,0x00000000 # euc_jp encoding a3a9 .word 0x00000000,0x00200030,0x00287fe4,0x40024001,0x40027fe4,0x00280030,0x00200000,0x00000000 # euc_jp encoding a3aa .word 0x00000000,0x04000c00,0x140027fe,0x40028002,0x400227fe,0x14000c00,0x04000000,0x00000000 # euc_jp encoding a3ab .word 0x01000280,0x04400820,0x10103c78,0x04400440,0x04400440,0x04400440,0x04400440,0x07c00000 # euc_jp encoding a3ac .word 0x000007c0,0x04400440,0x04400440,0x04400440,0x04400440,0x3c781010,0x08200440,0x02800100 # euc_jp encoding a3ad .word 0x00000008,0x0008001c,0x002a0008,0x00080008,0x00100010,0x002000c0,0x7f000000,0x00000000 # euc_jp encoding a3ae .word 0x00000000,0x7f0000c0,0x00200010,0x00100008,0x00080008,0x002a001c,0x00080008,0x00000000 # euc_jp encoding a3af .word 0x000003c0,0x04200810,0x08101818,0x10081008,0x10081008,0x18180810,0x08100420,0x03c00000 # euc_jp encoding a3b0 .word 0x00000100,0x03000500,0x09000100,0x01000100,0x01000100,0x01000100,0x01000100,0x07c00000 # euc_jp encoding a3b1 .word 0x000007e0,0x0c101808,0x10080008,0x00180030,0x006000c0,0x01800300,0x06000c00,0x1ff80000 # euc_jp encoding a3b2 .word 0x000003e0,0x0e101808,0x00080008,0x001007e0,0x00100008,0x00080008,0x00180070,0x1fc00000 # euc_jp encoding a3b3 .word 0x00000060,0x00e001a0,0x03200620,0x0c201820,0x30202020,0x3ffc0020,0x00200020,0x00f80000 # euc_jp encoding a3b4 .word 0x00001ff8,0x10001000,0x10001000,0x17e01810,0x10080008,0x00080018,0x003000e0,0x1f800000 # euc_jp encoding a3b5 .word 0x000000f0,0x03800600,0x0c000800,0x1bc01430,0x18181008,0x10081808,0x08180c30,0x03c00000 # euc_jp encoding a3b6 .word 0x00001ffc,0x10081018,0x10100030,0x00200060,0x004000c0,0x00800080,0x01800100,0x01000000 # euc_jp encoding a3b7 .word 0x000003c0,0x0c301818,0x10081008,0x081007e0,0x08101008,0x10081008,0x18180c30,0x03c00000 # euc_jp encoding a3b8 .word 0x000003c0,0x0c301810,0x10181008,0x10081818,0x0c2803d8,0x00100030,0x006001c0,0x0f000000 # euc_jp encoding a3b9 .word 0x000003c0,0x0c301008,0x20042184,0x43c247e2,0x47e243c2,0x21842004,0x10080c30,0x03c00000 # euc_jp encoding a3ba .word 0x000003c0,0x0c301188,0x27e42ff4,0x4ff25ffa,0x5ffa4ff2,0x2ff427e4,0x11880c30,0x03c00000 # euc_jp encoding a3bb .word 0x00001800,0x28c06520,0x06200020,0x00300010,0x00100018,0x0008000c,0x00040004,0x00000000 # euc_jp encoding a3bc .word 0x00000000,0x00000000,0x00000f00,0x02c00120,0x00900050,0x00300000,0x00000000,0x00000000 # euc_jp encoding a3bd .word 0x00000000,0x00000000,0x00000f00,0x03c001e0,0x00f00070,0x00300000,0x00000000,0x00000000 # euc_jp encoding a3be .word 0x00000000,0x00000000,0x01800240,0x04200420,0x02400180,0x00000000,0x00000000,0x00000000 # euc_jp encoding a3bf .word 0x00000000,0x00000000,0x018003c0,0x07e007e0,0x03c00180,0x00000000,0x00000000,0x00000000 # euc_jp encoding a3c0 .word 0x00000100,0x03800280,0x06c00440,0x0c600820,0x0fe01830,0x10103018,0x2008f83e,0x00000000 # euc_jp encoding a3c1 .word 0x00003fe0,0x08100808,0x08080808,0x08100fe0,0x08180804,0x08040804,0x08083ff0,0x00000000 # euc_jp encoding a3c2 .word 0x000003c8,0x0c281818,0x10083008,0x20002000,0x20003000,0x10081818,0x0c3003c0,0x00000000 # euc_jp encoding a3c3 .word 0x00003fc0,0x08300818,0x0808080c,0x08040804,0x0804080c,0x08080818,0x08303fc0,0x00000000 # euc_jp encoding a3c4 .word 0x00003ff8,0x08080804,0x08000840,0x08400fc0,0x08400840,0x08000804,0x08083ff8,0x00000000 # euc_jp encoding a3c5 .word 0x00001ffc,0x04040404,0x04000420,0x042007e0,0x04200420,0x04000400,0x04001f00,0x00000000 # euc_jp encoding a3c6 .word 0x000003c8,0x0c381808,0x10083000,0x20002000,0x203e3008,0x10081818,0x0c2803c8,0x00000000 # euc_jp encoding a3c7 .word 0x00007c3e,0x10081008,0x10081008,0x10081ff8,0x10081008,0x10081008,0x10087c3e,0x00000000 # euc_jp encoding a3c8 .word 0x000007c0,0x01000100,0x01000100,0x01000100,0x01000100,0x01000100,0x010007c0,0x00000000 # euc_jp encoding a3c9 .word 0x000000f8,0x00200020,0x00200020,0x00200020,0x00200020,0x00201020,0x18400f80,0x00000000 # euc_jp encoding a3ca .word 0x00003e7c,0x08300860,0x08c00980,0x0b000f00,0x098008c0,0x08600830,0x08183e3e,0x00000000 # euc_jp encoding a3cb .word 0x00001f00,0x04000400,0x04000400,0x04000400,0x04000400,0x04040404,0x04041ffc,0x00000000 # euc_jp encoding a3cc .word 0x0000f01e,0x30183838,0x28282828,0x2c682448,0x244826c8,0x22882388,0x2108f11e,0x00000000 # euc_jp encoding a3cd .word 0x0000783e,0x1c081408,0x16081308,0x11081188,0x10c81048,0x10681038,0x10187808,0x00000000 # euc_jp encoding a3ce .word 0x000003c0,0x0c301818,0x1008300c,0x20042004,0x2004300c,0x10081818,0x0c3003c0,0x00000000 # euc_jp encoding a3cf .word 0x00001ff0,0x04080404,0x04040404,0x040807f0,0x04000400,0x04000400,0x04001f00,0x00000000 # euc_jp encoding a3d0 .word 0x000003c0,0x0c301818,0x1008300c,0x20042004,0x2004300c,0x11881a58,0x0c3003d2,0x000c0000 # euc_jp encoding a3d1 .word 0x00003fe0,0x08100808,0x08080808,0x08100fe0,0x08200830,0x08100818,0x08083e3e,0x00000000 # euc_jp encoding a3d2 .word 0x000007c8,0x08281018,0x10081008,0x0c0003c0,0x00301008,0x10081808,0x141013e0,0x00000000 # euc_jp encoding a3d3 .word 0x00007ffc,0x41044104,0x01000100,0x01000100,0x01000100,0x01000100,0x010007c0,0x00000000 # euc_jp encoding a3d4 .word 0x00007c3e,0x10081008,0x10081008,0x10081008,0x10081008,0x10081818,0x0c3003c0,0x00000000 # euc_jp encoding a3d5 .word 0x00007c3e,0x10081818,0x08100830,0x0c200420,0x04600640,0x02c00280,0x03800100,0x00000000 # euc_jp encoding a3d6 .word 0x0000f99f,0x21842184,0x23c4324c,0x12481668,0x14281428,0x1c380c30,0x08100810,0x00000000 # euc_jp encoding a3d7 .word 0x00007c7c,0x10101830,0x0c6006c0,0x03800100,0x038006c0,0x0c601830,0x1010787c,0x00000000 # euc_jp encoding a3d8 .word 0x00007c7c,0x10101830,0x08200c60,0x044006c0,0x03800100,0x01000100,0x010007c0,0x00000000 # euc_jp encoding a3d9 .word 0x00001ff8,0x10301060,0x004000c0,0x01800100,0x03000600,0x04000c08,0x18083ff8,0x00000000 # euc_jp encoding a3da .word 0x00000000,0x3ffc0000,0x00000100,0x01000100,0x01003ffc,0x01000100,0x01000100,0x00000000 # euc_jp encoding a3db .word 0x00001020,0x10301810,0x0c180628,0x03200fc0,0x18c01060,0x10300818,0x18083008,0x00000000 # euc_jp encoding a3dc .word 0x00000e00,0x02c00300,0x06001c00,0x05e00630,0x04100410,0x0c300820,0x08240838,0x00000000 # euc_jp encoding a3dd .word 0x000079f8,0x20842082,0x20822082,0x20843ff8,0x20802080,0x20802080,0x208079e0,0x00000000 # euc_jp encoding a3de .word 0x000000c0,0x01200220,0x02200420,0x04200420,0x04400440,0x05880308,0x051018e0,0x00000000 # euc_jp encoding a3df .word 0x00003e7c,0x22442244,0x0c301818,0x10082004,0x20042004,0x10081818,0x0c3003c0,0x00000000 # euc_jp encoding a3e0 .word 0x00000000,0x00000000,0x00000000,0x07c00020,0x002007e0,0x08200820,0x08680798,0x00000000 # euc_jp encoding a3e1 .word 0x00001c00,0x04000400,0x04000400,0x05e00610,0x04080408,0x04080408,0x061005e0,0x00000000 # euc_jp encoding a3e2 .word 0x00000000,0x00000000,0x00000000,0x03e00410,0x08000800,0x08000800,0x041003e0,0x00000000 # euc_jp encoding a3e3 .word 0x000000e0,0x00200020,0x00200020,0x07a00860,0x10201020,0x10201020,0x086007b8,0x00000000 # euc_jp encoding a3e4 .word 0x00000000,0x00000000,0x00000000,0x03c00420,0x08100ff0,0x08000800,0x041003e0,0x00000000 # euc_jp encoding a3e5 .word 0x00000078,0x00880100,0x01000100,0x0fe00100,0x01000100,0x01000100,0x010007c0,0x00000000 # euc_jp encoding a3e6 .word 0x00000000,0x00000000,0x00000000,0x07d80820,0x08200820,0x07c00800,0x0ff01008,0x10080ff0 # euc_jp encoding a3e7 .word 0x00001c00,0x04000400,0x04000400,0x05e00630,0x04100410,0x04100410,0x04101e3c,0x00000000 # euc_jp encoding a3e8 .word 0x00000000,0x01800180,0x00000000,0x03800080,0x00800080,0x00800080,0x008003e0,0x00000000 # euc_jp encoding a3e9 .word 0x00000000,0x00c000c0,0x00000000,0x01c00040,0x00400040,0x00400040,0x00400040,0x10801f00 # euc_jp encoding a3ea .word 0x00003800,0x08000800,0x08000800,0x08f80860,0x09800e00,0x090008c0,0x08303e7c,0x00000000 # euc_jp encoding a3eb .word 0x00000700,0x01000100,0x01000100,0x01000100,0x01000100,0x01000100,0x010007c0,0x00000000 # euc_jp encoding a3ec .word 0x00000000,0x00000000,0x00000000,0x373818c4,0x10841084,0x10841084,0x108439ce,0x00000000 # euc_jp encoding a3ed .word 0x00000000,0x00000000,0x00000000,0x1de00630,0x04100410,0x04100410,0x04101e3c,0x00000000 # euc_jp encoding a3ee .word 0x00000000,0x00000000,0x00000000,0x03c00420,0x08100810,0x08100810,0x042003c0,0x00000000 # euc_jp encoding a3ef .word 0x00000000,0x00000000,0x00000000,0x1de00610,0x04080408,0x04080610,0x05e00400,0x04001f00 # euc_jp encoding a3f0 .word 0x00000000,0x00000000,0x00000000,0x07a00860,0x10201020,0x10200860,0x07a00020,0x002000f8 # euc_jp encoding a3f1 .word 0x00000000,0x00000000,0x00000000,0x0e700290,0x03000200,0x02000200,0x02000f80,0x00000000 # euc_jp encoding a3f2 .word 0x00000000,0x00000000,0x00000000,0x07d00830,0x08100780,0x00600810,0x0c100be0,0x00000000 # euc_jp encoding a3f3 .word 0x00000000,0x02000200,0x02000200,0x1fe00200,0x02000200,0x02000200,0x011000f0,0x00000000 # euc_jp encoding a3f4 .word 0x00000000,0x00000000,0x00000000,0x1c700410,0x04100410,0x04100410,0x063003dc,0x00000000 # euc_jp encoding a3f5 .word 0x00000000,0x00000000,0x00000000,0x3c780820,0x0c600440,0x06c00280,0x03800100,0x00000000 # euc_jp encoding a3f6 .word 0x00000000,0x00000000,0x00000000,0x799e1188,0x1bd80a50,0x0a500e70,0x04200420,0x00000000 # euc_jp encoding a3f7 .word 0x00000000,0x00000000,0x00000000,0x1e780420,0x02400180,0x02400420,0x08103e7c,0x00000000 # euc_jp encoding a3f8 .word 0x00000000,0x00000000,0x00000000,0x1e3c0410,0x06300220,0x03600140,0x00c00180,0x13001e00 # euc_jp encoding a3f9 .word 0x00000000,0x00000000,0x00000000,0x0ff00820,0x08400080,0x01000210,0x04100ff0,0x00000000 # euc_jp encoding a3fa .word 0x00000000,0x00000000,0x00000ff0,0x00000000,0x00000ff0,0x00000000,0x00000000,0x00000000 # euc_jp encoding a3fb .word 0x00000000,0x00000000,0x00000000,0x00000ff0,0x00000000,0x00000000,0x00000000,0x00000000 # euc_jp encoding a3fc .word 0x00000420,0x04200420,0x04200420,0x04207ffe,0x04200420,0x04200420,0x04200420,0x00000000 # euc_jp encoding a3fd .word 0x00000920,0x09200920,0x09200920,0x09207ffe,0x09200920,0x09200920,0x09200920,0x00000000 # euc_jp encoding a3fe .word 0x00000000,0x00000000,0x01000100,0x1ff80240,0x03f00658,0x0a4c1284,0x1284110c,0x0e180060 # euc_jp encoding a4a1 .word 0x02000200,0x3ff80400,0x044007f0,0x1c5c3444,0x24466482,0x44824506,0x4604381c,0x00700000 # euc_jp encoding a4a2 .word 0x00000000,0x00000000,0x00000000,0x10001030,0x10181008,0x100c1804,0x0a040e00,0x04000000 # euc_jp encoding a4a3 .word 0x00000000,0x20002010,0x2018200c,0x20042006,0x20022002,0x32021600,0x1c000800,0x00000000 # euc_jp encoding a4a4 .word 0x00000000,0x00000000,0x06000380,0x00e00000,0x0fe00010,0x00100010,0x00300060,0x01c00700 # euc_jp encoding a4a5 .word 0x06000380,0x00e00000,0x00001ff0,0x00180008,0x00080008,0x00180030,0x006001c0,0x0f000000 # euc_jp encoding a4a6 .word 0x00000000,0x00000000,0x06000380,0x00e00000,0x0fe00040,0x00800100,0x07800c80,0x18800078 # euc_jp encoding a4a7 .word 0x06000380,0x00e00000,0x1ff00020,0x00400080,0x010003c0,0x06400c40,0x18403060,0x003e0000 # euc_jp encoding a4a8 .word 0x00000000,0x00000000,0x02000210,0x03d81e08,0x020003e0,0x06100a08,0x12081218,0x0c700000 # euc_jp encoding a4a9 .word 0x04000400,0x040c07c6,0x7c020400,0x040005f8,0x070c1c06,0x34026402,0x44064c0c,0x38380000 # euc_jp encoding a4aa .word 0x04000400,0x0408040c,0x7f860442,0x04430c41,0x08410840,0x18401040,0x30c06080,0x03800000 # euc_jp encoding a4ab .word 0x04050405,0x04100418,0x7f8c0444,0x04460c42,0x08420840,0x18401040,0x30c06080,0x03800000 # euc_jp encoding a4ac .word 0x02000200,0x3ff80100,0x01003ffc,0x00800040,0x0ff01018,0x20002000,0x30001c00,0x07f00000 # euc_jp encoding a4ad .word 0x02050205,0x3ff00100,0x01003ff8,0x00800040,0x0ff01018,0x20002000,0x30001c00,0x07f00000 # euc_jp encoding a4ae .word 0x00100030,0x006000c0,0x01800300,0x0c001800,0x0c000600,0x03000180,0x00c00060,0x00300010 # euc_jp encoding a4af .word 0x00100035,0x006500c0,0x01800300,0x0c001800,0x0c000600,0x03000180,0x00c00060,0x00300010 # euc_jp encoding a4b0 .word 0x00102010,0x20106010,0x47ff4010,0x40104010,0x40104010,0x50106030,0x20200060,0x00c00000 # euc_jp encoding a4b1 .word 0x00252025,0x20206020,0x47fe4020,0x40204020,0x40204020,0x50206060,0x204000c0,0x01800000 # euc_jp encoding a4b2 .word 0x00000000,0x1ff80000,0x00000000,0x00000000,0x00000000,0x20003000,0x1c0007fc,0x00000000 # euc_jp encoding a4b3 .word 0x00050005,0x1ff00000,0x00000000,0x00000000,0x00000000,0x20003000,0x1c0007fc,0x00000000 # euc_jp encoding a4b4 .word 0x04000600,0x02007ffc,0x01000180,0x00c00060,0x0ff8100c,0x20002000,0x30001c00,0x07f00000 # euc_jp encoding a4b5 .word 0x04050605,0x02007ffc,0x01000180,0x00c00060,0x0ff8100c,0x20002000,0x30001c00,0x07f00000 # euc_jp encoding a4b6 .word 0x00000800,0x08000800,0x08000800,0x08000800,0x08000800,0x0804080c,0x08180470,0x03c00000 # euc_jp encoding a4b7 .word 0x00000800,0x08500850,0x08000800,0x08000800,0x08000800,0x0804080c,0x08180470,0x03c00000 # euc_jp encoding a4b8 .word 0x00800080,0x0080ffff,0x00800080,0x07800cc0,0x08400840,0x0c4007c0,0x00800180,0x03000e00 # euc_jp encoding a4b9 .word 0x00850085,0x0080ffff,0x00800080,0x07800cc0,0x08400840,0x0c4007c0,0x00800180,0x03000e00 # euc_jp encoding a4ba .word 0x00000810,0x08100810,0x0810ffff,0x08100810,0x08100810,0x08600800,0x08000400,0x03fc0000 # euc_jp encoding a4bb .word 0x00050825,0x08200820,0x0820ffff,0x08200820,0x08200820,0x08c00800,0x08000400,0x03fc0000 # euc_jp encoding a4bc .word 0x00001ff8,0x003000c0,0x01800300,0x0c007ffe,0x01800300,0x06000400,0x04000600,0x038000f0 # euc_jp encoding a4bd .word 0x00001ff0,0x006500c5,0x01800300,0x0c007ffe,0x01800300,0x06000400,0x04000600,0x038000f0 # euc_jp encoding a4be .word 0x04000400,0x04007f80,0x0800087c,0x08001800,0x10001000,0x30002000,0x208060c0,0x407e0000 # euc_jp encoding a4bf .word 0x040a040a,0x04007f80,0x0800087c,0x08001800,0x10001000,0x30002000,0x208060c0,0x407e0000 # euc_jp encoding a4c0 .word 0x01000100,0x01007ffc,0x02000600,0x04000ff0,0x18083004,0x00040004,0x000c0038,0x07e00000 # euc_jp encoding a4c1 .word 0x01050105,0x01007ffc,0x02000600,0x04000ff0,0x18083004,0x00040004,0x000c0038,0x07e00000 # euc_jp encoding a4c2 .word 0x00000000,0x00000000,0x00000000,0x000001e0,0x07101c08,0x00080008,0x00180030,0x00e00000 # euc_jp encoding a4c3 .word 0x00000000,0x000003f8,0x1e047002,0x00020002,0x00020006,0x000c0038,0x00e00000,0x00000000 # euc_jp encoding a4c4 .word 0x00050005,0x000003f8,0x1e047002,0x00020002,0x00020006,0x000c0038,0x00e00000,0x00000000 # euc_jp encoding a4c5 .word 0x00000000,0x7ffe0060,0x00c00180,0x01000300,0x02000200,0x02000300,0x018000e0,0x00380000 # euc_jp encoding a4c6 .word 0x00000000,0x7ffc0060,0x00c50185,0x01000300,0x02000200,0x02000300,0x018000e0,0x00380000 # euc_jp encoding a4c7 .word 0x00001000,0x18000800,0x0c0c0438,0x06e00380,0x06000c00,0x18001000,0x10001800,0x0ffc0000 # euc_jp encoding a4c8 .word 0x00051005,0x18000800,0x0c0c0438,0x06e00380,0x06000c00,0x18001000,0x10001800,0x0ffc0000 # euc_jp encoding a4c9 .word 0x08000800,0x08187f0c,0x08061800,0x10201020,0x30202020,0x602003e0,0x0438046c,0x03c00000 # euc_jp encoding a4ca .word 0x00001000,0x100031fc,0x20002000,0x20002000,0x20002000,0x22002200,0x2b0031fe,0x10000000 # euc_jp encoding a4cb .word 0x00800080,0x20802080,0x37f01c9c,0x10843986,0x29026d02,0x4702423a,0x47444d4e,0x383b0000 # euc_jp encoding a4cc .word 0x08000800,0x080008f8,0x798c0b06,0x0e020c02,0x08021802,0x383a6844,0x084e083b,0x08000000 # euc_jp encoding a4cd .word 0x00000000,0x03e00eb8,0x188c3084,0x21866102,0x43024202,0x46064c04,0x381c0070,0x00000000 # euc_jp encoding a4ce .word 0x00002020,0x20206020,0x47fe4020,0x40204020,0x40204020,0x43e04438,0x542c6466,0x23c00000 # euc_jp encoding a4cf .word 0x00052025,0x20206020,0x47fe4020,0x40204020,0x40204020,0x43e04438,0x542c6466,0x23c00000 # euc_jp encoding a4d0 .word 0x00002040,0x20466049,0x47f94046,0x40404040,0x40404040,0x43c04470,0x545864cc,0x23800000 # euc_jp encoding a4d1 .word 0x00000210,0x7e100418,0x0c1c1816,0x10133010,0x20102010,0x20102030,0x302018e0,0x0f800000 # euc_jp encoding a4d2 .word 0x00050215,0x7e100418,0x0c1c1816,0x10133010,0x20102010,0x20102030,0x302018e0,0x0f800000 # euc_jp encoding a4d3 .word 0x00000840,0xf8461049,0x30692076,0x20586040,0x40404040,0x40404040,0x60c03180,0x1f000000 # euc_jp encoding a4d4 .word 0x00000400,0x06000380,0x00c00000,0x06000300,0x018c4086,0x40c25843,0x704120c0,0x03800000 # euc_jp encoding a4d5 .word 0x0000040a,0x060a0380,0x00c00000,0x06000300,0x018c4086,0x40c25843,0x704120c0,0x03800000 # euc_jp encoding a4d6 .word 0x00000400,0x060c0392,0x00d2000c,0x06000300,0x018c4086,0x40c25843,0x704120c0,0x03800000 # euc_jp encoding a4d7 .word 0x00000000,0x00000600,0x09001980,0x108030c0,0x60600030,0x0018000c,0x00060000,0x00000000 # euc_jp encoding a4d8 .word 0x00000028,0x00280600,0x09001980,0x108030c0,0x60600030,0x0018000c,0x00060000,0x00000000 # euc_jp encoding a4d9 .word 0x00000000,0x00000618,0x092419a4,0x109830c0,0x60600030,0x0018000c,0x00060000,0x00000000 # euc_jp encoding a4da .word 0x00002000,0x27fe6020,0x40204020,0x47fe4020,0x40204020,0x43e04438,0x542c6466,0x23c00000 # euc_jp encoding a4db .word 0x00052005,0x27f86020,0x40204020,0x47fc4020,0x40204020,0x43e04438,0x542c6466,0x23c00000 # euc_jp encoding a4dc .word 0x00002000,0x27f66049,0x40494046,0x47f84040,0x40404040,0x43c04470,0x545864cc,0x23800000 # euc_jp encoding a4dd .word 0x00800080,0x00803ffc,0x00800080,0x3ffc0080,0x00800080,0x1f8020e0,0x20b8218c,0x1f000000 # euc_jp encoding a4de .word 0x00000000,0x1f000100,0x01080108,0x01081ff8,0x320e660b,0x44184c10,0x58303060,0x00c00000 # euc_jp encoding a4df .word 0x08000800,0x08007f18,0x080c0806,0x08023800,0x48004800,0x48004808,0x38080c18,0x07f00000 # euc_jp encoding a4e0 .word 0x00400040,0x20402040,0x37f01c9c,0x10843886,0x2d826502,0x47024206,0x4f04391c,0x00700000 # euc_jp encoding a4e1 .word 0x02000200,0x02003fe0,0x02000200,0x3fe00400,0x04000404,0x04040404,0x060c0318,0x01f00000 # euc_jp encoding a4e2 .word 0x00000000,0x00000000,0x00c00860,0x0c2004f8,0x07841e04,0x33040118,0x01000180,0x00800080 # euc_jp encoding a4e3 .word 0x000010c0,0x18600820,0x0cfc0782,0x3c02e606,0x021c0200,0x03000100,0x01000180,0x00800080 # euc_jp encoding a4e4 .word 0x00000000,0x00000000,0x00400840,0x09f01248,0x14441444,0x18440a48,0x09f00040,0x00c00180 # euc_jp encoding a4e5 .word 0x00000040,0x204023f8,0x664c4c46,0x48425042,0x50426046,0x264c23f8,0x004000c0,0x01800000 # euc_jp encoding a4e6 .word 0x00000000,0x00000000,0x01000100,0x010001f0,0x01000100,0x01000100,0x0f0011e0,0x11300e00 # euc_jp encoding a4e7 .word 0x00800080,0x00800080,0x00fc0080,0x00800080,0x00800080,0x1f8020e0,0x20b8218c,0x1f000000 # euc_jp encoding a4e8 .word 0x018000c0,0x08600800,0x18001000,0x100013f8,0x1e0c3004,0x00040004,0x000c0038,0x01e00000 # euc_jp encoding a4e9 .word 0x00000808,0x08080808,0x08080808,0x08080a08,0x0c080808,0x00180010,0x00300060,0x01c00000 # euc_jp encoding a4ea .word 0x00001ff0,0x006000c0,0x01800300,0x07f00c18,0x180c3004,0x07040984,0x088c0c98,0x07f00000 # euc_jp encoding a4eb .word 0x08000800,0x080008e0,0x79900b10,0x0e100c10,0x08101810,0x38106811,0x0813080e,0x08000000 # euc_jp encoding a4ec .word 0x00001ff0,0x006000c0,0x01800300,0x07f00c18,0x180c3004,0x0004000c,0x00180070,0x03c00000 # euc_jp encoding a4ed .word 0x00000000,0x00000000,0x04000400,0x04003c70,0x05880604,0x04040c04,0x1c043408,0x04300400 # euc_jp encoding a4ee .word 0x08000800,0x080008f8,0x798c0b06,0x0e020c02,0x08021802,0x38026806,0x080c0838,0x08000000 # euc_jp encoding a4ef .word 0x00000f80,0x00800080,0x008003f8,0x0d0c1906,0x33022602,0x64624cb2,0x589630cc,0x00780000 # euc_jp encoding a4f0 .word 0x00001ff0,0x00c00300,0x0ff03818,0x00080e08,0x13181930,0x0fe00800,0x3e7c63c6,0xc0830000 # euc_jp encoding a4f1 .word 0x02000200,0x03e03e00,0x04000406,0x0f9c1870,0x31c00340,0x06400c40,0x08000c00,0x07fc0000 # euc_jp encoding a4f2 .word 0x02000200,0x06000400,0x0c000800,0x08001b80,0x14401840,0x30402042,0x2046604c,0x40380000 # euc_jp encoding a4f3 .word 0x00000000,0x00000000,0x00000000,0x1ffc000c,0x01180130,0x01000100,0x03000200,0x06000c00 # euc_jp encoding a5a1 .word 0x00000000,0x7ffe0006,0x010c0118,0x01300100,0x01000100,0x03000200,0x06000c00,0x38000000 # euc_jp encoding a5a2 .word 0x00000000,0x00000000,0x00000008,0x00180030,0x00e00380,0x1e800080,0x00800080,0x00800080 # euc_jp encoding a5a3 .word 0x00000004,0x000c0018,0x003000e0,0x03800e80,0x78800080,0x00800080,0x00800080,0x00800000 # euc_jp encoding a5a4 .word 0x00000000,0x00000000,0x00000100,0x01001ff8,0x10081008,0x00180010,0x00300060,0x01c00700 # euc_jp encoding a5a5 .word 0x01000100,0x01003ffc,0x20042004,0x20042004,0x000c0008,0x00180030,0x006001c0,0x07000000 # euc_jp encoding a5a6 .word 0x00000000,0x00000000,0x00000000,0x00000ff0,0x01000100,0x01000100,0x01000100,0x1ff80000 # euc_jp encoding a5a7 .word 0x00000000,0x00003ffc,0x01000100,0x01000100,0x01000100,0x01000100,0x7ffe0000,0x00000000 # euc_jp encoding a5a8 .word 0x00000000,0x00000000,0x00000040,0x00400040,0x1ffc0140,0x03400640,0x0c403840,0x004001c0 # euc_jp encoding a5a9 .word 0x00400040,0x00400040,0x7ffe0140,0x03400240,0x06400c40,0x18403040,0x60400040,0x01c00000 # euc_jp encoding a5aa .word 0x01000100,0x01000100,0x3ffc0104,0x01040304,0x02040204,0x0604040c,0x0c081808,0x30780000 # euc_jp encoding a5ab .word 0x01050105,0x01000100,0x3ffc0104,0x01040304,0x02040204,0x0604040c,0x0c081808,0x30780000 # euc_jp encoding a5ac .word 0x04000400,0x06000238,0x03e00f00,0x7900011e,0x01f00780,0x3c8000c0,0x00400040,0x00600020 # euc_jp encoding a5ad .word 0x04050405,0x06000238,0x03e00f00,0x7900011e,0x01f00780,0x3c8000c0,0x00400040,0x00600020 # euc_jp encoding a5ae .word 0x01000100,0x010003f8,0x02080608,0x0c181810,0x00300020,0x006000c0,0x01800700,0x1c000000 # euc_jp encoding a5af .word 0x01050105,0x010003f8,0x02080608,0x0c181810,0x00300020,0x006000c0,0x01800700,0x1c000000 # euc_jp encoding a5b0 .word 0x04000400,0x0c000800,0x1ffe1020,0x30206020,0x00200060,0x004000c0,0x01800300,0x0e000000 # euc_jp encoding a5b1 .word 0x04050405,0x0c000800,0x1ffe1020,0x30206020,0x00200060,0x004000c0,0x01800300,0x0e000000 # euc_jp encoding a5b2 .word 0x00000000,0x00003ffc,0x00040004,0x00040004,0x00040004,0x00040004,0x00043ffc,0x00000000 # euc_jp encoding a5b3 .word 0x00050005,0x00003ffc,0x00040004,0x00040004,0x00040004,0x00040004,0x00043ffc,0x00000000 # euc_jp encoding a5b4 .word 0x00000810,0x08100810,0xffff0810,0x08100810,0x08100030,0x00200060,0x00c00180,0x07000000 # euc_jp encoding a5b5 .word 0x00050815,0x08100810,0xffff0810,0x08100810,0x08100030,0x00200060,0x00c00180,0x07000000 # euc_jp encoding a5b6 .word 0x00000000,0x0c000600,0x02000000,0x30021806,0x080c0018,0x00300060,0x01c00700,0x3c000000 # euc_jp encoding a5b7 .word 0x0000000a,0x0c0a0600,0x02000000,0x30021806,0x080c0018,0x00300060,0x01c00700,0x3c000000 # euc_jp encoding a5b8 .word 0x00000000,0x3ff00010,0x00100030,0x00200060,0x00c001c0,0x03600630,0x0c18180c,0x70060000 # euc_jp encoding a5b9 .word 0x00050005,0x3ff00010,0x00100030,0x00200060,0x00c001c0,0x03600630,0x0c18180c,0x70060000 # euc_jp encoding a5ba .word 0x00000800,0x08000800,0x08fc0f8c,0xf8180830,0x08000800,0x08000800,0x0c0007fc,0x00000000 # euc_jp encoding a5bb .word 0x00050805,0x08000800,0x08fc0f8c,0xf8180830,0x08000800,0x08000800,0x0c0007fc,0x00000000 # euc_jp encoding a5bc .word 0x00000000,0x20043004,0x10041804,0x080c0008,0x00180010,0x00300060,0x00c00380,0x0e000000 # euc_jp encoding a5bd .word 0x00050005,0x20003008,0x10081808,0x08180010,0x00300020,0x006000c0,0x01800700,0x1c000000 # euc_jp encoding a5be .word 0x01000100,0x010003fc,0x0204060c,0x0d8818d8,0x00500030,0x006000c0,0x01800700,0x1c000000 # euc_jp encoding a5bf .word 0x02050205,0x020007f8,0x04080c18,0x1b1031b0,0x00a00060,0x00c00180,0x03000e00,0x38000000 # euc_jp encoding a5c0 .word 0x00000018,0x00f01f80,0x00800080,0x00807ffe,0x00800080,0x01800100,0x03000600,0x1c000000 # euc_jp encoding a5c1 .word 0x00050035,0x00e01f80,0x00800080,0x00807ffe,0x00800080,0x01800100,0x03000600,0x1c000000 # euc_jp encoding a5c2 .word 0x00000000,0x00000000,0x00000000,0x02001308,0x19080818,0x00100030,0x006000c0,0x01800700 # euc_jp encoding a5c3 .word 0x00000000,0x04004602,0x62022306,0x3104100c,0x00080018,0x00300060,0x00c00380,0x0e000000 # euc_jp encoding a5c4 .word 0x00050005,0x04004604,0x62042304,0x310c1008,0x00180010,0x00300060,0x00c00380,0x0e000000 # euc_jp encoding a5c5 .word 0x00000000,0x3ffc0000,0x00000000,0x7ffe0080,0x00800080,0x01800100,0x03000600,0x1c000000 # euc_jp encoding a5c6 .word 0x00050005,0x3ff80000,0x00000000,0x7ffc0080,0x00800080,0x01800100,0x03000600,0x1c000000 # euc_jp encoding a5c7 .word 0x00000200,0x02000200,0x02000200,0x03c00270,0x021c0200,0x02000200,0x02000200,0x02000000 # euc_jp encoding a5c8 .word 0x0000020a,0x020a0200,0x02000200,0x03c00270,0x021c0200,0x02000200,0x02000200,0x02000000 # euc_jp encoding a5c9 .word 0x00000080,0x00800080,0x00807ffe,0x00800080,0x00800080,0x01800100,0x03000600,0x1c000000 # euc_jp encoding a5ca .word 0x00000000,0x00000000,0x1ff80000,0x00000000,0x00000000,0x00000000,0x7ffe0000,0x00000000 # euc_jp encoding a5cb .word 0x00000000,0x1ff80008,0x00180010,0x0c300760,0x01c000e0,0x01b00318,0x06080c00,0x38000000 # euc_jp encoding a5cc .word 0x01000100,0x01003ff8,0x00300060,0x00c00180,0x07301d1c,0x71060100,0x01000100,0x01000000 # euc_jp encoding a5cd .word 0x00000000,0x00080008,0x00180010,0x00300060,0x004000c0,0x01800300,0x06000c00,0x38000000 # euc_jp encoding a5ce .word 0x00000000,0x00000420,0x04300410,0x0c180808,0x080c0804,0x18041006,0x30026002,0x00000000 # euc_jp encoding a5cf .word 0x00050005,0x00000420,0x04300410,0x0c180808,0x080c0804,0x18041006,0x30026002,0x00000000 # euc_jp encoding a5d0 .word 0x00000000,0x00060849,0x08690826,0x18301010,0x10181008,0x3008200c,0x6004c004,0x00000000 # euc_jp encoding a5d1 .word 0x00001000,0x10001000,0x101810f0,0x1f801000,0x10001000,0x10001000,0x18000ffc,0x00000000 # euc_jp encoding a5d2 .word 0x00051005,0x10001000,0x101810f0,0x1f801000,0x10001000,0x10001000,0x18000ffc,0x00000000 # euc_jp encoding a5d3 .word 0x00002000,0x20062009,0x206923c6,0x3e002000,0x20002000,0x20002000,0x30001ff8,0x00000000 # euc_jp encoding a5d4 .word 0x00000000,0x3ffc0004,0x000c0008,0x00180010,0x00300060,0x00c00180,0x07001c00,0x00000000 # euc_jp encoding a5d5 .word 0x00050005,0x7ff80008,0x00180010,0x00300020,0x006000c0,0x01800300,0x0e003800,0x00000000 # euc_jp encoding a5d6 .word 0x00000000,0xffe60029,0x00290066,0x004000c0,0x00800180,0x03000600,0x1c007000,0x00000000 # euc_jp encoding a5d7 .word 0x00000000,0x00000400,0x0e000b00,0x198010c0,0x30606030,0x0018000c,0x00060000,0x00000000 # euc_jp encoding a5d8 .word 0x00000050,0x00500400,0x0e000b00,0x198010c0,0x30606030,0x0018000c,0x00060000,0x00000000 # euc_jp encoding a5d9 .word 0x00000000,0x00000430,0x0e480b48,0x19b010c0,0x30606030,0x0018000c,0x00060000,0x00000000 # euc_jp encoding a5da .word 0x00000100,0x01000100,0x7ffe0100,0x01000910,0x0918190c,0x11043106,0x61020100,0x07000000 # euc_jp encoding a5db .word 0x000a010a,0x01000100,0x7ffe0100,0x01000910,0x0918190c,0x11043106,0x61020100,0x07000000 # euc_jp encoding a5dc .word 0x00000100,0x01060109,0x7ff90106,0x01000920,0x09301918,0x1108310c,0x61040100,0x07000000 # euc_jp encoding a5dd .word 0x00000000,0x00007ffe,0x000c0018,0x00300c60,0x06c00380,0x018000c0,0x00600020,0x00000000 # euc_jp encoding a5de .word 0x00000700,0x01e00030,0x00000000,0x070001c0,0x00600000,0x00000e00,0x038000e0,0x00300000 # euc_jp encoding a5df .word 0x00000100,0x01000300,0x02000200,0x06000410,0x04100c18,0x080808fc,0x1f847006,0x00000000 # euc_jp encoding a5e0 .word 0x00000008,0x00080018,0x00100c30,0x076001c0,0x00e001b0,0x03180608,0x0c001800,0x70000000 # euc_jp encoding a5e1 .word 0x00000000,0x3ff80200,0x02000200,0x02007ffc,0x02000200,0x02000200,0x030001fc,0x00000000 # euc_jp encoding a5e2 .word 0x00000000,0x00000000,0x00000400,0x0600023c,0x03e40f0c,0x39080180,0x008000c0,0x00400040 # euc_jp encoding a5e3 .word 0x00000800,0x0c00041e,0x05f21f06,0xf20c0308,0x01000180,0x00800080,0x00c00040,0x00400000 # euc_jp encoding a5e4 .word 0x00000000,0x00000000,0x00000000,0x00000fc0,0x00400040,0x00400040,0x00400040,0x1ff80000 # euc_jp encoding a5e5 .word 0x00000000,0x00001fe0,0x00200020,0x00200020,0x00200020,0x00200020,0x7ffe0000,0x00000000 # euc_jp encoding a5e6 .word 0x00000000,0x00000000,0x00000000,0x0ff00010,0x00100010,0x0ff00010,0x00100010,0x0ff00000 # euc_jp encoding a5e7 .word 0x00000000,0x1ff80008,0x00080008,0x00081ff8,0x00080008,0x00080008,0x00081ff8,0x00000000 # euc_jp encoding a5e8 .word 0x00000000,0x1ff80000,0x00000000,0x3ffc0004,0x000c0008,0x00180030,0x006001c0,0x0f000000 # euc_jp encoding a5e9 .word 0x00000808,0x08080808,0x08080808,0x08080808,0x08080008,0x00180010,0x00300060,0x01c00000 # euc_jp encoding a5ea .word 0x00000040,0x08400840,0x08400840,0x08400841,0x08430846,0x184c1058,0x30706060,0x00000000 # euc_jp encoding a5eb .word 0x00000000,0x08000800,0x08000800,0x08000802,0x0806080c,0x08180870,0x09c00f00,0x00000000 # euc_jp encoding a5ec .word 0x00000000,0x00001ff8,0x10081008,0x10081008,0x10081008,0x10081008,0x1ff80000,0x00000000 # euc_jp encoding a5ed .word 0x00000000,0x00000000,0x00000000,0x1ff81008,0x10081008,0x00180010,0x00300060,0x01c00700 # euc_jp encoding a5ee .word 0x00000000,0x3ffc2004,0x20042004,0x0004000c,0x00080018,0x00300060,0x01c00700,0x00000000 # euc_jp encoding a5ef .word 0x00000040,0x00400040,0x3ffc0840,0x08400840,0x08400840,0x7ffe0040,0x00400040,0x00400000 # euc_jp encoding a5f0 .word 0x00000000,0x00003ffc,0x000c0018,0x01300100,0x01000100,0x01000100,0x7ffe0000,0x00000000 # euc_jp encoding a5f1 .word 0x00000000,0x1ffc0004,0x00040004,0x1ffc0008,0x00180030,0x006000c0,0x03800e00,0x00000000 # euc_jp encoding a5f2 .word 0x00000000,0x30001c00,0x06000002,0x0006000c,0x00180030,0x006001c0,0x07003c00,0x00000000 # euc_jp encoding a5f3 .word 0x01050105,0x01003ffc,0x20042004,0x20042004,0x000c0008,0x00180030,0x006001c0,0x07000000 # euc_jp encoding a5f4 .word 0x00000000,0x00000000,0x00000100,0x01000100,0x1ff80108,0x01080308,0x02080618,0x0c101870 # euc_jp encoding a5f5 .word 0x00000000,0x00000000,0x00000400,0x04000400,0x0ffc0820,0x18203060,0x004000c0,0x01800300 # euc_jp encoding a5f6 .word 0x00007ffe,0x04200420,0x04203ffc,0x24242424,0x24242424,0x3ffc0420,0x04200420,0xffff0000 # euc_jp encoding b0a1 .word 0x00000fff,0xf0909090,0x909097fe,0x94929492,0x949297fe,0x9090f090,0x00900090,0x0fff0000 # euc_jp encoding b0a2 .word 0x20102010,0x20fe2010,0xfc102410,0x25ff6400,0x44104c10,0xe8fe1810,0x14103410,0x6010c1ff # euc_jp encoding b0a3 .word 0x00007dff,0x44044c04,0x59e45124,0x49244524,0x45244524,0x45e44404,0x5c044004,0x4004401c # euc_jp encoding b0a4 .word 0x01000100,0xffff0000,0x1ff81008,0x10081008,0x1ff80642,0x0c66382c,0xe8300818,0x0f8c7807 # euc_jp encoding b0a5 .word 0x001c7ff0,0x22041108,0xffff8101,0x948d3416,0x67f20800,0x0ff83c30,0xe66003c0,0x1e78f00f # euc_jp encoding b0a6 .word 0x20802084,0x2184f93e,0x27e32100,0x210023fe,0x3620e020,0x27ff2050,0x20d8218c,0x23066603 # euc_jp encoding b0a7 .word 0x20102038,0x2028206c,0xfcc62583,0x2400647c,0x4c004800,0xe8fe1882,0x14823482,0x6082c0fe # euc_jp encoding b0a8 .word 0x008060fc,0x31041688,0x007001dc,0x0707f020,0x11fc1020,0x11fc1020,0x13fe3020,0x6800c7ff # euc_jp encoding b0a9 .word 0x04200420,0xffff0420,0x00007e44,0x04294812,0x3ffce107,0x01007ffe,0x02400660,0x1c38700e # euc_jp encoding b0aa .word 0x04200420,0xffff0420,0x0000ffff,0x04400440,0x7ffe4442,0x4c42787e,0x40024002,0x7ffe0000 # euc_jp encoding b0ab .word 0x088039f0,0xe22027fc,0x2244fbfc,0x224433fc,0x684067fe,0x6442a7fe,0x244227fe,0x2041203f # euc_jp encoding b0ac .word 0x00007ffe,0x04400440,0x3ffc2444,0x24443ffc,0x04400440,0xffff0080,0x24c6244b,0x6619c3f0 # euc_jp encoding b0ad .word 0x200023fe,0x22022202,0xfbfe2200,0x22fe2220,0x22443afe,0xe2122210,0x26fe2410,0x2c1061ff # euc_jp encoding b0ae .word 0x000063fe,0x32021202,0x03fec200,0x62fe2220,0x024412fe,0x12123210,0x26fe6410,0x4c10c1ff # euc_jp encoding b0af .word 0x200020fc,0x20842084,0xfc842484,0x24fc2484,0x24842484,0x248424fc,0x24006401,0x4603c3fe # euc_jp encoding b0b0 .word 0x0420ffff,0x04200200,0x3ff80408,0xffff0000,0x1ff81008,0x1ff80040,0x1ffc1040,0xffff0040 # euc_jp encoding b0b1 .word 0x04200420,0xffff0420,0x00007ffe,0x00001ffc,0x10041004,0x1ffc1000,0x30002000,0x6000c000 # euc_jp encoding b0b2 .word 0x20203c64,0x644648fa,0xfe1053ff,0x52287e44,0x53935220,0x7ec40018,0x55615506,0xd41880e0 # euc_jp encoding b0b3 .word 0x10201020,0x13fefc00,0x1104118c,0x388837ff,0x34205020,0x502093fe,0x10201020,0x10201020 # euc_jp encoding b0b4 .word 0x00003ffe,0x20002040,0x20402040,0x20402ffe,0x20402040,0x20406040,0x4040c040,0x1fff0000 # euc_jp encoding b0b5 .word 0x10101038,0xfe28106c,0x7cc64583,0x44647c34,0x440444c4,0x7c641007,0xfe3c10e4,0x10041004 # euc_jp encoding b0b6 .word 0x200027f8,0x21082118,0xf9102110,0x23bc2284,0x22c43a4c,0xe2682238,0x26102438,0x246c6dc7 # euc_jp encoding b0b7 .word 0x01000100,0x7ffe4002,0x50021000,0x1f7c3144,0x23447a44,0xce44044c,0x0c401841,0x3063e03e # euc_jp encoding b0b8 .word 0x200020fc,0x20842084,0xfc8424fc,0x24846484,0x4c844884,0xe8fc1884,0x14843484,0x6084c3ff # euc_jp encoding b0b9 .word 0x10101010,0x1010fe10,0x93ff9240,0x92409240,0xfe401040,0x10401240,0x12401f60,0xf13e0000 # euc_jp encoding b0ba .word 0x10203820,0x2c646646,0x50c2fc9f,0x45f17c00,0x44007cfe,0x40824482,0x44825e82,0x7282c0fe # euc_jp encoding b0bb .word 0x10403040,0x60ffc481,0x6d811879,0x30496449,0xfe791249,0x10495479,0x5601d203,0x9002100e # euc_jp encoding b0bc .word 0x10203020,0x61fec420,0x6fff1848,0x30c8658f,0xfe40127c,0x10c4558c,0x5658d230,0x90ec1387 # euc_jp encoding b0bd .word 0x20103e10,0x62104410,0xff1f4910,0x49107f10,0x4910497e,0x7f420042,0x55425542,0xd442807e # euc_jp encoding b0be .word 0x0048004c,0x0044ffff,0x00400040,0x7e424266,0x4224422c,0x7e380010,0x07393c6d,0xe1c70702 # euc_jp encoding b0bf .word 0x0000ffff,0x04407ffe,0x44424442,0x7ffe1108,0x19180910,0xffff0520,0x0d30391c,0xe1070100 # euc_jp encoding b0c0 .word 0x10101038,0x1028fc6c,0x04c60d83,0x1800127c,0x36007c00,0xd6fe1282,0x10821082,0x108210fe # euc_jp encoding b0c1 .word 0x01000100,0x7ffe4002,0x42020600,0x0400ffff,0x08081818,0x10303e60,0x03c00670,0x1c1c7006 # euc_jp encoding b0c2 .word 0x00800080,0x7fff4100,0x5ffe4220,0x44904ffc,0x788b4888,0x4ff84888,0xc8888ff9,0x8083007e # euc_jp encoding b0c3 .word 0x20402040,0x27fe2402,0xfc822080,0x20802fff,0x3904e30c,0x220827d8,0x207020d8,0x218c6706 # euc_jp encoding b0c4 .word 0x00200020,0xfbfe8904,0x898c8888,0x8ffff800,0x880089fc,0x89048904,0xf9fc0104,0x010401fc # euc_jp encoding b0c5 .word 0x01007ffe,0x40020200,0xffff0810,0x1e3003e0,0x0e38780c,0x0100ffff,0x05201d38,0xf10f0100 # euc_jp encoding b0c6 .word 0x00007e7e,0x42427e7e,0x42427e7e,0x41024ff2,0x44225ffa,0x400247e2,0x442247e2,0x442247ee # euc_jp encoding b0c7 .word 0x44104410,0xfefe4482,0x44a27c20,0x1020feff,0x92249264,0xfe4c10e8,0xfe38102c,0x106610c2 # euc_jp encoding b0c8 .word 0x01000100,0x0100ffff,0x05400d60,0x1930311c,0xe1070000,0x3ffc2004,0x20042004,0x20043ffc # euc_jp encoding b0c9 .word 0x00002004,0x20042004,0x26042304,0x21842084,0x200c2008,0x2008201c,0x2e363862,0xe0c30381 # euc_jp encoding b0ca .word 0x08000bfe,0x18221022,0x302227ff,0x6022a022,0x202223fe,0x20202020,0x20602040,0x20c02180 # euc_jp encoding b0cb .word 0x08200820,0x182013fe,0x30002000,0x6104a104,0x218c2088,0x20882098,0x20102010,0x27ff2000 # euc_jp encoding b0cc .word 0x08200820,0x182017ff,0x30402040,0x60e2a1a6,0x232c2738,0x2d102118,0x2108216c,0x21c62703 # euc_jp encoding b0cd .word 0x08400bfc,0x18841084,0x37ff2000,0x63fca204,0x23fc2010,0x27fe2110,0x21102fff,0x20102010 # euc_jp encoding b0ce .word 0x00007ffe,0x40024422,0x44225ffa,0x44224422,0x44225ffa,0x44224c22,0x58224002,0x7ffe0000 # euc_jp encoding b0cf .word 0x01000100,0xffff0100,0x7ffc0104,0x3ffc2100,0x21003ffe,0x028206c2,0x044e0c60,0x3838e00f # euc_jp encoding b0d0 .word 0x00383fe0,0x0100ffff,0x05200d30,0x391ce107,0x01000200,0xffff0420,0x08601fc0,0x03787c0e # euc_jp encoding b0d1 .word 0x0048004c,0x00447fff,0x40405f40,0x40444464,0x5fac4928,0x49385e10,0x4339c56d,0x98c78182 # euc_jp encoding b0d2 .word 0x00047f04,0x41044104,0x7f04407f,0x40045f04,0x40245f34,0x44145504,0xd5049504,0xa5040c1c # euc_jp encoding b0d3 .word 0x10801088,0x11981910,0x55ff5310,0xd51091fe,0x11101110,0x111011fe,0x11101110,0x111011ff # euc_jp encoding b0d4 .word 0x01000100,0x7ffe0810,0x0420ffff,0x00001ff8,0x10081ff8,0x10081ff8,0x01002486,0x6413c3f1 # euc_jp encoding b0d5 .word 0x00047f04,0x41047f04,0x407f5f04,0x40245f14,0x4414d504,0x95042c1c,0x01002486,0x6413c3f1 # euc_jp encoding b0d6 .word 0x00001ff8,0x10081008,0x1ff81008,0x10081ff8,0x08001ffe,0x3222e662,0x0c4238c6,0x0384001c # euc_jp encoding b0d7 .word 0x10201020,0x13fefc50,0x10d8118c,0x380037ff,0x340451e4,0x51249124,0x11e41004,0x1004101c # euc_jp encoding b0d8 .word 0x22003200,0x12007ff8,0x04080410,0x0ffe0802,0x18043fff,0x6001c011,0x1489124b,0x2242000e # euc_jp encoding b0d9 .word 0x00003ffc,0x21042104,0x3ffc2104,0x21043ffc,0x0000ffff,0x108410cc,0x10681730,0x1c1c7007 # euc_jp encoding b0da .word 0x00003ffc,0x21042104,0x3ffc2104,0x21043ffc,0x04207ffe,0x04200420,0xffff0810,0x381ce007 # euc_jp encoding b0db .word 0x06201c3e,0xf06210c6,0x11acfe18,0x103010e8,0x380f3419,0x523350ea,0x9006100c,0x103811e0 # euc_jp encoding b0dc .word 0x10403044,0x60ccc488,0x6dff1a88,0x308864fe,0xfe881288,0x108854fe,0x5688d288,0x908810ff # euc_jp encoding b0dd .word 0x102030fc,0x6044c444,0x6dff1800,0x30fe6482,0xfefe1208,0x10fe5448,0x5448d5ff,0x90081008 # euc_jp encoding b0de .word 0x7ffe4102,0x41027ffe,0x41024102,0x7ffe0000,0x3ffc2004,0x3ffc2004,0x3ffc2004,0x2004201c # euc_jp encoding b0df .word 0x0420ffff,0x04200078,0x3fc00100,0xffff0540,0x3938e10f,0x0400ffff,0x08103f20,0x01f87e0e # euc_jp encoding b0e0 .word 0x01000100,0x0100ffff,0x02800682,0x0cc6184c,0x3878e820,0x08300810,0x08180b8c,0x1e067003 # euc_jp encoding b0e1 .word 0x00007cfe,0x0092fefe,0x00927c92,0x00fe0000,0x7cfe0082,0x00fe7c82,0x44fe4482,0x44827c86 # euc_jp encoding b0e2 .word 0x004063fc,0x30841084,0x07ff0000,0x01fcf104,0x11fc1010,0x13fe1110,0x17ff3010,0x6810c7ff # euc_jp encoding b0e3 .word 0x002061fc,0x312411fc,0x002007ff,0x0000f1fc,0x110411fc,0x110411fc,0x110431fc,0x6a02c7ff # euc_jp encoding b0e4 .word 0x00007ffe,0x44004400,0x4ff85880,0x40805ffc,0x41404360,0x42204630,0x4c184000,0x7ffe0000 # euc_jp encoding b0e5 .word 0x04200420,0x04200420,0x7ffe0420,0x04200420,0x0420ffff,0x04200420,0x0c200820,0x18203020 # euc_jp encoding b0e6 .word 0x01000100,0x0100ffff,0x01000320,0x366018c8,0x0d980330,0x06601cc0,0x71b00718,0x1c0c7006 # euc_jp encoding b0e7 .word 0x20282024,0x202427ff,0xf8202020,0x27a224b2,0x24962494,0x279c3808,0x6399ce2d,0x00c70302 # euc_jp encoding b0e8 .word 0x01000100,0xffff0400,0x08081ffc,0x70060000,0x1ff81008,0x1ff81008,0x1ff81008,0x10081038 # euc_jp encoding b0e9 .word 0x0800083e,0xffa21026,0x10243f2c,0x21286124,0xbf222122,0x21223f22,0x2122212e,0x21202720 # euc_jp encoding b0ea .word 0x0122fa24,0x26ad2122,0x222522af,0x77a45022,0xd3ff5220,0x53125294,0x72880615,0x04270cc2 # euc_jp encoding b0eb .word 0x00000000,0x00000000,0x00000000,0x00007ffe,0x00000000,0x00000000,0x00000000,0x00000000 # euc_jp encoding b0ec .word 0x01000100,0xffff0100,0x01003ffc,0x0000ffff,0x80019031,0x11e01f00,0x10021006,0x18040ffc # euc_jp encoding b0ed .word 0x0204630c,0x310817fe,0x0108c30c,0x62042606,0x0c030000,0x17fe3492,0x24926492,0x4492cfff # euc_jp encoding b0ee .word 0x008060fc,0x31881310,0x07fe0222,0x0222f222,0x13fe1090,0x11901111,0x1311360f,0x6800c7ff # euc_jp encoding b0ef .word 0x06061c3c,0xf1e01000,0x1122fdb6,0x10941000,0x393e3522,0x5122513e,0x91221122,0x1122113e # euc_jp encoding b0f0 .word 0x04200420,0xffff0420,0x05206100,0x31fe1322,0x02260674,0x105030d8,0x2088618c,0xc3060603 # euc_jp encoding b0f1 .word 0x04200420,0xffff0420,0x04200000,0x3ffc0100,0x0100ffff,0x01000100,0x01000100,0x01000700 # euc_jp encoding b0f2 .word 0x21ef3c21,0x642149ef,0xfd085508,0x55ef7c21,0x552954a5,0x7c210163,0x55a55529,0xd46380c6 # euc_jp encoding b0f3 .word 0x04000400,0x0c100818,0x180c11fe,0x7f220420,0x04200420,0x04200c20,0x08211821,0x3033e01e # euc_jp encoding b0f4 .word 0x03000e00,0x78fe4082,0x40824082,0x40827e82,0x40824082,0x40824082,0x40827e9e,0x00800080 # euc_jp encoding b0f5 .word 0x000003fe,0xf2029222,0x922292fa,0x92229222,0x92729252,0xf252028a,0x02020202,0x03fe0000 # euc_jp encoding b0f6 .word 0x00001ff8,0x10081008,0x1ff80000,0x3ffc2004,0x3ffc2004,0x3ffc2004,0x3ffc0000,0x1818700e # euc_jp encoding b0f7 .word 0x00007ffe,0x40024102,0x41025ffa,0x41024382,0x42c24662,0x4c32581a,0x40024002,0x7ffe0000 # euc_jp encoding b0f8 .word 0x200023fe,0x22022222,0xfa222afa,0x2a226a22,0x4a725a52,0x5252d28a,0x3a022a02,0x63fec000 # euc_jp encoding b0f9 .word 0x0004ff04,0x01040104,0x01047f04,0x40044004,0x40047f04,0x01040104,0x03040204,0x06043c04 # euc_jp encoding b0fa .word 0x10403840,0x2c40667f,0x5041fcd3,0x44927c10,0x44107c38,0x40284428,0x446c5e44,0x72c6c183 # euc_jp encoding b0fb .word 0x600e33f8,0x10020246,0xc3646120,0x201c01f0,0x00201020,0x17ff3020,0x20206020,0x43fec000 # euc_jp encoding b0fc .word 0x21042204,0x2c442684,0x21042224,0x2ff42014,0x27e42424,0x27e42424,0x27e46425,0x4425c463 # euc_jp encoding b0fd .word 0x0420ffff,0x04200000,0x78304848,0x48b45303,0x50fc4808,0x49fe4800,0x5bff4084,0x413e43e3 # euc_jp encoding b0fe .word 0x00207820,0x4bfe4a02,0x4a0251fc,0x50004800,0x4fff4890,0x48904890,0x59904111,0x4313460e # euc_jp encoding b1a1 .word 0x00207870,0x48d8498c,0x4b765603,0x51fc4808,0x481049fc,0x48004fff,0x58804084,0x413e43e3 # euc_jp encoding b1a2 .word 0x0006783c,0x4be24926,0x489451fe,0x500249fe,0x480249fe,0x48204810,0x59524143,0x4345423c # euc_jp encoding b1a3 .word 0x100010fe,0xfe824482,0x6cfe2800,0xfefe0082,0x7cfe4482,0x44fe7c82,0x44fe4444,0x7cc60183 # euc_jp encoding b1a4 .word 0x00087c08,0x44084408,0x47ff4408,0x44084588,0x44c84448,0x44087c08,0x00080008,0x00080038 # euc_jp encoding b1a5 .word 0x02000200,0x0200ffff,0x04000400,0x0c000800,0x1ffc3804,0x6804c804,0x08040804,0x0ffc0000 # euc_jp encoding b1a6 .word 0x01000100,0x7ffe4002,0x40025ffa,0x01000100,0x0100ffff,0x01000100,0x01000100,0x01000700 # euc_jp encoding b1a7 .word 0x00800100,0x1ff81008,0x10081008,0x1ff81000,0x1fff1000,0x1ffe0022,0x29326d96,0x4484001c # euc_jp encoding b1a8 .word 0x0000fefe,0x02020202,0x62623232,0x12120202,0x0e0e1a1a,0x32326262,0xc2c20202,0x02020e0e # euc_jp encoding b1a9 .word 0x000063fe,0x30201020,0x00200020,0x07fff020,0x10201020,0x10201020,0x102030e0,0x6800c7ff # euc_jp encoding b1aa .word 0x0000ffff,0x01000100,0x7ffe4102,0x59624d32,0x45124102,0x59624d32,0x45124102,0x4102400e # euc_jp encoding b1ab .word 0x03000e00,0x787e4242,0x42424242,0x42424242,0x42424242,0x42427e42,0xc44e0c40,0x18407040 # euc_jp encoding b1ac .word 0x44106c20,0x28fefe82,0x12fe7e82,0x50fe5080,0x7eff1280,0x12ff3601,0x51559155,0x1203100e # euc_jp encoding b1ad .word 0x01000100,0x7ffe4442,0x587a0000,0x10fc7c84,0x10fc1084,0xfefc1084,0x38fc2c49,0x60c9c387 # euc_jp encoding b1ae .word 0x00007ff0,0x04100410,0x04100410,0x0410ffff,0x08100810,0x08100810,0x08100810,0xffff0000 # euc_jp encoding b1af .word 0x0024006c,0xfe4810ff,0x11883288,0x20883cfe,0x6488a488,0x248824fe,0x24882488,0x3c8800ff # euc_jp encoding b1b0 .word 0x03000e00,0x387c2004,0x20042004,0x20042004,0x3e7c2004,0x20042004,0x20042004,0x3ffc0000 # euc_jp encoding b1b1 .word 0x000063fc,0x32041204,0x027cc244,0x624427fe,0x040214f2,0x14923492,0x249264f2,0x4402c40e # euc_jp encoding b1b2 .word 0x0040007e,0xf04097ff,0x9441947a,0x95c09442,0x943e9400,0xf4480d49,0x094a194a,0x304803ff # euc_jp encoding b1b3 .word 0x000001fe,0xf9028902,0x89fe8902,0x89028902,0x89fe8902,0x8902f902,0x01fe0084,0x01860303 # euc_jp encoding b1b4 .word 0x2244f99f,0x2244718e,0xaa553ffc,0x24443ffc,0x00007e04,0x42ff7e04,0x42447e24,0x4404fa1c # euc_jp encoding b1b5 .word 0x04200420,0xffff0420,0x00047f04,0x41047f7f,0x40045f24,0x40145f14,0x4404d504,0xa4840c1c # euc_jp encoding b1b6 .word 0x207c3c44,0x647c4844,0xfe7c5200,0x52fe7eaa,0x52fe5200,0x7efc0044,0x556c5538,0xd46c81c7 # euc_jp encoding b1b7 .word 0x10221022,0x11fe1024,0xfc2c2428,0x27ff2430,0x64604dc6,0x4b5ce870,0x18403441,0x6463c03e # euc_jp encoding b1b8 .word 0x00007fff,0x40005f3e,0x51285128,0x5f285128,0x517f5f08,0x50185210,0xd2389f29,0xb16900c7 # euc_jp encoding b1b9 .word 0x00246022,0x37ff1020,0x0020c3fe,0x62222222,0x03fe1222,0x122233fe,0x22226222,0x4222c226 # euc_jp encoding b1ba .word 0x000c0078,0x3fc82008,0x21082108,0x21082108,0x2108210c,0x21042124,0x212461f6,0x4f12c003 # euc_jp encoding b1bb .word 0x00007e7e,0x42427e7e,0x42427e7e,0x40024ff2,0x41024102,0x47e24102,0x41025ffa,0x4002400e # euc_jp encoding b1bc .word 0x01040088,0x07fff050,0x93fe9252,0x939e9202,0x93fe9202,0x93fef004,0x07ff0104,0x0084001c # euc_jp encoding b1bd .word 0x00000000,0x3ffc0000,0x00000000,0xffff0400,0x04000410,0x0c180808,0x08fc1f84,0x70060000 # euc_jp encoding b1be .word 0x000067ff,0x34011421,0x03fe0020,0x03fef222,0x13fe1222,0x13fe1020,0x17ff3020,0x6800c7ff # euc_jp encoding b1bf .word 0x00003ffc,0x01007ffe,0x41025d3a,0x41021d38,0x00003ffc,0x0000ffff,0x08081808,0x10fc3f86 # euc_jp encoding b1c0 .word 0x04200420,0xffff0420,0x0420080c,0x183813e0,0x30207020,0xd7ff1020,0x10201020,0x13fe1000 # euc_jp encoding b1c1 .word 0x08001dff,0x16443344,0x6844be7c,0x22443e44,0x22443e7c,0x20442244,0x22472ffc,0x39046004 # euc_jp encoding b1c2 .word 0x08000f7e,0x0822ffa2,0x80a21c36,0x41149c94,0x221c7f08,0xc1887f1c,0x41147f36,0x41227f63 # euc_jp encoding b1c3 .word 0x2204330c,0x1108ffff,0x80019ff9,0x10081008,0x1ff80100,0x02003ffc,0x20042004,0x20043ffc # euc_jp encoding b1c4 .word 0x7e7e4242,0x7e7e4242,0x7e7e4242,0x7e7e2424,0x42420200,0xffff0410,0x08601fc0,0x01f87e0e # euc_jp encoding b1c5 .word 0x00027f06,0x410c7f18,0x41307f02,0x0806ff8c,0x00187f30,0x41017f03,0x0806490c,0x88981830 # euc_jp encoding b1c6 .word 0x00200020,0xf8208bfe,0x8a228a22,0x8a22fa22,0x8a228fff,0x885088d8,0xf888018c,0x03060603 # euc_jp encoding b1c7 .word 0x01000100,0x7ffe4102,0x41027ffe,0x41024102,0x41027ffe,0x01080198,0x00b101e1,0x0f39f80f # euc_jp encoding b1c8 .word 0x0604630c,0x31181010,0x7ffe4002,0x41020100,0xffff0540,0x0d600930,0x1918310c,0xe1070100 # euc_jp encoding b1c9 .word 0x070001c0,0x00400000,0x1f800086,0x008c7cd8,0x04f00ca0,0x08b01898,0x308c6086,0xc0830780 # euc_jp encoding b1ca .word 0x038060e0,0x30201000,0x07c0c042,0x60662f6c,0x01780150,0x23582248,0x664c4c46,0xd84381c0 # euc_jp encoding b1cb .word 0x00406040,0x37fe1442,0x0442c7fe,0x64422442,0x07fe1040,0x1064302c,0x20386071,0x41ddcf07 # euc_jp encoding b1cc .word 0x0088f888,0x27ff2088,0x20882020,0xfbfe2222,0x22222222,0x27ff2050,0x38d8e18c,0x03060603 # euc_jp encoding b1cd .word 0x0000fff0,0x10101010,0x1fde1042,0x34822302,0x6ccec000,0x3ffc2444,0x24442444,0xffff0000 # euc_jp encoding b1ce .word 0x400046ff,0x7c10407e,0x41423f42,0x007e0e42,0x7842087e,0xff422842,0x2e7e6b24,0xc86608c3 # euc_jp encoding b1cf .word 0x400046ff,0x7c10407e,0x41423f42,0x007e7f42,0x0042fffe,0x08422a42,0x6b7e4924,0xc86618c3 # euc_jp encoding b1d0 .word 0x08100810,0xffff0810,0x09100100,0x3ffc2104,0x21042104,0xffff0240,0x06600c30,0x381ce007 # euc_jp encoding b1d1 .word 0x110037ef,0x6220c220,0x0ff01000,0x37ef6422,0xe7e22042,0x2ff22242,0x22423ffa,0x20422046 # euc_jp encoding b1d2 .word 0x00c07870,0x0010fc00,0x01e07820,0x002203b6,0x78bc00a8,0x00a879ac,0x49244b26,0x4e2378e0 # euc_jp encoding b1d3 .word 0x108238c6,0x2c4466fe,0x4282fc82,0x10821082,0xfefe1048,0x9448d448,0x50c81e89,0xf1890307 # euc_jp encoding b1d4 .word 0x00206020,0x37ff1090,0x0090c19e,0x61122332,0x052a1166,0x1114311c,0x2108611c,0x4136c163 # euc_jp encoding b1d5 .word 0x00800080,0x3fffa000,0x63f02210,0x26102c1f,0x20006ffc,0xa20c2318,0x61b040e0,0xc3b81e0f # euc_jp encoding b1d6 .word 0x10081818,0x0c300420,0xffff0420,0x0c301818,0x300ce007,0x1ff81248,0x12481248,0x1248ffff # euc_jp encoding b1d7 .word 0x00007fbe,0x48224822,0x7f224822,0x48227f3e,0x48284828,0x7fac00a4,0xaaa4aaa6,0x81a20343 # euc_jp encoding b1d8 .word 0x11021186,0x108411fe,0x59025502,0x5502d102,0x91fe1048,0x10481048,0x10c81089,0x11891307 # euc_jp encoding b1d9 .word 0x000079fe,0x0102fdfe,0x010279fe,0x008000ff,0x79810319,0x01f17901,0x490948fb,0x4802780e # euc_jp encoding b1da .word 0x10141012,0x7c1011ff,0x1110ff12,0x11121116,0x51145d1c,0x51c8531d,0x50377062,0xdc0087ff # euc_jp encoding b1db .word 0x00007e7e,0x42427e7e,0x42427e7e,0x44224242,0x4ff24812,0x48124ff2,0x4242464a,0x5c3a4006 # euc_jp encoding b1dc .word 0x100013ff,0x1020fdfe,0x110211fe,0x390235fe,0x350251fe,0x504090fe,0x138610cc,0x107813cf # euc_jp encoding b1dd .word 0x00007fff,0x40005f0a,0x51095f08,0x517f5f08,0x40085f1c,0x51145f14,0xd1149f36,0x91221363 # euc_jp encoding b1de .word 0x00007ffe,0x41024102,0x41024102,0x41024102,0x7ffe4002,0x40024002,0x40024002,0x400e0000 # euc_jp encoding b1df .word 0x00007ffe,0x41024ff2,0x41025ffa,0x40024ff2,0x48124ff2,0x434a4532,0x591a4102,0x7ffe0000 # euc_jp encoding b1e0 .word 0x200027ff,0x240024fc,0x2484fcfc,0x248424fc,0x242025fe,0x24483cd8,0xe43005ce,0x040007ff # euc_jp encoding b1e1 .word 0x02000200,0xffff0420,0x09101108,0x3ffce107,0x21043ffc,0x21042104,0x3ffc0101,0x018300fe # euc_jp encoding b1e2 .word 0x01000100,0x7ffe4002,0x4ff20810,0x0ff00810,0x0ff00200,0xffff0410,0x08301fe0,0x03383c0c # euc_jp encoding b1e3 .word 0x0006fc1c,0x09f01010,0x20107890,0x089e0890,0x48906890,0x28903890,0x13ff3800,0x6e00c3ff # euc_jp encoding b1e4 .word 0x10001f7e,0x31422342,0x724ed640,0x0c411863,0x303ee000,0x018024c4,0x2446640b,0x4619c3f0 # euc_jp encoding b1e5 .word 0x20802080,0x2fff2108,0xf9482244,0x27fe2a45,0x22443bfc,0xe2442244,0x23fc2041,0x2063603e # euc_jp encoding b1e6 .word 0x200e27f8,0x2242fb66,0x212423fe,0x208027ff,0x3880e0fc,0x2184230c,0x26d82070,0x21dc6707 # euc_jp encoding b1e7 .word 0x61083108,0x1108030c,0x0204c606,0x6c032000,0x03fc1204,0x12043204,0x22046204,0x4204c3fc # euc_jp encoding b1e8 .word 0x00206020,0x37ff1401,0x05fdc020,0x63fe2222,0x022213fe,0x12223222,0x23fe6104,0x4306c603 # euc_jp encoding b1e9 .word 0x01001104,0x110c3398,0x22c00660,0x1c38710e,0x0104110c,0x339862c0,0x06600c30,0x381ce007 # euc_jp encoding b1ea .word 0x10201020,0x107e1242,0x56c6558c,0x5008d13f,0x91211121,0x3921293f,0x2d216521,0x4121c13f # euc_jp encoding b1eb .word 0x100013ff,0x10501450,0x55fe5552,0x5152d152,0x91fe1020,0x382029fe,0x2c206420,0x43ffc000 # euc_jp encoding b1ec .word 0x04200420,0xffff0420,0x07e01009,0xf3ca124c,0x12481249,0x73c9d00f,0x00002444,0x6666c223 # euc_jp encoding b1ed .word 0x08208820,0x53fe2020,0x27ff5000,0x93fe1202,0x320253fe,0x9091119b,0x170a110c,0x31e6e703 # euc_jp encoding b1ee .word 0x100031fc,0x6004c5fc,0x6c041bff,0x304064a2,0xfd341458,0x10905538,0x5454d492,0x91111060 # euc_jp encoding b1ef .word 0x14207f3e,0x55227f66,0x55c47f7f,0x0049ffc9,0x00497f7f,0x41407f40,0x22403641,0x1441ffbf # euc_jp encoding b1f0 .word 0x04200420,0xffff0420,0x04201000,0x1f7e3142,0x23427a42,0xce42044e,0x0c401841,0x3063e03e # euc_jp encoding b1f1 .word 0x0420ffff,0x04207ffe,0x41024ff2,0x41025ffa,0x40024ff2,0x48124ff2,0x431a5de2,0x411a7ffe # euc_jp encoding b1f2 .word 0x00206020,0x33fe1020,0x07ff0000,0x03fef202,0x13fe1063,0x10e611b8,0x172e3023,0x6820c7ff # euc_jp encoding b1f3 .word 0x10243824,0x2c246666,0x4242fcc3,0x10811000,0xfe7e1042,0x9442d442,0x50421e42,0x7042c07e # euc_jp encoding b1f4 .word 0x107c3f44,0xe241147f,0x1900fff8,0x10081ff8,0x10081ff8,0x10001fff,0x10005ffe,0xc9228496 # euc_jp encoding b1f5 .word 0x02002200,0x27fe2c00,0x23fcfa04,0x220423fc,0x200027fe,0x24923c92,0xe4920492,0x04920fff # euc_jp encoding b1f6 .word 0x10101010,0x1038ff28,0x106c1044,0x1ec613b3,0x1218120c,0x32042260,0x26306418,0x440ccc04 # euc_jp encoding b1f7 .word 0x600037fe,0x10800080,0x0080cfff,0x61002100,0x010013fe,0x10023002,0x20026006,0x4004c03c # euc_jp encoding b1f8 .word 0x100011fe,0x51225122,0x7dfed122,0x912211fe,0x7c2013ff,0x10211061,0x1c4170c3,0xc182070e # euc_jp encoding b1f9 .word 0x00007c3e,0x44224422,0x44224422,0x44224422,0x47e24002,0x40024002,0x40024002,0x7ffe0000 # euc_jp encoding b1fa .word 0x01000100,0x01003ffc,0x21042104,0x21042104,0x2104ffff,0x028006c0,0x04600c30,0x381ce007 # euc_jp encoding b1fb .word 0x01000200,0x3ffc2004,0x29242544,0x2ff42384,0x25442934,0x21042204,0xffff0660,0x1c38700e # euc_jp encoding b1fc .word 0x08c01860,0x302063fe,0xc8201820,0x30206020,0xe3fe2020,0x20202020,0x20202020,0x27ff2000 # euc_jp encoding b1fd .word 0x00800080,0x3fff2000,0x20c02060,0x21302110,0x25002504,0x25062d03,0x69014904,0xc18c00f8 # euc_jp encoding b1fe .end
source_codes/s/asmsim_examples.s/key_event.s
/* * key_event.s * Adds and removes key listener: * key_event_ena(): adds key listener * key_event_dis(): removes key listener * If the key listener was added, pressing a key will cause * a transfer of control to __Key_Event (exception handler). * * When you write codes for __Key_Event, please save all * the registers which you will use to the stack and restore * them before the return from the exception (eret). * * Try to develop your codes for Othello and Tetris games! */ .text # code segment main: # program entry subi $sp, $sp, 64 # reserve stack space sw $ra, 60($sp) # save return address sw $fp, 56($sp) # save frame pointer move $fp, $sp # new frame pointer user_main: la $4, g_sky # back ground color jal fillrect # fill rectangle sun: la $4, g_sun # fill a oval parameters jal filloval # fill a oval paint1: jal paint # paint off-screen buffer play_msg: la $4, move_msg # address of message jal printf # print out message your_score_msg: la $4, score_msg # address of message jal printf # print out message end_msg: la $4, end_anim_msg # address of message jal printf # print out message init_position: la $8, x # address of x_axis li $4, 295 # x = 295 (center) sw $4, 0($8) # store x li $4, 215 # y = 215 (center) sw $4, 4($8) # store y la $4, outside_tag # address of a tag sw $0, 0($4) # not outside are_you_ready?: la $4, to_start_msg # address of message jal printf # print out message jal getarrow # get an arrow key code get_timer: jal gettimer # gettimer la $4, start_time # adrress of start_time sw $2, 0($4) # store start_time add_key_listener: jal key_event_ena # enable key event animate: la $4, g_sky # back ground color jal fillrect # fill rectangle draw_circles: la $4, g_ring # draw a circle li $5, 0xff00 # color = sll $5, $5, 8 # 0xff0000 (red) sw $5, 0($4) li $5, 295 # x = 295 sw $5, 4($4) li $5, 215 # y = 215 sw $5, 8($4) li $5, 50 # rx = 50 sw $5, 12($4) li $5, 50 # ry = 50 sw $5, 16($4) li $6, 0x0303 # color sll $6, $6, 8 # diff jal drawoval # draw a oval ori $5, $5, 0xff00 # color = yellow next_circle: lw $5, 0($4) # color = sub $5, $5, $6 # color - 0x030300 sw $5, 0($4) lw $5, 4($4) # x = subi $5, $5, 5 # x - 5 sw $5, 4($4) lw $5, 8($4) # y = subi $5, $5, 5 # y - 5 sw $5, 8($4) lw $5, 12($4) # rx = addi $5, $5, 10 # rx + 10 sw $5, 12($4) lw $5, 16($4) # ry = addi $5, $5, 10 # ry + 10 sw $5, 16($4) subi $5, $5, 800 # if (ry > 800) bgez $5, draw_line_h # done jal drawoval # draw a oval j next_circle # else draw_line_h: la $4, g_drawline_h # draw a line parameters jal drawline # draw a line draw_line_v: la $4, g_drawline_v # draw a line parameters jal drawline # draw a line sun_anim: la $4, g_sun # fill a oval parameters jal filloval # fill a oval get_calendar_string: la $4, g_cals # for getting cal string addi $4, $4, 16 # place of ascii jal getcals # get calendar string cals_bg: la $4, g_cals_bg # back ground color jal fillrect3d # fill rectangle show_calendar_while_playing: la $4, g_cals # draw the string parameters jal drawstring # draw the string score_bg: la $4, g_score_bg # back ground color jal fillrect # fill rectangle show_score_message: la $4, g_center # draw the string parameters jal drawstring # draw the string show_score: la $4, g_i2s # draw the string parameters jal drawstring # draw the string show_timer: la $4, g_elapsed_s # draw the string parameters jal drawstring # draw the string paint2: jal paint # paint off-screen buffer check_tag: # check if sun went outside la $4, outside_tag # address of a tag lw $4, 0($4) # check outside bne $4, $0, remove_key_listener get_a_random_number_x: jal key_event_dis # disable key event li $4, 5 # a random number 0 -- 4 jal getrandom # get a number 0 <= r <= 4 subi $4, $2, 2 # make it -2 -- +2 jal key_event_ena # enable key event update_x: la $8, x # address of x_axis lw $9, 0($8) # load x add $9, $9, $4 # + r sw $9, 0($8) # store x get_a_random_number_y: jal key_event_dis # disable key event li $4, 5 # a random number 0 -- 4 jal getrandom # get a number 0 <= i <= 4 subi $4, $2, 2 # make it -2 -- +2 jal key_event_ena # enable key event update_y: la $8, x # address of x lw $9, 4($8) # load y (next to x) add $9, $9, $4 # + r sw $9, 4($8) # store y calculate_your_score: la $8, x # address of x lw $9, 0($8) # load x subi $9, $9, 295 # dx = x - 295 slti $10, $9, 0 # +: $10 = 0 beq $10, $0, pos_x_d # is positive sub $9, $0, $9 # dx = -dx pos_x_d: slti $10, $9, 4 # dx >= 4: $10 = 0 beq $10, $0, try_next # no score plus check_y_diff: la $8, x # address of x lw $9, 4($8) # load y (next to x) subi $9, $9, 215 # dy = y - 215 slti $10, $9, 0 # +: $10 = 0 beq $10, $0, pos_y_d # is positive sub $9, $0, $9 # dy = -dy pos_y_d: slti $10, $9, 4 # dy >= 4: $10 = 0 beq $10, $0, try_next # no score plus congratulation: # you got it la $6, score # addresss of score lw $7, 0($6) # load score addi $7, $7, 100 # + 100 sw $7, 0($6) # store score try_next: la $4, i2s_addr # address score string la $5, dec_format # convert score to la $6, score # score address lw $6, 0($6) # load score jal sprintf # integer to string get_3_random_numbers_for_bg_color_change: jal key_event_dis # disable key event li $4, 5 # a random number 0 -- 4 jal getrandom # get a number 0 <= r <= 4 subi $2, $2, 2 # make it -2 -- +2 sll $20, $2, 16 # $20: r for red color jal getrandom # get a number 0 <= r <= 4 subi $2, $2, 2 # make it -2 -- +2 sll $21, $2, 8 # $21: r for green color jal getrandom # get a number 0 <= r <= 4 subi $22, $2, 2 # $22: r for blue color jal key_event_ena # enable key event update_color: # 0x00 <--> 0xff may happen la $16, g_sky # address of bg color lw $19, 0($16) # load bg color add $17, $19, $20 # change red color add $18, $19, $21 # change green color add $19, $19, $22 # change blue color li $22, 0x0000ff # blue color position sll $21, $22, 8 # green color position sll $20, $21, 8 # red color position and $20, $20, $17 # clear other than red and $21, $21, $18 # clear other than green and $22, $22, $19 # clear other than blue or $17, $20, $21 # combine red, green or $17, $17, $22 # and blue together sw $17, 0($16) # store bg color check_x_up_bound: la $8, x # address of x lw $9, 0($8) # load x slti $9, $9, 640 # x >= 640: $9 = 0 beq $9, $0, sun_call_back check_x_low_bound: la $8, x # address of x lw $9, 0($8) # load x slti $9, $9, -50 # x >= -50: $9 = 0 bne $9, $0, sun_call_back check_y_up_bound: la $8, x # address of x lw $9, 4($8) # load y (next to x) slti $9, $9, 480 # y >= 480 beq $9, $0, sun_call_back check_y_low_bound: la $8, x # address of x lw $9, 4($8) # load y (next to x) slti $9, $9, -50 # y >= -50: $9 = 0 bne $9, $0, sun_call_back gettimer_again: jal key_event_dis # disable key event jal gettimer # gettimer la $4, start_time # adrress of start time lw $3, 0($4) # load start time sub $2, $2, $3 # elapsed time (ms) li $3, 10 # 10, ms -> cs div $2, $3 # cs in lo mflo $2 # cs la $4, timer # address of timer sw $2, 0($4) # store timer la $4, g_elapsed_s # address of elapsed_s addi $4, $4, 16 # string address la $5, dec_format # convert score to move $6, $2 # for i2s jal sprintf # integer to string jal key_event_ena # enable key event sleep_after_paint: # sleep: after paint! li $4, 100 # sleep time (ms) jal sleep # do sleep continue: j animate # to continue sun_call_back: la $8, x # address of x_axis li $4, 295 # x = 295 (center) sw $4, 0($8) # store x li $4, 215 # y = 215 (center) sw $4, 4($8) # store y la $4, outside_tag # address of a tag li $5, 1 # outside tag sw $4, 0($4) # = true j animate # last show remove_key_listener: # animation finished jal key_event_dis # disable key event your_points: la $4, points_msg # address of a message la $5, score # address of score lw $5, 0($5) # load score la $6, timer # address of timer lw $6, 0($6) # lw timer sub $7, $5, $6 # your points bgez $7, not_bad # not minus points la $4, minus_msg # address of a message j print_points # to print not_bad: la $4, points_msg # address of a message print_points: jal printf # print out message input_string_msg: la $4, string_msg # address of a message jal printf # print out message input_string: la $4, string_format # for input a string: %s la $5, user_string # a place to store string jal scanf # input string draw_inputted_string: la $4, paint_string # address of a string jal drawstring # draw the inputted string draw_1234: la $4, g_1234 # address of a string jal drawstring # draw string li $6, 1 # 1 sll $6, $6, 24 # 1 << 24 lw $5, 16($4) # load '1' add $5, $5, $6 # '2' sw $5, 16($4) # store '2' jal drawstring # draw string lw $5, 16($4) # load '1' add $5, $5, $6 # '3' sw $5, 16($4) # store '2' jal drawstring # draw string lw $5, 16($4) # load '1' add $5, $5, $6 # '4' sw $5, 16($4) # store '2' jal drawstring # draw string get_calendar: la $4, calendar # address of calendar jal getcal # get calendar print_calendar: la $3, calendar # address of calendar la $4, calendar_msg # address of parameter lw $5, 0x00($3) # load month lw $6, 0x04($3) # load date lw $7, 0x08($3) # load year lw $2, 0x10($3) # load hour sw $2, 16($sp) # put into stack lw $2, 0x14($3) # load minute sw $2, 20($sp) # put into stack lw $2, 0x18($3) # load second sw $2, 24($sp) # put into stack jal printf # printf out calendar lw $8, 16($sp) # get hour subi $6, $8, 3 # < 4:00 blez $6, draw_good_night subi $6, $8, 11 # < 12:00 blez $6, draw_good_morning subi $6, $8, 18 # < 19:00 blez $6, draw_good_afternoon draw_good_evening: # < 24:00 la $4, g_evening # address of a string jal drawstring # draw good evening j try_yours # then input your name draw_good_night: la $4, g_night # address of a string jal drawstring # draw good night j try_yours # then input your name draw_good_morning: la $4, g_morning # address of a string jal drawstring # draw good morning j try_yours # then input your name draw_good_afternoon: la $4, g_afternoon # address of a string jal drawstring # draw good_afternoon try_yours: la $4, g_sky # address of a string (sky) lw $5, 0($4) # load sky color li $6, -1 # 0xffffffff xor $5, $5, $6 # invert color la $4, try_msg # address of a string (try) sw $5, 0($4) # as try msg color jal drawstring # draw the string paint3: jal paint # paint off-screen buffer return_to_caller(os): move $sp, $fp # restore stack pointer lw $fp, 56($sp) # restore frame pointer lw $ra, 60($sp) # restore return address addi $sp, $sp, 64 # release stack space jr $ra # return to operating system __Key_Event: # pre-defined, key event entry subi $sp, $sp, 40 # reserve stack space sw $ra, 36($sp) # save return address sw $fp, 32($sp) # save frame pointer sw $3, 28($sp) # save $3 sw $4, 24($sp) # save $4 sw $5, 20($sp) # save $5 move $fp, $sp # new frame pointer key_code: move $5, $2 # key code: arrow_char la $4, x # address of x_axis test_escape: li $3, 0xff00 # escape? bne $3, $5, not_esc # no, check next is_esc: sw $3, 0($4) # 0xff00: outside x j return # return not_esc: li $3, 0x8100 # left arrow? bne $3, $5, not_left # no, check next is_left: lw $3, 0($4) # x_axis subi $3, $3, 4 # - 4 sw $3, 0($4) # store x_axis j return # return not_left: li $3, 0x8300 # right arrow? bne $3, $5, not_right # no, check next is_right: lw $3, 0($4) # x_axis addi $3, $3, 4 # + 4 sw $3, 0($4) # store x_axis j return # return not_right: li $3, 0x8000 # up arrow? bne $3, $5, not_up # no, check next is_up: lw $3, 4($4) # y_axis subi $3, $3, 4 # - 4 sw $3, 4($4) # store y_axis j return # return not_up: li $3, 0x8200 # down arrow? bne $3, $5, return # no, return is_down: lw $3, 4($4) # y_axis addi $3, $3, 4 # + 4 sw $3, 4($4) # store y_axis return: move $sp, $fp # restore stack pointer lw $5, 20($sp) # restore $5 lw $4, 24($sp) # restore $4 lw $3, 28($sp) # restore $3 lw $fp, 32($sp) # restore frame pointer lw $ra, 36($sp) # restore return address addi $sp, $sp, 40 # release stack space eret # return from exception .data # data segment g_sky: .word 0x1f7fdf # color .word 0 # x .word 0 # y .word 640 # w .word 480 # h g_sun: # moving c: .word 0xff0000 # color x: .word 295 # x y: .word 215 # y w: .word 50 # w h: .word 50 # h move_msg: .ascii "Press left, right, up, or down arrow key to move sun\n" score_msg: .ascii "Try to get score larger than the timer\n" end_anim_msg: .ascii "Pressing Escape key will terminate the animation\n" to_start_msg: .ascii "Press an arrow key to start: " outside_tag: .word 0 start_time: .word 0 g_ring: # ring .word 0xffff00 # color .word 295 # x .word 215 # y .word 50 # w .word 50 # h g_drawline_h: .word 0xff0000 # color .word 0 # x1 .word 240 # y1 .word 639 # x2 .word 240 # y2 g_drawline_v: .word 0xff0000 # color .word 320 # x1 .word 0 # y1 .word 320 # x2 .word 479 # y2 g_cals: .word 0xe0ffe0 # color .word 10 # x .word 20 # y .word 0x020112 # font name_type_size .ascii "Nov 21 2011 Mon 23:46:53" g_cals_bg: .word 0x000000 # color .word 5 # x .word 3 # y .word 272 # w .word 22 # h g_score_bg: .word 0x000000 # color .word 5 # x .word 453 # y .word 630 # w .word 22 # h g_i2s: .word 0xd0ffd0 # color .word 280 # x .word 470 # y .word 0x030112 # font name_type_size i2s_addr: .ascii "2147483647" g_1234: .word 0xdf0000 # color .word 20 # x .word 100 # y .word 0x030150 # font name_type_size .ascii "1" g_morning: .word 0xdf0000 # color .word 68 # x .word 100 # y .word 0x030136 # font name_type_size .ascii "Good Morning" g_afternoon: .word 0xdf0000 # color .word 68 # x .word 100 # y .word 0x030136 # font name_type_size .ascii "Good Afternoon" g_evening: .word 0xdf0000 # color .word 68 # x .word 100 # y .word 0x030136 # font name_type_size .ascii "Good Evening" g_night: .word 0xdf0000 # color .word 68 # x .word 100 # y .word 0x030136 # font name_type_size .ascii "Good Night" g_center: .word 0xd0ffd0 # color .word 10 # x .word 470 # y .word 0x030110 # font name_type_size .ascii "Keep the sun in the center. Score: " g_elapsed_s: .word 0xd0ffd0 # color .word 350 # x .word 470 # y .word 0x030110 # font name_type_size .ascii "-2147483648" score: # pointed by score_pointer .word 100 # see below timer: .word 0 points_msg: .ascii "You got %d - %d = %d points, congratulations!\n" minus_msg: .ascii "You got %d - %d = %d points, try again.\n" string_msg: .ascii "Input your name: " string_format: .ascii "%s" # "%s" for string calendar_msg: .asciiz "%d %d %d %02d:%02d:%02d\n" dec_format: .asciiz "%d" calendar: .word 0 # month .word 0 # date .word 0 # year .word 0 # day .word 0 # hour .word 0 # minute .word 0 # second try_msg: .word 0xffff00 # color .word 10 # x .word 358 # y .word 0x010120 # font name_type_size .ascii "This program finished. Please try yours." paint_string: .word 0xdf0000 # color .word 68 # x .word 160 # y .word 0x010136 # font name_type_size user_string: .ascii " " .end
source_codes/s/asmsim_examples.s/linked_list.s
/* * linked_list.s * Shows a linked list: * <Value, Pointer> * if Pointer == NULL, the list terminates */ `define NULL 0x0 .text # code segment main: # program entry subi $sp, $sp, 64 # reserve stack space sw $ra, 60($sp) # save return address sw $fp, 56($sp) # save frame pointer move $fp, $sp # new frame pointer user_main: la $6, node1 # address of node0's value next_node: lw $5, 0($6) # load the value of the node la $4, print_format # address format jal printf # return to operating system lw $6, 4($6) # load the linker of the node bne $6, $0, next_node # if != 0, next node return_to_caller(os): # exit(); move $sp, $fp # restore stack pointer lw $fp, 56($sp) # restore frame pointer lw $ra, 60($sp) # restore return address addi $sp, $sp, 64 # release stack space jr $ra # return to operating system .data # data segment node1: # a node .word 100, node5 # value and link pointer node2: # a node .word 200, NULL # value and terminator node3: # a node .word 300, node4 # value and link pointer node4: # a node .word 400, node2 # value and link pointer node5: # a node .word 500, node3 # value and link pointer print_format: # string address .ascii "%d\n" # string ([enter]) .end
source_codes/s/asmsim_examples.s/malooc.s
/* * malloc.s * Allocates a block of <size> bytes of memory, * returning a pointer to the beginning of the block. * Input: $4: <size> in byte * Output: $2: the address of the block */ .text # code segment .end main: # program entry subu $sp, $sp, 40 # reserve stack space sw $ra, 36($sp) # save return address sw $fp, 32($sp) # save frame pointer move $fp, $sp # new frame pointer user_main: sw $0, 20($fp) # head = NULL li $2, 0x00000001 # i = 1 sw $2, 24($fp) next_i: lw $2, 24($fp) # if slt $3, $2, 11 # i <= 10 bne $3, $0, go_on # go on j loop_ended # else loop end go_on: li $4, 0x00000008 # value, next: 2 words jal malloc # malloc sw $2, 16($fp) # address in $2 lw $2, 16($fp) # curr = address lw $3, 24($fp) sw $3, 0($2) # curr->val = i lw $2, 16($fp) lw $3, 20($fp) sw $3, 4($2) # curr->next = head lw $2, 16($fp) sw $2, 20($fp) # head = curr lw $3, 24($fp) addu $2, $3, 1 move $3, $2 sw $3, 24($fp) # i++ j next_i # next i loop_ended: lw $2, 20($fp) sw $2, 16($fp) # curr = head while: lw $2, 16($fp) # if curr bne $2, $0, continue # != NULL, continue j return_to_caller # else finish continue: lw $2, 16($fp) # printf la $4, dec_format # %d lw $5, 0($2) # curr->value jal printf # print out value lw $2, 16($fp) lw $3, 4($2) sw $3, 16($fp) # curr = curr->next j while # go to while return_to_caller: # return() move $sp, $fp # restore stack pointer lw $ra, 36($sp) # restore return address lw $fp, 32($sp) # restore frame pointer addu $sp, $sp, 40 # release stack space jr $ra # return to operating system .data # data segment dec_format: .ascii "%d\n" # %d
source_codes/s/asmsim_examples.s/picture.s
/* * picture.s * displays a picture (bitmap) with lw/sw instructions * picture size: 75 (width) * 100 (height) pixels * video ram address: (y << 10) + x; x: 0 - 639; y: 0 - 479 * pixel: (r << 16) + (g << 8) + b; 24-bit true color */ `define _Video_RAM 0xc0000000 # 0xc0000000 - 0xc007ffff .text # code segment main: # program entry subi $sp, $sp, 64 # reserve stack space sw $ra, 60($sp) # save return address sw $fp, 56($sp) # save frame pointer move $fp, $sp # new frame pointer user_main: jal refresh_vga_manu # refresh VGA manually # jal refresh_vga_auto # refresh automatically la $4, _Video_RAM # vram start address la $3, bitmap # pixel address write_pixels: li $6, 0 # for (y = 0; y < height; y++) write_a_row: li $7, 0 # for (x = 0; x < width; x++) write_a_col: addi $8, $6, 190 # centering sll $8, $8, 10 # y << 10 addi $8, $8, 282 # centering add $8, $8, $7 # + x add $9, $4, $8 # + base draw_a_pixel: lw $5, 0($3) # load pixel addi $3, $3, 4 # pixel address sw $5, 0($9) # write pixel update_x: addi $7, $7, 1 # x++ subi $8, $7, 75 # if (x < 75) bltz $8, write_a_col # goto next col jal paint # refresh VGA manually update_y: addi $6, $6, 1 # y++ subi $8, $6, 100 # if (y < 100) bltz $8, write_a_row # goto next row return_to_caller(os): # exit(); move $sp, $fp # restore stack pointer lw $fp, 56($sp) # restore frame pointer lw $ra, 60($sp) # restore return address addi $sp, $sp, 64 # release stack space jr $ra # return to operating system .data # data segment bitmap: # row 0 .word 0xb3a87b, 0xb3a87b, 0xb3a87b, 0xb4a97c, 0xb5aa7d, 0xb6ab7e, 0xb8ac82, 0xb9ad83 # row 0 .word 0xbbaf87, 0xbcb088, 0xbdb189, 0xbeb28a, 0xc0b48e, 0xc1b58f, 0xc3b791, 0xc1b891 # row 0 .word 0xc5bd99, 0xc4be9a, 0xc5bf9b, 0xc7c19d, 0xc8c2a0, 0xcac4a2, 0xcdc4a5, 0xcec5a6 # row 0 .word 0xcdc4a7, 0xcdc4a7, 0xcfc5aa, 0xd0c6ab, 0xd3c7ad, 0xd5c9af, 0xd6cab2, 0xd7cbb5 # row 0 .word 0xd9ccbc, 0xd8cabd, 0xd9cbbe, 0xdbcdc0, 0xdbcebe, 0xd9ccbc, 0xd9ccbb, 0xdacdbc # row 0 .word 0xd3c6b3, 0xe1d4c1, 0xc6baa4, 0xa99d87, 0x82765e, 0xc7bba3, 0xc2b69c, 0xbbb196 # row 0 .word 0xb6b299, 0xc4c2a9, 0xc0bea5, 0xcac8af, 0xb1af96, 0x939178, 0xafab92, 0xbab69d # row 0 .word 0x99947e, 0xc1bca6, 0xc3bda7, 0xcbc5af, 0xc7c0ad, 0xb8b19e, 0xc4bca9, 0xbdb5a2 # row 0 .word 0xc0b9a6, 0xb4ad9a, 0xc2bba8, 0xc1baa7, 0xbfb8a5, 0xc0b9a6, 0xb5ae9b, 0xc0b9a6 # row 0 .word 0xbdb6a3, 0xbeb7a4, 0xbeb7a4 # row 1 .word 0xb0a47a, 0xb0a47a, 0xb0a47a, 0xb1a57b, 0xb2a67c, 0xb3a77f, 0xb5a981, 0xb6aa82 # row 1 .word 0xb8ac86, 0xb8ac86, 0xb9ad87, 0xbbaf89, 0xbdb08d, 0xbeb18e, 0xbfb28f, 0xbeb491 # row 1 .word 0xbfb695, 0xbdb795, 0xbeb896, 0xc0ba98, 0xc2bc9c, 0xc3bd9d, 0xc6bda0, 0xc7bea1 # row 1 .word 0xc8bea3, 0xc9bfa4, 0xcac0a7, 0xccc2a9, 0xcec2aa, 0xd0c4ac, 0xd1c5af, 0xd2c5b2 # row 1 .word 0xcfc2b2, 0xcec1b1, 0xd1c3b6, 0xd5c8b8, 0xd6c9b9, 0xd4c7b6, 0xd5c8b7, 0xd8cbba # row 1 .word 0xe8dbc8, 0xd8cbb8, 0xb9ad97, 0x867a64, 0x83775f, 0xbfb39b, 0xdaceb6, 0xdad0b7 # row 1 .word 0xcfcbb0, 0xd6d4bb, 0xceccb3, 0xd3d1b8, 0xe9e7ce, 0xcfcdb4, 0xb8b49b, 0xddd9c0 # row 1 .word 0xd1ccb6, 0xe3dec8, 0xdcd6c0, 0xdcd6c0, 0xcec8b2, 0xcec7b4, 0xd0c8b5, 0xcbc3b0 # row 1 .word 0xc8c1ae, 0xd7d0bd, 0xc8c1ae, 0xcac3b0, 0xd3ccb9, 0xc1baa7, 0xbfb8a5, 0xd1cab7 # row 1 .word 0xc7c0ad, 0xc8c1ae, 0xc9c2af # row 2 .word 0xb0a380, 0xb0a380, 0xb0a380, 0xb1a481, 0xb2a582, 0xb4a785, 0xb6a987, 0xb7aa88 # row 2 .word 0xbaad8d, 0xbaad8d, 0xbcaf8f, 0xbdb090, 0xbfb194, 0xc0b295, 0xc2b497, 0xc0b597 # row 2 .word 0xc5bc9f, 0xc3bca0, 0xc5bea2, 0xc6bfa3, 0xc8c1a7, 0xc9c2a8, 0xccc2a9, 0xcdc3aa # row 2 .word 0xd0c5af, 0xd1c6b0, 0xd2c7b1, 0xd3c8b2, 0xd5cab6, 0xd6cbb7, 0xd8cdb9, 0xd8cdbb # row 2 .word 0xd9cebc, 0xd8cdbb, 0xdacebe, 0xddd2c0, 0xdbd0be, 0xd5cab8, 0xd5cab8, 0xd8cdb9 # row 2 .word 0xd3c8b4, 0xc4b9a5, 0xcdc2ac, 0xa79c86, 0xc6bba5, 0xd4c9b3, 0xddd2bc, 0xc8c1a7 # row 2 .word 0xcfcbb0, 0xcdccb0, 0xede9ce, 0xe0dcc1, 0xdbd7be, 0xe9e5cc, 0xd0cab2, 0xccc6ae # row 2 .word 0xbfb9a1, 0xcfc9b1, 0xddd5be, 0xddd5be, 0xbcb49d, 0xcdc5b0, 0xcbc0ac, 0xd3cbb6 # row 2 .word 0xc9c2af, 0xdbd4c1, 0xc4bdaa, 0xc8c1ae, 0xcac3b0, 0xc2bba8, 0xd1cab7, 0xc2bba8 # row 2 .word 0xc5beab, 0xc5beab, 0xc6bfac # row 3 .word 0xbeb191, 0xbcb191, 0xbfb292, 0xbeb393, 0xc1b396, 0xc1b698, 0xc5b79a, 0xc4b99b # row 3 .word 0xcbbda2, 0xcabfa3, 0xcdbfa4, 0xccc1a5, 0xd0c2a8, 0xd0c4aa, 0xd3c5ab, 0xd1c5ab # row 3 .word 0xd8cdb7, 0xd6ceb7, 0xd7cfb8, 0xd9d1ba, 0xdbd3be, 0xdcd4bf, 0xdfd4c0, 0xe0d5c1 # row 3 .word 0xe3d8c6, 0xe4d9c7, 0xe5dac8, 0xe6dbc9, 0xe8ddcb, 0xe9decc, 0xeadece, 0xeadfcd # row 3 .word 0xf0e5d3, 0xede2ce, 0xede2ce, 0xede2ce, 0xe6dbc9, 0xd9ceba, 0xd6cbb7, 0xdacfbb # row 3 .word 0xdcd1bd, 0xccc1ad, 0xd8cdb7, 0xbbb09a, 0xded3bd, 0xdacfb9, 0xdacfbb, 0xccc4ad # row 3 .word 0xbcb89d, 0x89856a, 0x6a664b, 0x787459, 0x9e9a81, 0x8e8a71, 0x625c44, 0x756f57 # row 3 .word 0x817b63, 0x706a52, 0x746c55, 0x807861, 0x857d66, 0xc7bca6, 0xc6bba5, 0xd2c7b3 # row 3 .word 0xcbc3b0, 0xc1baa7, 0xc5beab, 0xc9c2af, 0xc0b9a6, 0xd1cab7, 0xded7c4, 0xbcb5a2 # row 3 .word 0xc5beab, 0xc6bfac, 0xc7c0ad # row 4 .word 0xcec3a7, 0xcdc4a7, 0xcfc4a8, 0xcfc6a9, 0xd2c6ac, 0xd3c9ae, 0xd6cab0, 0xd6ccb1 # row 4 .word 0xdaceb6, 0xdad0b7, 0xdcd0b8, 0xddd3ba, 0xdfd3bd, 0xe0d5bf, 0xe2d6c0, 0xe2d7c1 # row 4 .word 0xe2d7c5, 0xe3d8c6, 0xe4d9c7, 0xe5dac8, 0xe7dcca, 0xe8ddcb, 0xeadfcd, 0xeadfcd # row 4 .word 0xece0d0, 0xede1d1, 0xeee2d2, 0xefe3d3, 0xf0e4d4, 0xf1e5d5, 0xf2e6d8, 0xf2e6d6 # row 4 .word 0xf2ead5, 0xeee6cf, 0xefe7d0, 0xf0e8d1, 0xe6dec9, 0xd7cfb8, 0xd2cab3, 0xd9d1ba # row 4 .word 0xe0d8c3, 0xd5cdb8, 0xcec6b1, 0xbdb5a0, 0xcec6b1, 0xd3cbb6, 0xcac2af, 0xd6ceb9 # row 4 .word 0x9e9880, 0x342e14, 0x2b250b, 0x6a644a, 0x666046, 0x7d775d, 0xb0a98f, 0x898268 # row 4 .word 0x857e64, 0x888167, 0x9d937a, 0xa2987f, 0xa2987f, 0xcec2aa, 0xcabea6, 0xd9ceb8 # row 4 .word 0xd6ceb9, 0xc3bca9, 0xd7d0bd, 0xd4cdba, 0xd5cebb, 0xcbc4b1, 0xb0a996, 0xd9d2bf # row 4 .word 0xd7d0bd, 0xd7d0bd, 0xd8d1be # row 5 .word 0xd0c6ab, 0xd0c7aa, 0xd1c7ac, 0xd2c8ad, 0xd4caaf, 0xd6ccb1, 0xd9cfb6, 0xdad0b7 # row 5 .word 0xd9cfb6, 0xdacfb9, 0xdbd0ba, 0xdcd1bb, 0xded3bd, 0xdfd4be, 0xe1d6c2, 0xe1d6c2 # row 5 .word 0xdfd4c2, 0xdfd4c2, 0xe1d6c4, 0xe2d7c5, 0xe4d9c7, 0xe5dac8, 0xe6daca, 0xe7dbcb # row 5 .word 0xe8dccc, 0xe9ddcd, 0xe9ddcd, 0xeadece, 0xebdfcf, 0xece0d0, 0xede1d3, 0xebe3d0 # row 5 .word 0xece4cd, 0xe8e1c7, 0xebe3cc, 0xefe7d0, 0xe6dec7, 0xd5cdb6, 0xd2cab3, 0xdbd3bc # row 5 .word 0xcec6b1, 0xd4ccb7, 0xccc4af, 0xccc4b1, 0xd1c9b6, 0xdbd3c0, 0xc2b9a8, 0xd7cfbc # row 5 .word 0xa09a82, 0x595339, 0x433d23, 0x999379, 0xbfb99f, 0xb6b096, 0xcec7ad, 0xc0b99f # row 5 .word 0xbbb49a, 0xcac3a9, 0xd8ceb5, 0xcdc3aa, 0xd9cdb5, 0xe0d4bc, 0xdaceb6, 0xe2d7c1 # row 5 .word 0xdfd7c2, 0xdad3c0, 0xe1dac7, 0xd1cab7, 0xe3dcc9, 0xa19a87, 0x5b5441, 0xded7c4 # row 5 .word 0xdfd8c5, 0xe0d9c6, 0xe1dac7 # row 6 .word 0xccc3a6, 0xccc3a4, 0xcdc4a7, 0xcfc6a9, 0xd1c8ab, 0xd3caad, 0xd5cbb0, 0xd7cdb2 # row 6 .word 0xd6ccb1, 0xd6ccb3, 0xd7cdb4, 0xd9cfb6, 0xdbd1b8, 0xdcd2b9, 0xddd2bc, 0xded3bd # row 6 .word 0xe0d4be, 0xe1d4c1, 0xe2d5c2, 0xe4d7c4, 0xe4d9c5, 0xe6dbc7, 0xe7dcca, 0xe8ddcb # row 6 .word 0xe9decc, 0xe9decc, 0xe8e0cd, 0xe8e0cd, 0xe9e1ce, 0xeae2cf, 0xeae1d0, 0xebe3ce # row 6 .word 0xf0e9cf, 0xeae5c8, 0xece6cc, 0xefe9cf, 0xe3ddc3, 0xcfc9b1, 0xcbc5ad, 0xd5cfb9 # row 6 .word 0xd6cfbc, 0xd9d2bf, 0xc6bfac, 0xbeb7a5, 0xcbc4b2, 0xded7c5, 0xd0c9b9, 0xeee7d5 # row 6 .word 0xaea892, 0x2e2810, 0x363018, 0xc4bea6, 0xfff7e0, 0xe3dbc4, 0xd8d1b7, 0xd4cdb3 # row 6 .word 0xd7cdb4, 0xbbb198, 0x877b63, 0x796d55, 0xd4c8ae, 0xeadec4, 0xeee2c8, 0xdcd2b9 # row 6 .word 0xdfd7c2, 0xdcd5c2, 0xdcd5c2, 0xd0c9b6, 0xddd6c3, 0xa69f8c, 0x716a57, 0xd4cdba # row 6 .word 0xdad3c0, 0xdbd4c1, 0xdcd5c2 # row 7 .word 0xcfc6a5, 0xcfc7a3, 0xd0c7a6, 0xd2c9a8, 0xd4cbaa, 0xd7cead, 0xd9d0b1, 0xdad1b2 # row 7 .word 0xdcd3b4, 0xdcd3b6, 0xddd4b7, 0xdfd6b9, 0xe1d7bc, 0xe2d9bc, 0xe3d9be, 0xe4dabf # row 7 .word 0xe8dcc2, 0xe8dcc2, 0xe9ddc3, 0xebdfc5, 0xede1c9, 0xede3ca, 0xeee4cb, 0xefe4ce # row 7 .word 0xf1e6d0, 0xf1e6d0, 0xf0e8d1, 0xf0e8d1, 0xf1e9d4, 0xf2ead5, 0xf2ead5, 0xf1ebd3 # row 7 .word 0xf8f2d8, 0xf0ead0, 0xf0ead0, 0xf0ead0, 0xded8be, 0xc5bfa7, 0xbdb7a1, 0xc6bfac # row 7 .word 0xcfc8b5, 0xd4cdbb, 0xc8c1af, 0xbbb4a4, 0xd6cfbf, 0xe3dccc, 0xd5cebe, 0xebe4d2 # row 7 .word 0xe1dac7, 0xeee8d0, 0xf6f0da, 0xdcd6be, 0xe8e0cb, 0xf3ebd4, 0xd3cbb4, 0xd8d1b7 # row 7 .word 0xcbc1a8, 0xd2c8af, 0xada189, 0x968a72, 0xece0c6, 0xdaceb4, 0xe4d8be, 0xd6ccb3 # row 7 .word 0xded6c1, 0xcfc8b5, 0xdcd5c2, 0xe0d9c6, 0xdcd5c2, 0xe5decb, 0xe3dcc9, 0xe0d9c6 # row 7 .word 0xdad3c0, 0xdbd4c1, 0xdcd5c2 # row 8 .word 0xd2caa3, 0xd1caa0, 0xd0c8a1, 0xcfc7a0, 0xcec69f, 0xcec69f, 0xcec6a1, 0xcfc7a2 # row 8 .word 0xcec6a1, 0xcec6a2, 0xcdc5a1, 0xcdc5a1, 0xccc3a2, 0xcbc39f, 0xcac1a0, 0xcac1a0 # row 8 .word 0xc7bc9c, 0xc6b999, 0xbdb090, 0xc5ba9a, 0xc3b89a, 0xb3a88a, 0xb1a889, 0xafa689 # row 8 .word 0x999275, 0xa8a184, 0xa19a7e, 0x968f73, 0x989278, 0x8f896f, 0x868066, 0x918b71 # row 8 .word 0x7f795f, 0x949077, 0x9f9b82, 0xb6b299, 0xddd9c0, 0x938e78, 0x645f49, 0x88836f # row 8 .word 0xbdb8a5, 0xc0baaa, 0xa59f8f, 0xa19b8d, 0xc2bcae, 0xe1dbcd, 0xe4ded0, 0xd7d1c1 # row 8 .word 0xe5decc, 0xece6d0, 0xefe8d5, 0xebe5cf, 0xe8e1ce, 0xe7e1cb, 0xe2dac5, 0xd9d1ba # row 8 .word 0xd1c9b2, 0xcfc7b0, 0xddd3ba, 0xe7ddc4, 0xe3d9c0, 0xe1d7be, 0xe3d7bd, 0xdfd5bc # row 8 .word 0xded6c1, 0xdad3c0, 0xd8d1be, 0xd8d1be, 0xdad3c0, 0xdcd5c2, 0xdad3c0, 0xd8d1be # row 8 .word 0xd9d2bf, 0xdcd5c2, 0xdfd8c5 # row 9 .word 0x797143, 0x777042, 0x776f41, 0x756e40, 0x766d42, 0x756e42, 0x766d42, 0x756e42 # row 9 .word 0x776e45, 0x756e44, 0x766d46, 0x746c45, 0x746b44, 0x726a43, 0x736a43, 0x726942 # row 9 .word 0x6a5e38, 0x6d613b, 0x6d613b, 0x6f633d, 0x746a46, 0x625834, 0x3c3410, 0x2b2201 # row 9 .word 0x3a3412, 0x352f0f, 0x2f280b, 0x383315, 0x4f4a2d, 0x5b5639, 0x605b3e, 0x69654a # row 9 .word 0x7f7a64, 0x8f8a74, 0x56513b, 0x85806a, 0x7a7561, 0x7d7864, 0x2c2714, 0x46412e # row 9 .word 0x4e4838, 0x8e887a, 0x565042, 0x746e60, 0x696357, 0x857f73, 0x8a8478, 0xa59f91 # row 9 .word 0x9c9686, 0xa19c89, 0xb4ad9b, 0xcdc6b4, 0xd9d2c0, 0xd6cfbc, 0xd0c9b6, 0xd1c9b4 # row 9 .word 0xcbc3ae, 0xd6ceb7, 0xdcd4bd, 0xd8ceb5, 0xd7cdb4, 0xe0d6bd, 0xe2d8bf, 0xdcd2b9 # row 9 .word 0xded6c1, 0xdbd4c1, 0xd8d1be, 0xd8d1be, 0xdad3c0, 0xdbd4c1, 0xdad3c0, 0xd8d1be # row 9 .word 0xd8d1be, 0xdcd5c2, 0xdfd8c5 # row 10 .word 0x817746, 0x7e7645, 0x7f7544, 0x7d7544, 0x7e7345, 0x7d7546, 0x7f7446, 0x7d7546 # row 10 .word 0x817649, 0x7e7648, 0x80744a, 0x7d7449, 0x7e7248, 0x7b7247, 0x7d7147, 0x7d7147 # row 10 .word 0x7e7346, 0x7f7246, 0x7d7245, 0x6f6339, 0x837a51, 0x7c734a, 0x3f3710, 0x362e09 # row 10 .word 0x413b19, 0x453f1f, 0x484325, 0x4f4a2c, 0x696447, 0x8d896e, 0x918d72, 0x78735d # row 10 .word 0x8d8875, 0x787564, 0x7b7867, 0x484534, 0x807d6c, 0x4f4c3b, 0x555243, 0x434031 # row 10 .word 0x646152, 0x4d493d, 0x524e42, 0x494539, 0x413d32, 0x5f5b50, 0x625e53, 0x646054 # row 10 .word 0x4d4a3b, 0x545142, 0x534d3d, 0x5f5949, 0x9a9484, 0xdfdac7, 0xede8d5, 0xd3ccb9 # row 10 .word 0xc7c0ad, 0xd3cdb7, 0xd3cdb7, 0xd4ccb5, 0xdfd7c0, 0xe3dbc4, 0xddd5be, 0xdad2bb # row 10 .word 0xddd7c1, 0xdbd4c1, 0xd9d2bf, 0xd9d2bf, 0xdad3c0, 0xdad3c0, 0xdad3c0, 0xd8d1be # row 10 .word 0xd8d1be, 0xdbd4c1, 0xdfd8c5 # row 11 .word 0x807442, 0x7e7441, 0x7f7341, 0x7d7340, 0x7e7242, 0x7d7342, 0x7f7343, 0x7e7443 # row 11 .word 0x827548, 0x807547, 0x817448, 0x7f7447, 0x7f7246, 0x7d7245, 0x7e7145, 0x7d7044 # row 11 .word 0x847848, 0x807444, 0x827548, 0x6c6133, 0x877c4f, 0x80774e, 0x3c330c, 0x48401b # row 11 .word 0x3f3917, 0x443e1e, 0x585336, 0x676147, 0x68644b, 0x736e58, 0x6c6751, 0x484532 # row 11 .word 0x474435, 0x3f3b2f, 0x433f33, 0x2f2b1f, 0x454135, 0x332f23, 0x383429, 0x2c281d # row 11 .word 0x221e13, 0x514d42, 0x332f24, 0x2b271c, 0x413d32, 0x080400, 0x262217, 0x272318 # row 11 .word 0x2d291e, 0x3b392c, 0x595549, 0x636051, 0x464334, 0x353221, 0x6b6857, 0xbab5a2 # row 11 .word 0xd4cfbc, 0xd3ceba, 0xcfc8b5, 0xd7d1bb, 0xe4dec8, 0xddd7bf, 0xd7cfb8, 0xe0dac4 # row 11 .word 0xddd6c3, 0xdcd5c2, 0xdad3c0, 0xd9d2bf, 0xd9d2bf, 0xd9d2bf, 0xd9d2bf, 0xd9d2bf # row 11 .word 0xd8d1be, 0xdbd4c1, 0xdfd8c5 # row 12 .word 0x867849, 0x847848, 0x857748, 0x837747, 0x847649, 0x84774a, 0x86784b, 0x85784b # row 12 .word 0x897a4f, 0x877a4e, 0x88794e, 0x86794d, 0x86774e, 0x84774d, 0x85764d, 0x85764b # row 12 .word 0x807243, 0x7d713f, 0x887c4c, 0x7a6f41, 0x8e8356, 0x7a7148, 0x342a06, 0x49411d # row 12 .word 0x524c2c, 0x494226, 0x615b43, 0x78725c, 0x605b48, 0x464030, 0x3e3b2c, 0x3b372b # row 12 .word 0x363229, 0x312e27, 0x14110a, 0x46433c, 0x2c2920, 0x49463d, 0x201d14, 0x221f16 # row 12 .word 0x252219, 0x1e1b12, 0x4a473e, 0x656259, 0x3a372e, 0x4a473e, 0x2d2a21, 0x1d1a11 # row 12 .word 0x343128, 0x24241a, 0x333027, 0x575549, 0x5d5b4f, 0x413f32, 0x333124, 0x3e3b2c # row 12 .word 0xb3b09f, 0xcac7b4, 0xdbd6c3, 0xd9d4c0, 0xd3ceba, 0xd0cbb5, 0xd7d1bb, 0xe3ddc7 # row 12 .word 0xddd6c3, 0xdcd5c2, 0xdbd4c1, 0xdad3c0, 0xd8d1be, 0xd8d1be, 0xd8d1be, 0xd9d2bf # row 12 .word 0xd7d0bd, 0xdad3c0, 0xded7c4 # row 13 .word 0x867549, 0x847649, 0x867549, 0x837548, 0x867549, 0x85764b, 0x87764b, 0x86774c # row 13 .word 0x8a794e, 0x887950, 0x89774f, 0x86774e, 0x887650, 0x85764f, 0x86744e, 0x84754c # row 13 .word 0x807243, 0x7f7142, 0x817545, 0x7a6d40, 0x8c8056, 0x81754f, 0x4d4320, 0x564d2e # row 13 .word 0x4d4328, 0x5c543d, 0x625b48, 0x4a4434, 0x312b1f, 0x332c22, 0x322e25, 0x241f19 # row 13 .word 0x1f1c17, 0x120e0b, 0x191512, 0x292621, 0x312e29, 0x1e1b16, 0x17140f, 0x1b1811 # row 13 .word 0x120f08, 0x312e27, 0x17140d, 0x39362d, 0x5e5b52, 0x47443b, 0x48453c, 0x1f1f15 # row 13 .word 0x111109, 0x22221a, 0x27271f, 0x27271d, 0x434339, 0x636357, 0x565448, 0x2d2b1e # row 13 .word 0x494738, 0x8e8b7a, 0xd7d4c3, 0xe4e1ce, 0xd0cdba, 0xd7d2be, 0xe2ddc9, 0xd8d3bf # row 13 .word 0xddd6c3, 0xddd6c3, 0xddd6c3, 0xdbd4c1, 0xd8d1be, 0xd7d0bd, 0xd8d1be, 0xd9d2bf # row 13 .word 0xd6cfbc, 0xdad3c0, 0xded7c4 # row 14 .word 0x8d7a50, 0x8c7b50, 0x8d7a50, 0x8c7b50, 0x8d7a50, 0x8d7b53, 0x8f7c54, 0x8f7d55 # row 14 .word 0x917e56, 0x907e58, 0x907c57, 0x8e7c56, 0x8e7a57, 0x8d7b57, 0x8d7956, 0x8c7a54 # row 14 .word 0x8b7d50, 0x8d7f50, 0x807346, 0x7b6e42, 0x92865e, 0x9b8e6b, 0x786d4f, 0x594f34 # row 14 .word 0x352a16, 0x534a39, 0x473f32, 0x1d160c, 0x1d1610, 0x35302c, 0x2d2825, 0x0d0707 # row 14 .word 0x050102, 0x0d0b0c, 0x131210, 0x22211f, 0x1e1d1b, 0x0f0e0a, 0x060501, 0x181712 # row 14 .word 0x100f0a, 0x040400, 0x404038, 0x23231b, 0x2e2e24, 0x28281e, 0x57574d, 0x3e3e36 # row 14 .word 0x393a34, 0x262721, 0x171812, 0x16170f, 0x1a1b13, 0x1d1f14, 0x232319, 0x2a2a1e # row 14 .word 0x0a0b00, 0x3d3b2c, 0xa1a08e, 0xdddcc8, 0xd6d5c1, 0xdbd8c5, 0xe5e2cf, 0xd3ceba # row 14 .word 0xdcd5c2, 0xded7c4, 0xded7c4, 0xdbd4c1, 0xd7d0bd, 0xd6cfbc, 0xd7d0bd, 0xd9d2bf # row 14 .word 0xd6cfbc, 0xdad3c0, 0xded7c4 # row 15 .word 0x8e7b53, 0x8e7b51, 0x8e7b53, 0x8e7b51, 0x8e7b53, 0x8f7c54, 0x907d55, 0x917e56 # row 15 .word 0x927f57, 0x927f57, 0x917d58, 0x907c57, 0x8f7b58, 0x8f7b58, 0x8e7a57, 0x8d7b55 # row 15 .word 0x817247, 0x8e8154, 0x807349, 0x7f714c, 0x988b69, 0xa5977a, 0x796d53, 0x2b200a # row 15 .word 0x372f1c, 0x302919, 0x221c10, 0x2e2a21, 0x4a4742, 0x433f3e, 0x282629, 0x252326 # row 15 .word 0x17151a, 0x181619, 0x1b191c, 0x1a1819, 0x373536, 0x201f1d, 0x0d0c08, 0x070602 # row 15 .word 0x0c0b06, 0x25251d, 0x2f2f27, 0x3d3d33, 0x424238, 0x4e4e42, 0x67675b, 0x4c4c42 # row 15 .word 0x24251f, 0x24251f, 0x21221c, 0x1c1d17, 0x21221c, 0x2b2c26, 0x2d2e28, 0x282921 # row 15 .word 0x28281e, 0x131307, 0x5e5f51, 0xc0beaf, 0xcdccba, 0xcecdb9, 0xe0ddca, 0xdbd6c2 # row 15 .word 0xdcd6c0, 0xded8c2, 0xded8c2, 0xdbd4c1, 0xd7d0bd, 0xd5cebb, 0xd7d0bd, 0xd9d2c0 # row 15 .word 0xd6cfbd, 0xd9d2c0, 0xded7c5 # row 16 .word 0x907f54, 0x8f7e52, 0x8d7c51, 0x8e7d51, 0x907f54, 0x928156, 0x928156, 0x918055 # row 16 .word 0x948358, 0x948358, 0x938257, 0x928156, 0x918055, 0x907f54, 0x907f54, 0x8f7e53 # row 16 .word 0x93865a, 0x8c8056, 0x776b45, 0x8e8161, 0xa5977d, 0x7d6e59, 0x251807, 0x1d1101 # row 16 .word 0x433a29, 0x3e3828, 0x433f33, 0x37372d, 0x363731, 0x3d3f3e, 0x2c2f34, 0x292c33 # row 16 .word 0x191a1f, 0x0f0e13, 0x0d0c11, 0x29292b, 0x1f1f1f, 0x0d0d0b, 0x20211c, 0x151611 # row 16 .word 0x23221d, 0x25251d, 0x16160c, 0x212115, 0x5c5d4f, 0x494a3c, 0x2d2e1e, 0x3b3c2e # row 16 .word 0x3c3c32, 0x2e2d28, 0x24231e, 0x1f201b, 0x161614, 0x0f110e, 0x1f211e, 0x383a37 # row 16 .word 0x191a15, 0x171812, 0x19190f, 0x545245, 0x807e6f, 0xd7d4c1, 0xe7e2ce, 0xdcd7c1 # row 16 .word 0xded8c0, 0xd7d1b7, 0xe4dec6, 0xcdc7b1, 0xdfd8c5, 0xdbd4c1, 0xdbd4c2, 0xcbc4b4 # row 16 .word 0xd5cebe, 0xdbd4c4, 0xe1daca # row 17 .word 0x948357, 0x928155, 0x907f53, 0x918054, 0x938256, 0x958458, 0x958458, 0x948357 # row 17 .word 0x97865a, 0x97865a, 0x968559, 0x958458, 0x948357, 0x948357, 0x938256, 0x918356 # row 17 .word 0x897c50, 0x8c8056, 0xa39674, 0x76684d, 0x92836e, 0x392c1c, 0x281c0e, 0x2f2519 # row 17 .word 0x2d2518, 0x3f3c2d, 0x545245, 0x3c3e33, 0x282a25, 0x212526, 0x080d13, 0x000007 # row 17 .word 0x0c0b11, 0x0c0a0f, 0x0f0d12, 0x252326, 0x1b191a, 0x0d0d0b, 0x191814, 0x080703 # row 17 .word 0x1f1e19, 0x2f2f27, 0x3a3a30, 0x2c2c20, 0x434436, 0x434436, 0x464737, 0x3e3f31 # row 17 .word 0x353229, 0x333029, 0x272320, 0x191814, 0x1b1b1b, 0x252726, 0x242527, 0x191a1c # row 17 .word 0x282a29, 0x20221d, 0x000100, 0x37372b, 0x716f60, 0x5e5b48, 0xe9e7d2, 0xcdc9b0 # row 17 .word 0xe3ddc3, 0xdcd6bc, 0xe4dec6, 0xded8c0, 0xddd6c3, 0xd1cab7, 0xdad3c3, 0xede6d6 # row 17 .word 0xdad2c5, 0xddd6c6, 0xe1daca # row 18 .word 0x95875a, 0x948659, 0x928457, 0x928457, 0x948659, 0x96885b, 0x96885b, 0x95875a # row 18 .word 0x988a5d, 0x97895c, 0x97895c, 0x96885b, 0x95875a, 0x95875a, 0x948659, 0x948659 # row 18 .word 0x887a4d, 0xa6996f, 0x847755, 0x897b61, 0x5a4d3c, 0x45392d, 0x140a01, 0x312a20 # row 18 .word 0x171308, 0x2b291d, 0x3b3b31, 0x24241c, 0x191a15, 0x282828, 0x1d1c22, 0x131218 # row 18 .word 0x09040a, 0x130e12, 0x161115, 0x1c1819, 0x141011, 0x100f0d, 0x1b1714, 0x090502 # row 18 .word 0x0b0704, 0x282520, 0x2a2924, 0x585850, 0x36362c, 0x65655b, 0x45453b, 0x2e2e24 # row 18 .word 0x28251e, 0x312e27, 0x2e2a27, 0x1e1d19, 0x191919, 0x212121, 0x252628, 0x212224 # row 18 .word 0x2d2f2e, 0x1c1e1b, 0x181913, 0x0b0b01, 0x323325, 0x5e5d4b, 0x65624f, 0xe6e1cb # row 18 .word 0xd8d2ba, 0xe0dac0, 0xdad4bc, 0xe9e3cb, 0xe6dfcc, 0xe4ddca, 0xd7d0c0, 0xded7c7 # row 18 .word 0xe1daca, 0xe2dbcb, 0xe1daca # row 19 .word 0x97895c, 0x95875a, 0x948659, 0x948659, 0x96885b, 0x97895c, 0x96885b, 0x96885b # row 19 .word 0x988a5d, 0x988a5d, 0x988a5d, 0x97895c, 0x97895c, 0x96885b, 0x96885b, 0x95875a # row 19 .word 0x948659, 0x988960, 0x8c7d5c, 0x665a42, 0x6e6254, 0x332a21, 0x261e1b, 0x1c1914 # row 19 .word 0x31302b, 0x272621, 0x21201b, 0x0e0d08, 0x16120f, 0x2a2625, 0x1f191d, 0x170e13 # row 19 .word 0x150c0d, 0x221817, 0x211716, 0x150d0b, 0x100806, 0x1c1412, 0x271f1c, 0x1c1713 # row 19 .word 0x27221e, 0x18130f, 0x2b2622, 0x27241f, 0x3a3730, 0x35322b, 0x48453e, 0x3b3831 # row 19 .word 0x3f3a34, 0x362f29, 0x292420, 0x211d1a, 0x161513, 0x111111, 0x1b1b1d, 0x2b2c2e # row 19 .word 0x1b1d1c, 0x20221f, 0x383933, 0x000200, 0x2d2f21, 0x474836, 0x3d3c28, 0xbfbda6 # row 19 .word 0xebe7ce, 0xd9d3b9, 0x827c64, 0x79735d, 0x938c79, 0xded7c4, 0xe3dcca, 0xded7c7 # row 19 .word 0xe0d9c9, 0xdfd8c6, 0xddd6c4 # row 20 .word 0x98895e, 0x96875c, 0x95865b, 0x95865b, 0x96875c, 0x97885d, 0x96875c, 0x95865b # row 20 .word 0x98895e, 0x98895e, 0x97885d, 0x97885d, 0x97885d, 0x97885d, 0x96875c, 0x96885b # row 20 .word 0x968559, 0x938159, 0x9a8b6a, 0x534731, 0x686055, 0x0c0703, 0x292728, 0x19191b # row 20 .word 0x2d2e30, 0x151515, 0x12110d, 0x13100b, 0x1f1715, 0x221817, 0x0f0003, 0x0b0000 # row 20 .word 0x21120f, 0x2d1e19, 0x2f201b, 0x1f100b, 0x1d0e09, 0x281b15, 0x2e201d, 0x302521 # row 20 .word 0x2a1f1b, 0x3b312f, 0x2d2321, 0x312725, 0x19110e, 0x1f1714, 0x191410, 0x3b3330 # row 20 .word 0x5c534e, 0x3f3430, 0x201614, 0x170f0d, 0x181212, 0x171314, 0x0f0f11, 0x0c0c0e # row 20 .word 0x1a1c1b, 0x0f110e, 0x2b2d28, 0x3b3e35, 0x040800, 0x4a4d3c, 0x353825, 0x797863 # row 20 .word 0xd1ccb6, 0xbdb79f, 0x4a442e, 0x48422c, 0x77705d, 0xd5cebb, 0xd7d0be, 0xc6bfad # row 20 .word 0xc7c0ae, 0xc6bfad, 0xc5beac # row 21 .word 0x9c8d62, 0x9a8b60, 0x98895e, 0x97885d, 0x998a5f, 0x998a5f, 0x998a5f, 0x98895e # row 21 .word 0x998a5f, 0x998a5f, 0x998a5f, 0x998a5f, 0x998a5f, 0x998a5f, 0x998a5f, 0x998a5f # row 21 .word 0x9a895d, 0xa8966e, 0x625334, 0x6b604c, 0x272018, 0x1b191a, 0x0a0b10, 0x1a1d24 # row 21 .word 0x101318, 0x000105, 0x0c0807, 0x160e0b, 0x1d0f0e, 0x1e0c0a, 0x180302, 0x2d1312 # row 21 .word 0x2f160f, 0x3a2216, 0x472f23, 0x3e281b, 0x3e281d, 0x3a261d, 0x2f1b12, 0x3f2c25 # row 21 .word 0x34211b, 0x3f2e27, 0x55433f, 0x20110c, 0x423330, 0x190b08, 0x251716, 0x190b08 # row 21 .word 0x3c2d28, 0x3f302b, 0x30221f, 0x170c0a, 0x120809, 0x1a1416, 0x130f10, 0x000002 # row 21 .word 0x151515, 0x121411, 0x161813, 0x272a21, 0x3f4335, 0x020600, 0x505541, 0x32341f # row 21 .word 0xe1dcc6, 0xdfd9c3, 0x7a745e, 0x7d7761, 0x98917e, 0xd2cbb8, 0xddd6c4, 0xe6dfcd # row 21 .word 0xe1dac8, 0xe0d9c6, 0xdfd8c5 # row 22 .word 0xa09367, 0x9e9165, 0x9c8f63, 0x9c8f63, 0x9d9064, 0x9d9064, 0x9d9064, 0x9b8e62 # row 22 .word 0x9d9064, 0x9d9064, 0x9d9064, 0x9d9064, 0x9d9064, 0x9d9064, 0x9d9064, 0x9e8f64 # row 22 .word 0xa8976b, 0x9a8862, 0x433518, 0x524938, 0x221d19, 0x16151a, 0x080b14, 0x0b0f1a # row 22 .word 0x131720, 0x0a0b10, 0x150f11, 0x130806, 0x140100, 0x1e0501, 0x2a0b08, 0x48251f # row 22 .word 0x4c2b1a, 0x51311c, 0x664532, 0x694835, 0x684736, 0x533422, 0x391c0c, 0x563a2c # row 22 .word 0x6a4e42, 0x573c31, 0x3e231a, 0x3b221b, 0x2a110c, 0x3b241e, 0x371f1b, 0x2e1914 # row 22 .word 0x1b0700, 0x38251e, 0x42312a, 0x291a15, 0x150706, 0x140a09, 0x130d0f, 0x0b0708 # row 22 .word 0x101010, 0x070906, 0x1c1e19, 0x060b04, 0x282e22, 0x3f4537, 0x091000, 0x282b18 # row 22 .word 0xa2a08b, 0xf1ead7, 0xd9d2bf, 0xe8e1ce, 0xe5decc, 0xe3dcca, 0xd8d1bf, 0xd7d0be # row 22 .word 0xdad3c0, 0xd6cfbc, 0xd2cbb8 # row 23 .word 0xa5986c, 0xa3966a, 0xa19468, 0xa09367, 0xa19468, 0xa29569, 0xa19468, 0xa09367 # row 23 .word 0xa19468, 0xa19468, 0xa19468, 0xa19468, 0xa29569, 0xa29569, 0xa29569, 0xa39469 # row 23 .word 0xa29166, 0x877753, 0x413319, 0x473e2f, 0x2a2623, 0x08090e, 0x0c101b, 0x080c18 # row 23 .word 0x03060f, 0x040308, 0x140b0c, 0x140200, 0x1e0500, 0x37160f, 0x431c15, 0x572d1f # row 23 .word 0x6e442c, 0x6b4224, 0x80573b, 0x885f43, 0x875d44, 0x673f26, 0x49230c, 0x714d37 # row 23 .word 0x876250, 0x573323, 0x583426, 0x6b493d, 0x3a180e, 0x2f0f04, 0x3c1b12, 0x3a1c12 # row 23 .word 0x31150a, 0x382016, 0x3f2820, 0x39251e, 0x271511, 0x130504, 0x0b0100, 0x090303 # row 23 .word 0x050304, 0x0a0a08, 0x171916, 0x060b05, 0x13190f, 0x4d5347, 0x242a1c, 0x080a00 # row 23 .word 0x646150, 0xe3dcc9, 0xe5decc, 0xdcd5c3, 0xcfc8b6, 0xd0c9b7, 0xd8d1bf, 0xd6cfbc # row 23 .word 0xddd6c3, 0xd5cfb9, 0xccc6b0 # row 24 .word 0xa99c72, 0xa99c72, 0xa79a70, 0xa6996f, 0xa5986e, 0xa5986e, 0xa5986e, 0xa5986e # row 24 .word 0xa6996f, 0xa99c72, 0xa99c72, 0xa1946a, 0xa79a70, 0xab9e74, 0xa1946a, 0xa89b71 # row 24 .word 0xb3a47d, 0x6c5d3c, 0x32260e, 0x261e13, 0x201c1b, 0x0a0911, 0x00010d, 0x080a16 # row 24 .word 0x04030b, 0x130d11, 0x180a07, 0x1e0701, 0x35150a, 0x4c2418, 0x633528, 0x774733 # row 24 .word 0x865535, 0x9a6843, 0xab7956, 0xb0805c, 0xa87756, 0x8b5d3b, 0x794a2c, 0x7c4f32 # row 24 .word 0xa17359, 0x8e6249, 0x6c3f28, 0x582b16, 0x5e311e, 0x5a2f1e, 0x491e0e, 0x3a1302 # row 24 .word 0x3b1707, 0x39190a, 0x33150a, 0x2e130a, 0x341d17, 0x392622, 0x251716, 0x080000 # row 24 .word 0x110b0b, 0x0d0c0a, 0x0d0f0c, 0x020701, 0x0b100a, 0x181f17, 0x3f473c, 0x0e1204 # row 24 .word 0x191607, 0xbab3a1, 0xdbd4c4, 0xc8c1af, 0xdbd4c2, 0xd3ccba, 0xb9b29f, 0xc9c2af # row 24 .word 0xcfc8b5, 0xc6c0aa, 0xbbb59f # row 25 .word 0xada076, 0xac9f75, 0xab9e74, 0xa99c72, 0xa89b71, 0xa89b71, 0xa89b71, 0xa89b71 # row 25 .word 0xa99c72, 0xac9f75, 0xac9f75, 0xa89b71, 0xab9e74, 0xab9e74, 0xa6996f, 0xad9f78 # row 25 .word 0x9b8d6a, 0x4c3e21, 0x2b200c, 0x231a11, 0x040000, 0x030007, 0x12101b, 0x010007 # row 25 .word 0x0b0509, 0x130806, 0x1e0a03, 0x33170b, 0x502b19, 0x633623, 0x794432, 0x945c43 # row 25 .word 0xa6704a, 0xb78256, 0xc38e64, 0xc89369, 0xc28d65, 0xa8744d, 0x95613c, 0x976240 # row 25 .word 0xb2805f, 0xaa7758, 0x925f42, 0x804d30, 0x814e33, 0x7c4a31, 0x6f3d24, 0x66361f # row 25 .word 0x522810, 0x512b16, 0x4b2614, 0x3d1d0e, 0x371b10, 0x351e16, 0x2d1b17, 0x211312 # row 25 .word 0x100806, 0x0c0807, 0x0f0f0d, 0x090b08, 0x0c110d, 0x141b14, 0x373e36, 0x12150c # row 25 .word 0x0c0800, 0x8c8477, 0xd6cfbf, 0xc9c2b2, 0xdad3c1, 0xd9d2c0, 0xc9c2af, 0xd7d1bb # row 25 .word 0xdad4be, 0xd3cdb5, 0xccc6ae # row 26 .word 0xb0a47a, 0xafa379, 0xaea278, 0xada177, 0xaca076, 0xab9f75, 0xaca076, 0xaca076 # row 26 .word 0xab9f75, 0xaea278, 0xaea278, 0xafa379, 0xaea278, 0xaca076, 0xaea278, 0xb2a680 # row 26 .word 0x736848, 0x463c23, 0x2b2213, 0x180f08, 0x040000, 0x090209, 0x181118, 0x090005 # row 26 .word 0x130504, 0x1b0801, 0x2e1204, 0x512e1a, 0x744730, 0x814d35, 0x945a42, 0xb27759 # row 26 .word 0xc08960, 0xcd9769, 0xd6a072, 0xdba577, 0xd9a377, 0xc48f63, 0xb27d53, 0xb37e56 # row 26 .word 0xb7825a, 0xba845e, 0xad7552, 0x9e6643, 0x9c6441, 0x955f3d, 0x8c5634, 0x8a5535 # row 26 .word 0x774628, 0x6f4225, 0x653b22, 0x5b3520, 0x51301f, 0x472b1f, 0x3c251d, 0x33211d # row 26 .word 0x110604, 0x0b0505, 0x11100e, 0x111111, 0x0d1110, 0x111612, 0x2c322e, 0x1a1c17 # row 26 .word 0x0c0800, 0x534b40, 0xd1c9bc, 0xc0b9a9, 0xc3bcaa, 0xbeb7a5, 0xb5ae9b, 0xbab49e # row 26 .word 0xb8b29a, 0xb3ad93, 0xaea88e # row 27 .word 0xb3a77d, 0xb2a67c, 0xb1a57b, 0xb0a47a, 0xafa379, 0xafa379, 0xafa379, 0xafa379 # row 27 .word 0xaea278, 0xb0a47a, 0xada177, 0xb3a77d, 0xafa379, 0xada177, 0xb7ab81, 0xafa581 # row 27 .word 0x484125, 0x57503e, 0x322a1f, 0x0a0300, 0x130a0d, 0x14090f, 0x090001, 0x170707 # row 27 .word 0x180400, 0x311507, 0x4e2b15, 0x6e4529, 0x8c5b3b, 0x9a6241, 0xaa6d4e, 0xc18561 # row 27 .word 0xc79067, 0xd19e6f, 0xd6a374, 0xdaa778, 0xdeab7e, 0xd49f73, 0xc59064, 0xc48f63 # row 27 .word 0xbc875d, 0xc18c62, 0xb88158, 0xaa734a, 0xa87148, 0xa46a42, 0x9d633d, 0x9d663f # row 27 .word 0x9b653f, 0x8b5634, 0x7e4d2d, 0x7f5338, 0x7e5843, 0x6d4c3b, 0x4e3328, 0x35211a # row 27 .word 0x180906, 0x0f0504, 0x150f11, 0x161415, 0x0e0f11, 0x0e1213, 0x222627, 0x242623 # row 27 .word 0x1b1610, 0x2f261d, 0xe2dacf, 0xd8d0c3, 0xd7d0c0, 0xd8d1be, 0xd8d2bc, 0xd8d2ba # row 27 .word 0xddd7bd, 0xd9d3b9, 0xd6d0b6 # row 28 .word 0xb5a981, 0xb4a880, 0xb3a77f, 0xb2a67e, 0xb1a57d, 0xb1a57d, 0xb1a57d, 0xb1a57d # row 28 .word 0xafa37b, 0xb1a57d, 0xaa9e76, 0xb2a67e, 0xaea27a, 0xafa37b, 0xbbaf87, 0x9f9773 # row 28 .word 0x322c16, 0x4f4b3f, 0x37332a, 0x110906, 0x150b0c, 0x16070a, 0x0e0000, 0x1d0400 # row 28 .word 0x280b00, 0x523017, 0x744b2b, 0x875733, 0x9a653d, 0xab7048, 0xb87852, 0xc2875f # row 28 .word 0xc7966d, 0xcfa278, 0xd0a379, 0xd2a57b, 0xd8ac7f, 0xd4a579, 0xc99a6e, 0xca996e # row 28 .word 0xca9a6c, 0xce9b6e, 0xc18c60, 0xb37e52, 0xb37e52, 0xb17b4f, 0xaa7446, 0xad7447 # row 28 .word 0xae7548, 0xa1683d, 0x98623c, 0x9c6a49, 0x9a6e53, 0x835d4a, 0x5d3d30, 0x3f261f # row 28 .word 0x220f0b, 0x160808, 0x160d10, 0x181317, 0x0e0d12, 0x101417, 0x191d20, 0x2a2a2a # row 28 .word 0x110c08, 0x070000, 0xcec6bb, 0xccc4b7, 0xc9c2b2, 0xcec7b4, 0xcfc9b3, 0xcdc7af # row 28 .word 0xc4bea4, 0xc3bda3, 0xc1bba1 # row 29 .word 0xb7ab83, 0xb6aa82, 0xb5a981, 0xb4a880, 0xb3a77f, 0xb2a67e, 0xb3a77f, 0xb3a77f # row 29 .word 0xafa37b, 0xb5a981, 0xaa9e76, 0xb3a77f, 0xb0a47c, 0xb3a77f, 0xb9ad85, 0x7e7554 # row 29 .word 0x343120, 0x2f2f27, 0x3c3733, 0x2b2321, 0x0b0000, 0x1a0808, 0x361d18, 0x2d0f04 # row 29 .word 0x4a2610, 0x774e30, 0x95653f, 0x9a653b, 0xa56c3f, 0xb6794c, 0xc28256, 0xc58a60 # row 29 .word 0xcea178, 0xd3ad86, 0xd1ab84, 0xcea97f, 0xd3ac83, 0xd2a87e, 0xcba276, 0xcda277 # row 29 .word 0xd1a578, 0xd2a375, 0xc39365, 0xb38353, 0xb58253, 0xb38051, 0xad7949, 0xae7947 # row 29 .word 0xb67a48, 0xb47748, 0xb07549, 0xa9734d, 0x9c6b4d, 0x835941, 0x654131, 0x4d3126 # row 29 .word 0x27120d, 0x1b0b0b, 0x160b0f, 0x161117, 0x0d0c12, 0x18191e, 0x111217, 0x252527 # row 29 .word 0x28231f, 0x0f0600, 0xd3cac1, 0xd6cec1, 0xd4cdbd, 0xd7d0bd, 0xd0cab4, 0xcfc9b1 # row 29 .word 0xd5cfb5, 0xd5cfb5, 0xd4ceb4 # row 30 .word 0xb9ad85, 0xb8ac84, 0xb7ab83, 0xb6aa82, 0xb5a981, 0xb5a981, 0xb5a981, 0xb5a981 # row 30 .word 0xb0a47c, 0xbbaf87, 0xada179, 0xb7ab83, 0xb5a981, 0xb8ac84, 0xb1a57d, 0x554f2f # row 30 .word 0x353324, 0x20211b, 0x332f2c, 0x312726, 0x0e0000, 0x26110e, 0x5a3d35, 0x5e3a2a # row 30 .word 0x784e35, 0x936541, 0xa37045, 0xa87041, 0xb47846, 0xc18151, 0xca8a5a, 0xd0976c # row 30 .word 0xcfa881, 0xd3b591, 0xd2b18e, 0xcbab85, 0xcfad87, 0xcfae85, 0xcca97f, 0xd1ac82 # row 30 .word 0xd4aa80, 0xd6ab80, 0xc89c6f, 0xb88c5d, 0xb78958, 0xb38554, 0xac7c4b, 0xb17d4b # row 30 .word 0xbe814b, 0xc1824d, 0xbb7e4f, 0xac754c, 0x9e6c4b, 0x8a5e43, 0x684330, 0x492b20 # row 30 .word 0x28110b, 0x1d0b0b, 0x14090d, 0x150e15, 0x0f0c13, 0x202028, 0x080810, 0x19181d # row 30 .word 0x1d1815, 0x0c0300, 0xbdb4ab, 0xcbc3b8, 0xd4cdbd, 0xdcd5c2, 0xcfc9b3, 0xd2ccb4 # row 30 .word 0xcac4aa, 0xcac5a8, 0xc9c4a7 # row 31 .word 0xbcae89, 0xbbad88, 0xbaac87, 0xb9ab84, 0xb8aa83, 0xb8aa83, 0xb8aa83, 0xb8aa83 # row 31 .word 0xb1a37c, 0xbfb38b, 0xb2a680, 0xbbaf89, 0xb9ac89, 0xbcaf8c, 0xab9e7c, 0x3a3319 # row 31 .word 0x27291e, 0x232524, 0x211f20, 0x1e1413, 0x1d0b09, 0x311813, 0x614134, 0x8c6651 # row 31 .word 0x9a6d4e, 0xa3724a, 0xa77145, 0xae7645, 0xbe8250, 0xc48856, 0xce9164, 0xdaa57b # row 31 .word 0xcba580, 0xd1b391, 0xcfb18d, 0xc9a885, 0xcdad87, 0xd0ae88, 0xd1ae88, 0xd9b38c # row 31 .word 0xdcb58c, 0xe4ba90, 0xd9ae84, 0xc99e73, 0xc3976a, 0xbc9063, 0xb5895a, 0xbd8b5a # row 31 .word 0xc68a56, 0xc58651, 0xba7e4c, 0xaf7649, 0xab754f, 0x9a6b4d, 0x6d442e, 0x3b1a0b # row 31 .word 0x260d06, 0x1d0b09, 0x13080c, 0x130e14, 0x100f15, 0x25252d, 0x02020a, 0x0e0d12 # row 31 .word 0x211917, 0x130a03, 0xada49b, 0xb8b0a5, 0xbeb7a7, 0xc0b9a6, 0xa7a18b, 0xaba58b # row 31 .word 0xada78d, 0xaca78a, 0xaaa588 # row 32 .word 0xc1ae8e, 0xc0ad8d, 0xc0ad8c, 0xbfad89, 0xbcad86, 0xbcad84, 0xbbac83, 0xbbac83 # row 32 .word 0xbdae85, 0xb8aa83, 0xb6a885, 0xbaab8c, 0xc0b096, 0xcbbba2, 0x776750, 0x382f20 # row 32 .word 0x2a2c2b, 0x272c30, 0x141215, 0x1e1413, 0x130000, 0x3a1e10, 0x76533d, 0x9d7456 # row 32 .word 0xa97955, 0xab774f, 0xae784c, 0xb47e50, 0xc28c60, 0xd09b6f, 0xd7a27a, 0xd4a47c # row 32 .word 0xd1a985, 0xd8b490, 0xe1bd99, 0xddb793, 0xcda782, 0xc69e7a, 0xd0a884, 0xe0b894 # row 32 .word 0xdbb18b, 0xe1b590, 0xdcb08b, 0xcea27d, 0xc59974, 0xc49873, 0xbf936e, 0xba8a62 # row 32 .word 0xc28c5d, 0xbd8351, 0xbf8555, 0xb2784a, 0xb07950, 0x9a6543, 0x885c41, 0x3f1c08 # row 32 .word 0x270f05, 0x140502, 0x140b0e, 0x0b090e, 0x0c0d12, 0x11141b, 0x070a0f, 0x101012 # row 32 .word 0x1c1411, 0x140903, 0x81776e, 0xafa599, 0xb3aa9b, 0xb4ac99, 0xbcb6a0, 0xb1ab91 # row 32 .word 0xb1ab91, 0xb2ad90, 0xb2af90 # row 33 .word 0xc3b092, 0xc3b090, 0xc2af8e, 0xc1af8b, 0xbfb089, 0xbeaf84, 0xbdae83, 0xbdae83 # row 33 .word 0xbbae84, 0xbeb089, 0xbeb18f, 0xc1b396, 0xbeb096, 0xc8b9a4, 0x635343, 0x271d14 # row 33 .word 0x2c2d31, 0x20242d, 0x08060b, 0x160c0a, 0x140200, 0x432815, 0x7d583e, 0x976c4a # row 33 .word 0xa6744f, 0xad7951, 0xb78258, 0xc18c62, 0xc7936b, 0xc99870, 0xce9e7a, 0xd1a37f # row 33 .word 0xcda27f, 0xd4ac88, 0xd8b08c, 0xd2aa86, 0xcba07d, 0xca9f7c, 0xd2a784, 0xdbb08d # row 33 .word 0xd9ad8a, 0xd7ab88, 0xd3a685, 0xcea180, 0xca9d7c, 0xc29574, 0xb28564, 0xa57753 # row 33 .word 0xbb885d, 0xc08a5b, 0xc78f60, 0xb98152, 0xb67d52, 0xa46e48, 0x936649, 0x4a2610 # row 33 .word 0x270f03, 0x130400, 0x100a0c, 0x08070c, 0x090911, 0x0d1017, 0x04070c, 0x0e0e0e # row 33 .word 0x1b1310, 0x080000, 0x62584e, 0x9b9185, 0x978e7f, 0x958d7a, 0x8f8973, 0x857f67 # row 33 .word 0x8e886e, 0x8d886b, 0x8b876a # row 34 .word 0xc3b493, 0xc2b392, 0xc2b491, 0xc1b38c, 0xc0b389, 0xc0b387, 0xbeb386, 0xbeb386 # row 34 .word 0xb6ad82, 0xbdb48b, 0xbdb38f, 0xbfb494, 0xb4ab8e, 0xc6bca3, 0x514632, 0x1a1408 # row 34 .word 0x212226, 0x191e24, 0x070508, 0x160d08, 0x130100, 0x492e1b, 0x866147, 0x9b7050 # row 34 .word 0xab7956, 0xae7a53, 0xb6805a, 0xbd8761, 0xba8863, 0xb98965, 0xc49675, 0xd3a685 # row 34 .word 0xc89d7a, 0xd0a582, 0xd3a885, 0xcca17e, 0xc89d7a, 0xcca17e, 0xcfa482, 0xcda280 # row 34 .word 0xdeb190, 0xc69978, 0xac7f5e, 0x9c6f4e, 0x936647, 0x86593a, 0x774a2b, 0x6e401c # row 34 .word 0x87562b, 0x9b6737, 0xb1794a, 0xb0774a, 0xae754a, 0xa36f48, 0x95684b, 0x522e18 # row 34 .word 0x291105, 0x120300, 0x0e080a, 0x040509, 0x04070e, 0x080d13, 0x010409, 0x0c0c0e # row 34 .word 0x2f2a24, 0x120900, 0x6d655a, 0xc7bfb2, 0xc8c1b1, 0xccc5b2, 0xbbb59f, 0xbbb59d # row 34 .word 0xc7c1a7, 0xc5c0a3, 0xc1bda0 # row 35 .word 0xc4b795, 0xc1b793, 0xc1b891, 0xc0b78e, 0xbfb68b, 0xbeb688, 0xbeb687, 0xbcb686 # row 35 .word 0xb9b286, 0xbdb88e, 0xb6b18b, 0xbab492, 0xb1aa8d, 0xccc7aa, 0x575139, 0x191607 # row 35 .word 0x0d0e10, 0x15181f, 0x151112, 0x211612, 0x110000, 0x492c1a, 0x8f6a50, 0xa37858 # row 35 .word 0x976645, 0x8f5b36, 0x87532e, 0x844f2d, 0x7c4b2a, 0x7b4c2e, 0x8c5f42, 0xa27659 # row 35 .word 0xb38866, 0xc19673, 0xc99e7b, 0xc59a77, 0xc19673, 0xc19673, 0xbb906e, 0xb08563 # row 35 .word 0x976a49, 0x774a29, 0x582b0a, 0x4d2001, 0x4e2102, 0x512405, 0x592c0d, 0x623412 # row 35 .word 0x734219, 0x865324, 0xa16b3d, 0xb47e50, 0xb17a51, 0xa7734e, 0x9d7053, 0x69452f # row 35 .word 0x2c1408, 0x120500, 0x0c0608, 0x030409, 0x02050c, 0x050a10, 0x000209, 0x0c0d0f # row 35 .word 0x26211b, 0x0b0300, 0x6b6356, 0xded7c7, 0xe0d9c9, 0xe7e0cd, 0xd3cdb7, 0xddd7bf # row 35 .word 0xddd7bf, 0xdcd6bc, 0xdbd7bc # row 36 .word 0xc3b995, 0xc1b994, 0xc1b992, 0xc0b98f, 0xbfb88c, 0xbcb889, 0xbcb888, 0xbbb787 # row 36 .word 0xbfbb8e, 0xc0bd92, 0xb6b38a, 0xc0bc97, 0xb8b393, 0xcfcbae, 0x6a664b, 0x0f0e00 # row 36 .word 0x060805, 0x101417, 0x171312, 0x241913, 0x120000, 0x4e311f, 0x906b51, 0x95694c # row 36 .word 0x6c3b1b, 0x62300f, 0x5a2807, 0x592607, 0x542509, 0x512309, 0x572a13, 0x61351c # row 36 .word 0x8f6444, 0xa47855, 0xb68a67, 0xba8e6b, 0xb68968, 0xae8160, 0xa07352, 0x926544 # row 36 .word 0x86593a, 0x7c4f30, 0x7b4e2f, 0x86593c, 0x8e6144, 0x8f6245, 0x936649, 0x9b6d4c # row 36 .word 0x8f5f37, 0x906032, 0x9d683c, 0xb98458, 0xae794f, 0xa06e49, 0x9a6d50, 0x79553f # row 36 .word 0x30180c, 0x130600, 0x0c0608, 0x030409, 0x02050c, 0x04090f, 0x000309, 0x0f1012 # row 36 .word 0x26211b, 0x0b0500, 0x686254, 0xd0caba, 0xc4beae, 0xc5c0ac, 0xb5b09a, 0xc5c1a8 # row 36 .word 0xbab69d, 0xbcb89f, 0xbfbba2 # row 37 .word 0xc3bb97, 0xc3bb96, 0xc0bb95, 0xc0bb93, 0xbfba90, 0xbeba8d, 0xbeba8b, 0xbcba8a # row 37 .word 0xbdba8d, 0xbdba8f, 0xb5b38c, 0xc4c29c, 0xbbb897, 0xc2bea1, 0x7f7e62, 0x030200 # row 37 .word 0x0b0d0a, 0x0c0d0f, 0x0c0805, 0x1b1108, 0x140000, 0x593c2a, 0x906b51, 0x7c5033 # row 37 .word 0x643313, 0x6b3819, 0x774425, 0x865439, 0x8e5e47, 0x8b5e47, 0x7f5441, 0x754b33 # row 37 .word 0x7f5233, 0x916542, 0xa87c59, 0xb78b68, 0xb68968, 0xa97c5b, 0x986b4a, 0x8d603f # row 37 .word 0x916445, 0xa17455, 0xbd9073, 0xd3a689, 0xd4a78a, 0xc19477, 0xab7e61, 0x9e7150 # row 37 .word 0xaa7d56, 0xa17246, 0x9c693e, 0xb88359, 0xa9744c, 0xa4724d, 0xa07356, 0x86624c # row 37 .word 0x351a0f, 0x150601, 0x0b0507, 0x030409, 0x02050c, 0x030710, 0x00040a, 0x121315 # row 37 .word 0x14110a, 0x060000, 0x5f594b, 0xaea898, 0x9f9989, 0xa09b88, 0x9e9985, 0xaea993 # row 37 .word 0xbab59f, 0xbebaa1, 0xc2bea5 # row 38 .word 0xc6bd9c, 0xc6be9a, 0xc5bd99, 0xc4bc97, 0xc4bc95, 0xc1bc94, 0xc0bb91, 0xc0bb91 # row 38 .word 0xbcb990, 0xbab690, 0xb4b08b, 0xc6c29f, 0xbab798, 0xb6b295, 0xaca88d, 0x131200 # row 38 .word 0x070904, 0x050608, 0x040000, 0x140a01, 0x110000, 0x5e422d, 0x98725b, 0x7a4e33 # row 38 .word 0x815234, 0x956446, 0xab795e, 0xba8b71, 0xc79982, 0xca9d8a, 0xb88e7e, 0xa57b65 # row 38 .word 0x916445, 0x966844, 0xa87a58, 0xbe906e, 0xc49674, 0xb58765, 0xa47655, 0x9c6e4d # row 38 .word 0xa17455, 0xaf8263, 0xc09376, 0xca9d80, 0xcc9e84, 0xc89a80, 0xbe9076, 0xb48768 # row 38 .word 0xae825d, 0xae8158, 0xa6754a, 0xbf8c61, 0xb37e56, 0xbd8b66, 0xb18465, 0x87614a # row 38 .word 0x371b0f, 0x160500, 0x090303, 0x030207, 0x01040b, 0x02060f, 0x00040a, 0x151618 # row 38 .word 0x18150e, 0x110d01, 0x807d6e, 0xc1bead, 0xbebbaa, 0xc0bdaa, 0xc7c5b0, 0xcac8b1 # row 38 .word 0xc0bba5, 0xc2bda7, 0xc5c0aa # row 39 .word 0xc8bfa2, 0xc8bfa0, 0xc7be9f, 0xc7be9d, 0xc6bd9c, 0xc5bc9b, 0xc5bd99, 0xc2bc98 # row 39 .word 0xc4be9c, 0xbeba97, 0xb7b292, 0xc8c3a5, 0xbdb79d, 0xb8b49b, 0xddd8c2, 0x3c3a2b # row 39 .word 0x000100, 0x000304, 0x080401, 0x150b02, 0x0f0000, 0x5d412c, 0xa17d65, 0x8c6045 # row 39 .word 0x96674b, 0xaa795b, 0xb68469, 0xb5856e, 0xb98a76, 0xbc917e, 0xb08676, 0x9d725f # row 39 .word 0xa97a5c, 0xa3734f, 0xab7b57, 0xc29470, 0xcd9f7b, 0xbe906e, 0xac7e5c, 0xa77958 # row 39 .word 0xae7f61, 0xa37657, 0x8d6043, 0x774a2d, 0x784a30, 0x8e6046, 0xa4765c, 0xac7f60 # row 39 .word 0x966a47, 0xa77a51, 0xa4734a, 0xb9865b, 0xac774f, 0xbf8b66, 0xa37456, 0x613b24 # row 39 .word 0x381b0d, 0x150200, 0x090100, 0x020003, 0x02020a, 0x01060c, 0x00040a, 0x161719 # row 39 .word 0x040300, 0x0a0800, 0x8a867a, 0xc4c1b2, 0xc8c5b4, 0xc4c1ae, 0xc7c4b1, 0xb9b7a2 # row 39 .word 0xc6c1ad, 0xc6c1ab, 0xc7c2ae # row 40 .word 0xcdc1ab, 0xccc0aa, 0xccc0aa, 0xcbbfa7, 0xcabea6, 0xc9bfa4, 0xcac0a5, 0xc8c1a5 # row 40 .word 0xc4bda1, 0xc4bda3, 0xc4bda3, 0xc4bea6, 0xc5bfa9, 0xc6bfac, 0xc8c1af, 0xc6c2b6 # row 40 .word 0x000100, 0x141819, 0x010000, 0x0c0300, 0x100000, 0x593e2b, 0x9a765e, 0xaa8165 # row 40 .word 0x98694d, 0x9f6e50, 0xa06e53, 0x83543a, 0x582a13, 0x522714, 0x774d3d, 0x996f59 # row 40 .word 0x936544, 0x84522d, 0xb88661, 0xd1a17b, 0xe8b892, 0xca9a76, 0xa37251, 0xa17351 # row 40 .word 0x875938, 0x4f2002, 0x885b3e, 0x300300, 0x2b0000, 0x310500, 0x4f2308, 0x623717 # row 40 .word 0x9a6f4c, 0xa87d53, 0xab7a51, 0xaa774c, 0xa77248, 0x8c5831, 0x7f4e2e, 0x8e664d # row 40 .word 0x472718, 0x140000, 0x140907, 0x030000, 0x05040a, 0x05080d, 0x070a0f, 0x101113 # row 40 .word 0x0d0c07, 0x010100, 0xb1afa3, 0xc8c6b9, 0xc3c1b2, 0xd1d0be, 0xbab7a4, 0xc3c1ac # row 40 .word 0xc0bea9, 0xc1bfaa, 0xc4bfac # row 41 .word 0xb0a496, 0xafa395, 0xaea294, 0xada191, 0xada191, 0xada290, 0xaba291, 0xaba390 # row 41 .word 0xaca593, 0xaca593, 0xaca593, 0xaca595, 0xaca698, 0xada799, 0xaea89c, 0xaca9a0 # row 41 .word 0x8b9191, 0x000104, 0x11110f, 0x221b13, 0x0d0000, 0x8b725e, 0x300e00, 0x92694d # row 41 .word 0x9d6e50, 0x885739, 0x613012, 0x6a381d, 0x340600, 0x3d1000, 0x390e00, 0x582b14 # row 41 .word 0xa77753, 0xa27148, 0xc29168, 0xe7b68e, 0xf3c29a, 0xbc8c66, 0xb3835f, 0xb88766 # row 41 .word 0x8d5f3d, 0x7a4c2b, 0xb18465, 0x74472a, 0x764a2d, 0x794d32, 0x7a4e33, 0x6f4424 # row 41 .word 0xc29872, 0xd8ad83, 0xd6a57c, 0xc48f65, 0xc18a61, 0xb9845c, 0xaa7857, 0xa67a5f # row 41 .word 0x4a2916, 0x160000, 0x160805, 0x0b0505, 0x070508, 0x0a0b0f, 0x0b0c10, 0x0f1012 # row 41 .word 0x0b0c07, 0x0e0e06, 0xb2b2aa, 0xc6c6ba, 0xbebcaf, 0xb5b3a4, 0xc4c1b0, 0xc0bdaa # row 41 .word 0xc0bdaa, 0xc1bfaa, 0xc4bfac # row 42 .word 0x2d241f, 0x2d241d, 0x2c231c, 0x2b221b, 0x2a211a, 0x2a2118, 0x2a231b, 0x2a2319 # row 42 .word 0x2a261d, 0x29251c, 0x29251c, 0x28241b, 0x27241d, 0x28251e, 0x29261f, 0x262722 # row 42 .word 0x1e282a, 0x121b20, 0x000100, 0x58554e, 0x9c8e81, 0xbba492, 0x9e7c63, 0xa67d61 # row 42 .word 0x9b6c4e, 0x774625, 0x5b2908, 0x855434, 0x794a2c, 0x906248, 0x966952, 0xb98c6f # row 42 .word 0xd4a27d, 0xb8855a, 0xaf7c51, 0xddac81, 0xf3c299, 0xb8875f, 0xc19169, 0xc4946e # row 42 .word 0xa27450, 0x936543, 0xb78a69, 0xbf9273, 0xcca181, 0xaf8366, 0xa07457, 0xa37858 # row 42 .word 0xa87e58, 0xb88d63, 0xb8875c, 0xaf7a4e, 0xb57c51, 0xb27b52, 0xa26e49, 0x936649 # row 42 .word 0x58341e, 0x1c0200, 0x150400, 0x1a100f, 0x090506, 0x0e0e10, 0x0f0f11, 0x0c0d0f # row 42 .word 0x080808, 0x13140f, 0x1a1b16, 0x181911, 0x0f0f05, 0x010100, 0xc9c7b8, 0xc7c6b4 # row 42 .word 0xc0bdaa, 0xc0bdaa, 0xc3beaa # row 43 .word 0x514d4e, 0x514d4e, 0x504c4d, 0x4f4b4a, 0x4e4a4b, 0x4c4b49, 0x4d4b4c, 0x4c4c4a # row 43 .word 0x4d4d4d, 0x4d4d4b, 0x4c4c4a, 0x4a4c49, 0x494b4a, 0x494b4a, 0x4a4c4b, 0x474c4f # row 43 .word 0x48555b, 0x4f5c62, 0x161b1e, 0x030200, 0x0a0000, 0x7e6956, 0x3b1b02, 0x9d7657 # row 43 .word 0xa17453, 0x8d5d39, 0xa16f4a, 0xb07e5b, 0xb07f5e, 0x8a5c3b, 0x8a5d40, 0x8e603f # row 43 .word 0xdba77f, 0xae7a4b, 0xa77344, 0xd6a376, 0xeebb90, 0xb4835a, 0xb7865d, 0xc4946c # row 43 .word 0xc59871, 0xa87a56, 0x8c603d, 0x936645, 0x956a48, 0x815636, 0x8d6242, 0xab805e # row 43 .word 0xb48a64, 0xaf8259, 0xb58257, 0xc69062, 0xcf9468, 0xbe8359, 0xa9714c, 0xa17050 # row 43 .word 0x724933, 0x290c00, 0x110000, 0x1e130f, 0x0d0805, 0x0f0e0c, 0x110f10, 0x090909 # row 43 .word 0x07080a, 0x131514, 0x444442, 0x33342f, 0x2d2d25, 0x18180e, 0xc3c1b4, 0xbcbaab # row 43 .word 0xbfbcab, 0xc0bdaa, 0xc3beaa # row 44 .word 0x42464f, 0x41454e, 0x40444d, 0x3f444a, 0x3f434c, 0x3d444a, 0x3d444c, 0x3e454b # row 44 .word 0x414850, 0x40494e, 0x3f484d, 0x3d464b, 0x3d464b, 0x3b464a, 0x3c4749, 0x3a474d # row 44 .word 0x374852, 0x2c3d45, 0x3f484d, 0x131311, 0x190f05, 0x3a2716, 0x72543a, 0x997253 # row 44 .word 0xb0845f, 0x9e6d45, 0xa57149, 0x925e36, 0x98673f, 0x95653f, 0xc1916d, 0xd2a27c # row 44 .word 0xbb8758, 0x9c6836, 0xc49060, 0xe4b281, 0xe9b687, 0xb08052, 0xa37247, 0xc8996f # row 44 .word 0xd2a57c, 0xe4b790, 0xc39772, 0xaf8360, 0xa87d5a, 0xb78c6a, 0xc49c79, 0xc29774 # row 44 .word 0xcaa078, 0xbb8e64, 0xbc895c, 0xca9164, 0xcb8e5f, 0xba7d50, 0xa66c44, 0x976542 # row 44 .word 0x8d634a, 0x3a1b07, 0x120000, 0x1f1009, 0x1b110f, 0x0f0a07, 0x140e0e, 0x090708 # row 44 .word 0x1f2024, 0x3b3f42, 0x353638, 0x3c3e3b, 0x383933, 0x080901, 0xdeded2, 0xbab8a9 # row 44 .word 0xbfbcab, 0xc0bdaa, 0xc3beaa # row 45 .word 0x162230, 0x15212d, 0x14202e, 0x131f2b, 0x12202d, 0x12202d, 0x12202d, 0x13212e # row 45 .word 0x12222f, 0x12232d, 0x11222c, 0x102129, 0x0e2128, 0x0e2128, 0x0e2128, 0x0e2128 # row 45 .word 0x0a1d2b, 0x20323e, 0x071218, 0x070908, 0x070000, 0x4d3a29, 0xa4866c, 0xd1aa89 # row 45 .word 0xb68a63, 0xbc8b62, 0xbb885d, 0xbc875b, 0xb07d52, 0xbf8e63, 0xc6956c, 0xc39267 # row 45 .word 0xc08c5a, 0xa26d39, 0xcf9a66, 0xdfab79, 0xe8b484, 0xc28f60, 0xab7b4d, 0xcc9b70 # row 45 .word 0xc7986e, 0xe5b88f, 0xeec29b, 0xeabe99, 0xdeb48e, 0xe2b794, 0xe1b996, 0xd1a683 # row 45 .word 0xd7ab84, 0xd2a379, 0xcd986c, 0xc38b5c, 0xbd7f50, 0xc28455, 0xb87d53, 0x9c6642 # row 45 .word 0x9c7055, 0x4e2b17, 0x1e0700, 0x23120a, 0x332822, 0x0d0502, 0x140c0a, 0x0e0a09 # row 45 .word 0x222328, 0x0d1017, 0x2f3034, 0x1c1d1f, 0x1d1d1b, 0x21221a, 0xbdbdb1, 0xc1c2b2 # row 45 .word 0xbfbcab, 0xbfbda8, 0xc2bda7 # row 46 .word 0xd7eafb, 0xd6e9f8, 0xd5e8f9, 0xd4e7f6, 0xd2e7f8, 0xd2e7f8, 0xd3e8f9, 0xd3e8f9 # row 46 .word 0xd1e8f8, 0xd1e8f6, 0xd0e7f5, 0xcfe7f3, 0xcde8f3, 0xcde8f1, 0xcee9f2, 0xcee9f4 # row 46 .word 0xd0e7f5, 0xe0f3ff, 0xa4b1b9, 0x393d3e, 0x0e0700, 0x3c2b1b, 0x9c8166, 0xb08c6a # row 46 .word 0xe6ba93, 0xe4b388, 0xdeaa7b, 0xd4a070, 0xc89464, 0xd29f70, 0xd7a477, 0xce9b6c # row 46 .word 0xc8935f, 0xb37e48, 0xc7925c, 0xdaa772, 0xeeba88, 0xce9c6b, 0xbb8b5b, 0xb9895b # row 46 .word 0xddae82, 0xd7aa80, 0xefc49a, 0xeec29b, 0xdeb48e, 0xd7ad87, 0xdfb793, 0xe0b690 # row 46 .word 0xc69a73, 0xc19268, 0xc49061, 0xbd8353, 0xb37343, 0xba7a4c, 0xb87b4f, 0x9b633e # row 46 .word 0x9a6b4f, 0x5b3721, 0x351b0c, 0x2f1d13, 0x534640, 0x0a0100, 0x120a07, 0x14100f # row 46 .word 0x0e0f14, 0x10131c, 0x0a0d14, 0x292d30, 0x282a29, 0x1b1c16, 0xccccc2, 0xbabbad # row 46 .word 0xbebbaa, 0xbfbda8, 0xc2bda7 # row 47 .word 0xdaeaf9, 0xdaeaf9, 0xd9e9f8, 0xd7e9f7, 0xd7e9f7, 0xd6e9f7, 0xd6e9f8, 0xd6e9f8 # row 47 .word 0xd7edfb, 0xd7edfa, 0xd6ecf9, 0xd5edf9, 0xd5edf7, 0xd4eff8, 0xd4eff8, 0xd7eff9 # row 47 .word 0xdaf0fe, 0xcde0ee, 0xeafbff, 0xa2acad, 0x100d06, 0x655545, 0x9e8068, 0xb78c6c # row 47 .word 0xc19068, 0xbc865a, 0xdba374, 0xc18c5a, 0xd49e6f, 0xbc8859, 0xd69f76, 0xc79165 # row 47 .word 0xa8703f, 0xbd8650, 0xd59d6a, 0xf3be8c, 0xfbc596, 0xc49060, 0xbc8859, 0x9f6c3f # row 47 .word 0x956237, 0xa37249, 0xe6b58d, 0xe6b690, 0xe3b38f, 0xf0bf9e, 0xf2c4a2, 0xd7a783 # row 47 .word 0xd09e79, 0xbf8b63, 0xc99367, 0xd59d6e, 0xc6895a, 0xb77a4b, 0xb4774b, 0xa76d47 # row 47 .word 0x956243, 0x673a23, 0x4b2a19, 0x3e261a, 0x6b5a53, 0x080000, 0x0f0a07, 0x171516 # row 47 .word 0x22222a, 0x151821, 0x0a0d14, 0x27282c, 0x1b1d1c, 0x1b1c16, 0xc0c0b6, 0xc0beaf # row 47 .word 0xbebba8, 0xc1bca8, 0xc2bda7 # row 48 .word 0xf9fcff, 0xf9fcff, 0xf9fcff, 0xf7fcff, 0xf7fbff, 0xf4fbff, 0xf3fcff, 0xf3fcff # row 48 .word 0xeffaff, 0xf0fdff, 0xf1feff, 0xedfcff, 0xedfcff, 0xeeffff, 0xefffff, 0xedfeff # row 48 .word 0xedfbff, 0xf2ffff, 0xeeffff, 0xe8f8f7, 0xc4c9c2, 0x887c6e, 0x94705a, 0xb37d61 # row 48 .word 0xbf7f5b, 0xd59268, 0xd49667, 0xc68c5c, 0xce986c, 0xdca57e, 0xc18465, 0x905130 # row 48 .word 0xb57a50, 0xb17749, 0xd3986c, 0xeeb588, 0xf5bc91, 0xcd9469, 0xa76d45, 0xd09670 # row 48 .word 0xc18762, 0xb67b59, 0xab704e, 0xd19676, 0xf1b698, 0xeaae92, 0xdfa387, 0xdea385 # row 48 .word 0xd29576, 0xca8e6a, 0xc68c64, 0xc48e60, 0xbc8657, 0xab7546, 0xa36d3e, 0xa66d42 # row 48 .word 0xa06543, 0x6b3519, 0x62331f, 0x815d4f, 0x372018, 0x0d0400, 0x141613, 0x1b2023 # row 48 .word 0x14191f, 0x13161d, 0x12151a, 0x202221, 0x20211c, 0x17170d, 0xcdc9bd, 0xc2bcac # row 48 .word 0xc0bba7, 0xc2bca6, 0xc3bda5 # row 49 .word 0xf6f1f5, 0xf6f1f5, 0xf4f2f5, 0xf3f1f4, 0xf2f1f6, 0xf0f1f5, 0xf0f1f5, 0xeef2f5 # row 49 .word 0xe9eef2, 0xf0f8fb, 0xf4fdff, 0xf2fbff, 0xf0fbff, 0xf4ffff, 0xf5ffff, 0xf5ffff # row 49 .word 0xf0faff, 0xeefcff, 0xf0ffff, 0xf1ffff, 0xf7fff8, 0xb5ac9d, 0x946f5c, 0x9d6449 # row 49 .word 0xd08a68, 0xd28960, 0xda976a, 0xe1a477, 0xcd966d, 0xab7350, 0x9f5d43, 0xa26046 # row 49 .word 0xcc906b, 0xba8156, 0xd29870, 0xecb28a, 0xe8ae86, 0xbf855f, 0xb87c57, 0xfec29e # row 49 .word 0xe2a684, 0xa56947, 0x844526, 0x915233, 0xca8a6e, 0xe4a489, 0xe3a388, 0xda9a7e # row 49 .word 0xd49375, 0xce8e6b, 0xc48a64, 0xbe895d, 0xb78455, 0xab7948, 0xa36f3f, 0xa36a3f # row 49 .word 0x985c38, 0x814529, 0x5f2b16, 0x82584a, 0x2b120b, 0x070000, 0x1b1f1e, 0x121c1e # row 49 .word 0x12191f, 0x12171d, 0x141519, 0x202221, 0x21201b, 0x19160d, 0xcdcabb, 0xc2bdaa # row 49 .word 0xc1baa7, 0xc2bca6, 0xc3bda5 # row 50 .word 0xfefcff, 0xfefcff, 0xfefcff, 0xfefcff, 0xfcfbff, 0xfbfcff, 0xfbfcff, 0xf9fdff # row 50 .word 0xf9feff, 0xf9ffff, 0xf4feff, 0xe1ebed, 0xcad5d9, 0xbdc8cc, 0xb9c4c8, 0xb8c3c9 # row 50 .word 0xd3dbe6, 0xb8c5ce, 0xaec3c6, 0xaabebc, 0xcfdbd1, 0xb6af9f, 0x8d6a56, 0xae765d # row 50 .word 0xc88161, 0xc67e56, 0xd19165, 0xdaa072, 0xb57e55, 0x834b28, 0x8c4a30, 0xb27257 # row 50 .word 0xcf9570, 0xc38e64, 0xc59068, 0xc69169, 0xcb966e, 0xc58f69, 0xbd8761, 0xd8a27e # row 50 .word 0xdba380, 0xa46c4b, 0xb37b5a, 0x9e6645, 0xaa7153, 0xba8163, 0xcc9375, 0xc88d6f # row 50 .word 0xce8f70, 0xca8b68, 0xc08660, 0xb58054, 0xb17e4f, 0xae7c4b, 0xa67243, 0x9d673b # row 50 .word 0x9b613c, 0x935a3d, 0x63301b, 0x70493a, 0x5a413a, 0x080000, 0x171b1a, 0x0a1416 # row 50 .word 0x12191f, 0x12171d, 0x141519, 0x202221, 0x21201b, 0x18150c, 0xcdcabb, 0xc2bdaa # row 50 .word 0xc1baa7, 0xc1bba5, 0xc2bca4 # row 51 .word 0xe9e7ea, 0xe9e7ea, 0xe9e7ea, 0xe9e7ea, 0xe8e7ec, 0xe8e7ec, 0xe6e7eb, 0xe4e8eb # row 51 .word 0xdce1e5, 0xe3e8ec, 0xe3ebee, 0xdee8ea, 0xdae3e8, 0xdbe6ea, 0xe0ebef, 0xe3ecf3 # row 51 .word 0xe2eaf5, 0xd2dfe8, 0xcadfe2, 0xc9dddb, 0xdbe7dd, 0xd1c9bc, 0x795643, 0xa36d53 # row 51 .word 0xb06b4c, 0xc07852, 0xc38458, 0xb57b4d, 0x9b643b, 0x915936, 0xa5654a, 0xbb7b60 # row 51 .word 0xa16b49, 0x9a6941, 0x9a6843, 0x9d6b46, 0xa3714c, 0x9e6c47, 0x8b5934, 0x83512e # row 51 .word 0x925d3b, 0x693412, 0xe1ac8a, 0xd09b79, 0x8f5a3a, 0x976242, 0xce9979, 0xb57f5d # row 51 .word 0xc38765, 0xc48562, 0xb97f59, 0xac774b, 0xac794a, 0xb07d4e, 0xa97546, 0x9b643b # row 51 .word 0xa46c49, 0x8f593d, 0x754531, 0x906a5d, 0x58413b, 0x120a07, 0x121617, 0x091315 # row 51 .word 0x11181e, 0x11161c, 0x131418, 0x1f2120, 0x201f1a, 0x18150c, 0xccc9ba, 0xc2bdaa # row 51 .word 0xc0b9a6, 0xc1bba5, 0xc2bca4 # row 52 .word 0xfcfafb, 0xfcfafb, 0xfdfbfe, 0xfdfbfe, 0xfcfcfe, 0xfcfcfe, 0xfbfcff, 0xf9fdff # row 52 .word 0xfbffff, 0xfbffff, 0xf8ffff, 0xf2fcfe, 0xf2fcfe, 0xf6ffff, 0xf6ffff, 0xf2fbff # row 52 .word 0xf5fcff, 0xf7ffff, 0xf1ffff, 0xf1ffff, 0xf8fffb, 0xfbf5e7, 0x735241, 0x905c44 # row 52 .word 0xa46345, 0xba7651, 0xb6794d, 0xa0673a, 0x9f6a40, 0xb8805d, 0xc48469, 0xb6765d # row 52 .word 0x612c0c, 0x4e1d00, 0x5b2a09, 0x7e4d2c, 0x744322, 0x4c1b00, 0x4c1b00, 0x663514 # row 52 .word 0x6e3d1c, 0xa06f4e, 0xcf9f7b, 0x9d6d49, 0xca9a76, 0xac7c58, 0x8e5e3a, 0xc6916f # row 52 .word 0xbb805e, 0xbb7f5b, 0xb37953, 0xa87347, 0xaa7748, 0xb07d4e, 0xaa7549, 0x9c673f # row 52 .word 0xa06a48, 0x835035, 0x805340, 0x977569, 0x0e0000, 0x1e1614, 0x14181b, 0x10191e # row 52 .word 0x111820, 0x11161c, 0x131418, 0x1f2120, 0x201f1a, 0x17140b, 0xccc9ba, 0xc1bca9 # row 52 .word 0xc0b9a6, 0xc1bba5, 0xc2bca4 # row 53 .word 0xfbf9fa, 0xfbf9fa, 0xfcfafd, 0xfcfafd, 0xfbfbfd, 0xfcfcfe, 0xfbfcff, 0xfbfcff # row 53 .word 0xf8fcff, 0xf5fafd, 0xf1f6fa, 0xedf5f8, 0xf2fafd, 0xf8ffff, 0xf8ffff, 0xf5fcff # row 53 .word 0xedf1fc, 0xeef7ff, 0xdaedf1, 0xeeffff, 0xebf8ef, 0xfffff3, 0x886859, 0x905d48 # row 53 .word 0xa8684c, 0xaf6d4a, 0xaa6f43, 0xa77143, 0xb27f54, 0xc28a65, 0xbf7f63, 0xad6d54 # row 53 .word 0x865034, 0x744325, 0x774628, 0x946345, 0x8f5e40, 0x815030, 0x9a6949, 0xaa7c5a # row 53 .word 0xb38261, 0xb08260, 0xcea07c, 0xb58763, 0xc99b77, 0xbb8d69, 0xa87a56, 0xad7b56 # row 53 .word 0xb97f5a, 0xb87c58, 0xb27852, 0xad764d, 0xad784c, 0xae794d, 0xa87349, 0x9f6b44 # row 53 .word 0x936140, 0x8e5f45, 0x764d3b, 0x290b00, 0x0e0000, 0x211b1b, 0x0c0f14, 0x11181e # row 53 .word 0x131720, 0x11161c, 0x131418, 0x1f2120, 0x201f1a, 0x17140b, 0xcbc8b9, 0xc1bca9 # row 53 .word 0xc0b9a6, 0xc0baa4, 0xc1bba3 # row 54 .word 0xfbf9fa, 0xfbf9fa, 0xfafafa, 0xfbfbfb, 0xfbfbfd, 0xfcfcfe, 0xfbfcfe, 0xfbfcfe # row 54 .word 0xfcffff, 0xfbffff, 0xf7fcff, 0xf1f6f9, 0xeff4f8, 0xf0f8fb, 0xf0f8fb, 0xecf3f9 # row 54 .word 0xf5f8ff, 0xf6fdff, 0xecfeff, 0xedffff, 0xf4fffa, 0xfffff4, 0x9f8375, 0x855642 # row 54 .word 0xa76b4f, 0xa86946, 0xa97347, 0xb17e4f, 0xb58257, 0xb07a54, 0xb27354, 0xb47459 # row 54 .word 0xa66e55, 0xa57159, 0x9a674c, 0x9c694e, 0x9b684d, 0xb17e61, 0xd7a487, 0xc99878 # row 54 .word 0xb88665, 0xb98867, 0xb98965, 0xb2825e, 0xc0906a, 0xb78761, 0xb3835d, 0xbd8c64 # row 54 .word 0xbc845f, 0xb97f5a, 0xb57e57, 0xb57e55, 0xb37c53, 0xab764c, 0xa57048, 0xa06e49 # row 54 .word 0x8f6042, 0x976d55, 0x6c4838, 0x120000, 0x31221f, 0x1c1819, 0x090c11, 0x0e151d # row 54 .word 0x12161f, 0x10151b, 0x121317, 0x1e201f, 0x1f1e19, 0x17140b, 0xcbc8b9, 0xc1bca9 # row 54 .word 0xbfb8a5, 0xc0baa4, 0xc1bba3 # row 55 .word 0xfdfbfc, 0xfdfbfc, 0xfcfcfc, 0xfdfdfd, 0xfdfdff, 0xfefeff, 0xfdfeff, 0xfdfeff # row 55 .word 0xf7fbfe, 0xfafeff, 0xf9fdff, 0xf1f6f9, 0xeef3f7, 0xf2f7fb, 0xf6fbff, 0xf7fcff # row 55 .word 0xf4f4fc, 0xf1f5fe, 0xeafcfe, 0xcce0df, 0xd9e8e3, 0xe4e4da, 0xb1968b, 0x926454 # row 55 .word 0xa66c54, 0xae7250, 0xb47f55, 0xb58557, 0xaa794e, 0xa46f47, 0xb57655, 0xca886e # row 55 .word 0xc58873, 0xc88f7b, 0xc68d79, 0xcb937c, 0xb37b64, 0xb27a61, 0xe3ab90, 0xeab596 # row 55 .word 0xd9a485, 0xdba686, 0xb2805d, 0xa77550, 0xb07e59, 0xa8774f, 0xae7d55, 0xc8946d # row 55 .word 0xc08a64, 0xba825d, 0xb9825b, 0xbd865f, 0xb78059, 0xaa734c, 0xa16d46, 0xa0704c # row 55 .word 0x916548, 0x89654d, 0x6c4f3f, 0x7e6a61, 0x0e0301, 0x131114, 0x171a21, 0x10171f # row 55 .word 0x12161f, 0x10151b, 0x121317, 0x1e201f, 0x1f1e19, 0x17140b, 0xcbc8b9, 0xc0bba8 # row 55 .word 0xbfb8a5, 0xc0baa4, 0xc1bba3 # row 56 .word 0xfafaf8, 0xfafaf8, 0xf9f9f7, 0xfafaf8, 0xfbfbfb, 0xfcfcfc, 0xfcfdff, 0xfdfeff # row 56 .word 0xf8f9fb, 0xfbfcfe, 0xfbfcff, 0xf5f9fc, 0xf6fafd, 0xfafeff, 0xfbffff, 0xf8fbff # row 56 .word 0xefeef6, 0xf9fcff, 0xf1ffff, 0xaabebd, 0xc2d1cc, 0xc8c9c1, 0xc6aea4, 0x845a4a # row 56 .word 0xa8725a, 0x9f6648, 0xbd8c63, 0xbc8d61, 0x86572b, 0x99653d, 0xd19271, 0xcd8c70 # row 56 .word 0xc4836f, 0xa76856, 0xb0715f, 0xc0826d, 0xc48671, 0xb47860, 0xa4684e, 0xb67a5e # row 56 .word 0xb98063, 0xd69d7f, 0xd09877, 0xbc8461, 0xb57f5b, 0xa46e48, 0xa36d47, 0xc28d65 # row 56 .word 0xc38d67, 0xc28c66, 0xc08962, 0xba835c, 0xb37953, 0xa9714c, 0xa06b49, 0x986a49 # row 56 .word 0x865e44, 0x84644f, 0xa0897b, 0x93847d, 0x0a0200, 0x0e0d12, 0x0f121b, 0x181c27 # row 56 .word 0x12161f, 0x11161c, 0x121317, 0x1c1e1d, 0x1e1d18, 0x1a170e, 0xcdcabb, 0xbeb9a6 # row 56 .word 0xbeb7a4, 0xbfb9a3, 0xc0baa2 # row 57 .word 0xfbfbf9, 0xfbfbf9, 0xfbfbf9, 0xfbfbf9, 0xfcfcfc, 0xfdfdfd, 0xfdfeff, 0xfeffff # row 57 .word 0xf8f9fb, 0xfbfcfe, 0xfbfcff, 0xf7f8fc, 0xf8f9fd, 0xfafeff, 0xfdfeff, 0xfafbff # row 57 .word 0xfffdff, 0xf7faff, 0xd5e4e7, 0x9db1b0, 0xd7e7e4, 0xf3f6ef, 0xdac6bd, 0x795346 # row 57 .word 0x915e49, 0xbb8667, 0xbe8e66, 0x996d40, 0x9d7144, 0x824e26, 0x7a3b18, 0x813e23 # row 57 .word 0x793522, 0x712e1d, 0x823f2e, 0x8a4734, 0x8e4b38, 0x894832, 0x73331a, 0x703317 # row 57 .word 0x85482b, 0x804525, 0x753a18, 0x7f4422, 0x995f3a, 0x9f6742, 0xa9724b, 0xc48f67 # row 57 .word 0xc08c65, 0xbc8861, 0xb7825a, 0xb47d56, 0xb17752, 0xa9714e, 0xa16c4c, 0x96694a # row 57 .word 0x88644a, 0x6f543f, 0xd8c6b8, 0x827771, 0x060201, 0x17181d, 0x11131f, 0x0e121e # row 57 .word 0x121621, 0x11161c, 0x121317, 0x1c1e1d, 0x1e1d18, 0x19160d, 0xcdcabb, 0xbeb9a6 # row 57 .word 0xbeb7a4, 0xbfb9a3, 0xc0baa2 # row 58 .word 0xfcfcfa, 0xfcfcfa, 0xfcfcfa, 0xfcfcfa, 0xfdfdfb, 0xfefefc, 0xffffff, 0xffffff # row 58 .word 0xf9f9fb, 0xfcfcfe, 0xfcfcfe, 0xf8f8fa, 0xf9f8fd, 0xfcfdff, 0xfefdff, 0xfbfaff # row 58 .word 0xfcf7fd, 0xfeffff, 0xdbebeb, 0x6f8382, 0x5b6b68, 0x6a6f69, 0x92817a, 0x826054 # row 58 .word 0x976854, 0xac7b5d, 0xb1855e, 0xaf8459, 0x9b6f42, 0x7d4921, 0x733411, 0x854225 # row 58 .word 0x9d5642, 0x9d5644, 0xa35c4a, 0x94503d, 0x995540, 0xaa6850, 0xa26048, 0x9c5c41 # row 58 .word 0x955539, 0x7d4021, 0x793d1b, 0x945937, 0xb07651, 0xb97f59, 0xc18a63, 0xd19c74 # row 58 .word 0xbb8a61, 0xb4835a, 0xaf7953, 0xad7550, 0xaf7452, 0xaa7251, 0xa06b4c, 0x91654a # row 58 .word 0x84644d, 0x604937, 0xfff8ec, 0x736e68, 0x060606, 0x161920, 0x0c101c, 0x0f1221 # row 58 .word 0x111520, 0x11161c, 0x121317, 0x1c1e1d, 0x1e1d18, 0x19160d, 0xccc9ba, 0xbdb8a5 # row 58 .word 0xbeb7a4, 0xbeb8a2, 0xbfb9a1 # row 59 .word 0xfbfbf9, 0xfbfbf9, 0xfbfbf9, 0xfbfbf9, 0xfcfcfa, 0xfefefc, 0xffffff, 0xffffff # row 59 .word 0xf9f9fb, 0xfcfcfe, 0xfcfcfe, 0xf8f8fa, 0xf9f8fd, 0xfdfcff, 0xfefdff, 0xfcfaff # row 59 .word 0xfcf5fc, 0xfefdff, 0xf5ffff, 0xdaeeed, 0xf2ffff, 0xfbfffd, 0xf9eae5, 0xd2b2a7 # row 59 .word 0x825746, 0x9b6c50, 0xad835d, 0xc9a074, 0x92673a, 0xa06f44, 0xa76b46, 0xb77555 # row 59 .word 0xb36c56, 0xc07965, 0xd48d79, 0xcd8974, 0xd28e77, 0xdc9a80, 0xc9876d, 0xba7a5e # row 59 .word 0xb37657, 0xad714f, 0xbb805e, 0xce946f, 0xc9926b, 0xc08962, 0xc08b63, 0xc18d65 # row 59 .word 0xb5865c, 0xb07f56, 0xac7650, 0xaf7550, 0xb27654, 0xac7153, 0x9b684b, 0x895f46 # row 59 .word 0x785944, 0x7a6957, 0xfff8ed, 0x72716c, 0x07080c, 0x0b0f18, 0x070a19, 0x1a1d2c # row 59 .word 0x111520, 0x11161c, 0x111216, 0x1b1d1c, 0x1e1d18, 0x19160d, 0xccc9ba, 0xbdb8a5 # row 59 .word 0xbdb6a3, 0xbeb8a2, 0xbfb9a1 # row 60 .word 0xf9fbf6, 0xf9fbf6, 0xfafbf6, 0xfafbf6, 0xfbfbf9, 0xfcfcfa, 0xfdfdfd, 0xfefefe # row 60 .word 0xf9f9f9, 0xfcfcfc, 0xfdfbfe, 0xf9f7fa, 0xfaf8fb, 0xfefcff, 0xfffdff, 0xfcfafd # row 60 .word 0xfffdff, 0xfffeff, 0xf5ffff, 0xeafefd, 0xf1ffff, 0xf3f9f7, 0xfff9f6, 0xfff1e7 # row 60 .word 0x6e4434, 0x996b51, 0xab845d, 0xae885b, 0xac8154, 0xb9885d, 0xb57a52, 0xac6a48 # row 60 .word 0xa76449, 0xa7654d, 0xb7755d, 0xb6765b, 0xba7a5f, 0xbf8265, 0xb27558, 0xb07555 # row 60 .word 0xb17958, 0xbf8764, 0xd19b77, 0xd39d77, 0xc38f67, 0xbd8961, 0xba8960, 0xb28359 # row 60 .word 0xaf8258, 0xae7f55, 0xaf7953, 0xb37856, 0xb37657, 0xaa6e52, 0x976449, 0x855b43 # row 60 .word 0x6d523d, 0xc2b2a3, 0xf3efe4, 0x767873, 0x000307, 0x090d18, 0x0d101f, 0x18192b # row 60 .word 0x111520, 0x10151b, 0x111216, 0x1b1d1c, 0x1d1c17, 0x18150c, 0xccc9ba, 0xbdb8a5 # row 60 .word 0xbdb6a3, 0xbeb8a2, 0xbfb9a1 # row 61 .word 0xf9fbf6, 0xf8faf5, 0xf9faf5, 0xfafbf6, 0xfafaf8, 0xfcfcfa, 0xfdfdfd, 0xfefefe # row 61 .word 0xf9f9f9, 0xfcfcfc, 0xfdfbfe, 0xf9f7fa, 0xfaf8fb, 0xfefcff, 0xfffdff, 0xfef9fd # row 61 .word 0xfff7fc, 0xf4f2f5, 0xeefafa, 0xefffff, 0xf2ffff, 0xf8fffe, 0xfffbf8, 0xfff7ef # row 61 .word 0xbf9887, 0x80543b, 0x946e49, 0xa37e52, 0xc49b6d, 0xa47348, 0xb77c54, 0x9c5a37 # row 61 .word 0xb27153, 0x9e5e42, 0x995c3f, 0x8f5235, 0x915638, 0xa06545, 0xa56d4c, 0xb9835f # row 61 .word 0xb47e5a, 0xbe8a63, 0xbe8d65, 0xb6865e, 0xb98a60, 0xc19268, 0xbd9066, 0xb5885e # row 61 .word 0xa87d52, 0xad7e54, 0xb37d57, 0xb67a58, 0xb17253, 0xa4684c, 0x946048, 0x865d47 # row 61 .word 0x705743, 0xe7dbcb, 0xfbf8ef, 0x737874, 0x000205, 0x0e151f, 0x181b2c, 0x090a1c # row 61 .word 0x10141f, 0x10151b, 0x111216, 0x1a1c1b, 0x1d1c17, 0x18150c, 0xcbc8b9, 0xbcb7a4 # row 61 .word 0xbdb6a3, 0xbdb7a1, 0xbeb8a0 # row 62 .word 0xf9fbf6, 0xf9fbf6, 0xfafbf6, 0xfbfcf7, 0xfbfbf9, 0xfdfdfb, 0xfefefc, 0xfffffd # row 62 .word 0xfaf8f9, 0xfdfbfc, 0xfdfbfc, 0xf9f7f8, 0xfaf8fb, 0xfefcff, 0xfffcff, 0xfef9fd # row 62 .word 0xfff8fb, 0xfffdff, 0xf6ffff, 0xecffff, 0xe7f9f9, 0xedf6f5, 0xfff4f2, 0xfff5ee # row 62 .word 0xfff6e6, 0x946a51, 0x7e5833, 0xa78256, 0xbc9365, 0xa07143, 0xbb7d56, 0xb06e4b # row 62 .word 0xa66a48, 0x9e6343, 0xa36b4a, 0x9d6544, 0x9d6745, 0xa7714d, 0xa26e49, 0xab7a52 # row 62 .word 0xb4835b, 0xba8a62, 0xad8057, 0xaa7f54, 0xbd9267, 0xbb9266, 0xaa8155, 0xa77e52 # row 62 .word 0xa1764b, 0xab7c52, 0xb57f59, 0xb47856, 0xaa6b4c, 0x9e6145, 0x956149, 0x8f6652 # row 62 .word 0x795f4e, 0xb0a798, 0xfffff8, 0x6a706e, 0x00040a, 0x0e1420, 0x181b2e, 0x060719 # row 62 .word 0x10141f, 0x10151b, 0x101115, 0x1a1c1b, 0x1d1c17, 0x18150c, 0xcbc8b9, 0xbcb7a4 # row 62 .word 0xbcb5a2, 0xbdb7a1, 0xbeb8a0 # row 63 .word 0xfbfdfa, 0xfbfdfa, 0xfcfcfa, 0xfcfcfa, 0xfdfdfb, 0xfefefc, 0xffffff, 0xffffff # row 63 .word 0xf9f9f9, 0xfcfcfc, 0xfdfbfc, 0xf8f8f8, 0xfaf8fb, 0xfefcff, 0xfffdff, 0xfef9fd # row 63 .word 0xfdf7fb, 0xfffeff, 0xf4feff, 0xedfbfb, 0xf0fefe, 0xfbffff, 0xfffdfb, 0xfff2ec # row 63 .word 0xfff5e9, 0xdfc0ab, 0x795c3c, 0x8b6e46, 0xa78558, 0xc4996c, 0x9f693d, 0xb87d55 # row 63 .word 0xb37954, 0xac7451, 0xad7753, 0x9d6743, 0x9c6843, 0xad7b56, 0xaf7e56, 0xb6865e # row 63 .word 0xb78a61, 0xc1966c, 0xba9066, 0xc0996e, 0xd4ad82, 0xbb966a, 0x9a7549, 0x9e794d # row 63 .word 0x99744a, 0xa67c54, 0xb18058, 0xae7653, 0xa16445, 0x975b3f, 0x98614c, 0x976e5c # row 63 .word 0x7e6457, 0x5e5148, 0xfffffb, 0x63686b, 0x081116, 0x050e17, 0x0f131f, 0x101420 # row 63 .word 0x10141f, 0x10131a, 0x101115, 0x1a1c1b, 0x1b1c16, 0x16160c, 0xcbc8b9, 0xbcb7a4 # row 63 .word 0xbbb6a0, 0xbdb79f, 0xbeb8a0 # row 64 .word 0xfafcfb, 0xf9fbfa, 0xf8faf9, 0xfafcfb, 0xfcfefd, 0xfeffff, 0xfdfeff, 0xfcfdff # row 64 .word 0xf9fafc, 0xfbfcfe, 0xfafafc, 0xf7f8fa, 0xfafafc, 0xfefeff, 0xfefeff, 0xfafafc # row 64 .word 0xfdfcff, 0xfcfbff, 0xfbfcff, 0xf8fcfd, 0xf8fcfb, 0xfbfdfa, 0xfdfcfa, 0xfffcf8 # row 64 .word 0xfdf6ee, 0xffffef, 0x928771, 0x776648, 0xa88e69, 0xb08e61, 0xbf9362, 0xbd8a5b # row 64 .word 0xba855d, 0xbe8661, 0xc18b65, 0xc38d67, 0xc38f68, 0xc5946c, 0xcb9b75, 0xcfa27b # row 64 .word 0xc89c75, 0xcca27a, 0xd0a980, 0xcda87e, 0xc09d73, 0xaf8c62, 0x9f7c52, 0x95744b # row 64 .word 0x947650, 0xb09069, 0x996f49, 0x95633e, 0xa16644, 0xac7153, 0x935c47, 0x9d7262 # row 64 .word 0x6c4f49, 0x837374, 0xc4c1c8, 0x6b6f78, 0x00040b, 0x131e22, 0x121c1d, 0x050d10 # row 64 .word 0x0f131c, 0x181b24, 0x020308, 0x222423, 0x21221c, 0x141408, 0xc4c3b1, 0xb8b6a1 # row 64 .word 0xb9b59c, 0xb9b598, 0xbbb699 # row 65 .word 0xfafbfd, 0xf9fafc, 0xf8f9fb, 0xfafbfd, 0xfcfdff, 0xfeffff, 0xfdfeff, 0xfcfdff # row 65 .word 0xf9fafc, 0xfbfcfe, 0xf9fafc, 0xf7f8fa, 0xf9fafc, 0xfdfeff, 0xfdfeff, 0xf9fafc # row 65 .word 0xfcfdff, 0xfbfcff, 0xfdfbfe, 0xfcfafb, 0xfcfbf9, 0xfcfcfa, 0xfcfcfa, 0xfcfefb # row 65 .word 0xf6fbf5, 0xf8fbf2, 0xe5e3d4, 0x564b35, 0x8d7958, 0xb3966c, 0xa98352, 0xbc8e5d # row 65 .word 0xbe8a62, 0xc08a64, 0xc38d69, 0xc7936c, 0xcc9a75, 0xd0a07a, 0xd1a47d, 0xd2a67f # row 65 .word 0xcca27a, 0xcba47b, 0xcaa37a, 0xc39d76, 0xb49169, 0xa5845b, 0x98774e, 0x91714a # row 65 .word 0x8d714c, 0x967852, 0x926c45, 0x9c6c46, 0xa16b45, 0x955c3e, 0x9f6b55, 0x986c5f # row 65 .word 0x5f413f, 0xb8a7ad, 0xb0adb8, 0x636772, 0x000209, 0x0d181a, 0x0a1511, 0x17201d # row 65 .word 0x03060f, 0x191b27, 0x1a1b20, 0x101211, 0x10110c, 0x27291c, 0xd6d5c3, 0xb4b49c # row 65 .word 0xbab99d, 0xbcb89b, 0xbeb99c # row 66 .word 0xfafbfd, 0xf9fafc, 0xf8f9fb, 0xfafbfd, 0xfcfdff, 0xfeffff, 0xfdfeff, 0xfcfdff # row 66 .word 0xf9fafc, 0xfbfcfe, 0xf9fafc, 0xf7f8fa, 0xf9fafc, 0xfdfeff, 0xfdfeff, 0xf9fafc # row 66 .word 0xfcfdff, 0xfbfcff, 0xfdfbfe, 0xfcfafb, 0xfcfbf9, 0xfcfcfa, 0xfcfcfc, 0xfcfefb # row 66 .word 0xfcfffd, 0xf7faf3, 0xfffdf1, 0xfffbe8, 0x655234, 0x9c8059, 0xc39e71, 0xb98d60 # row 66 .word 0xc5946c, 0xc3916c, 0xc3916e, 0xc69670, 0xcc9c78, 0xcb9d79, 0xc89a76, 0xc29671 # row 66 .word 0xc69c76, 0xc19a73, 0xba936c, 0xae8863, 0xa07d57, 0x95724c, 0x8f6c46, 0x8b6943 # row 66 .word 0x8f6f49, 0x896741, 0x956b43, 0x996941, 0xa36d49, 0x945f3f, 0xa97962, 0x815a4b # row 66 .word 0x7c635f, 0xe6d7da, 0xc0bfc7, 0xbabec9, 0x000209, 0x000507, 0x010a07, 0x101616 # row 66 .word 0x1e2128, 0x070711, 0x191a1f, 0x232524, 0x1e1f1a, 0x121407, 0xbbbaa8, 0xb7b6a1 # row 66 .word 0xb8b69d, 0xb9b59a, 0xbbb59b # row 67 .word 0xfafbfd, 0xf9fafc, 0xf8f9fb, 0xfafbfd, 0xfcfdff, 0xfeffff, 0xfdfeff, 0xfcfdff # row 67 .word 0xf9fafc, 0xfbfcfe, 0xf9fafc, 0xf7f8fa, 0xf9fafc, 0xfdfeff, 0xfdfeff, 0xf9fafc # row 67 .word 0xfcfdff, 0xfbfcff, 0xfcfcfe, 0xfcfafb, 0xfcfbf9, 0xfdfcfa, 0xfcfcfc, 0xfcfefd # row 67 .word 0xf4f8f7, 0xfefffb, 0xc8c5be, 0x8d8676, 0xe1cfb7, 0x6b5032, 0x8b6842, 0xa47a52 # row 67 .word 0xad7f5b, 0xaf7f5b, 0xae805e, 0xb0825e, 0xb18562, 0xaf835e, 0xaa7e5b, 0xa57b55 # row 67 .word 0xb38865, 0xae8662, 0xa77f5b, 0x9c7651, 0x936d48, 0x8c6943, 0x8d6742, 0x8d6742 # row 67 .word 0x97714c, 0x916741, 0x9a6d46, 0x8e5d35, 0xa16d48, 0xaa7959, 0x9b7159, 0x755445 # row 67 .word 0xd1bcb7, 0xb8aeaf, 0xbbbbc3, 0xd3dae2, 0xc2c9cf, 0x7d8588, 0x757b7b, 0x181c1d # row 67 .word 0x06060e, 0x000009, 0x0e0f14, 0x141517, 0x181914, 0x1d1f14, 0xd3d4c4, 0xbcbba7 # row 67 .word 0xb8b69f, 0xb8b69d, 0xb9b59c # row 68 .word 0xfafbfd, 0xf9fafc, 0xf8f9fb, 0xfafbfd, 0xfcfdff, 0xfeffff, 0xfdfeff, 0xfcfdff # row 68 .word 0xf9fafc, 0xfbfcfe, 0xf9fafc, 0xf7f8fa, 0xf9fafc, 0xfdfeff, 0xfdfeff, 0xf9fafc # row 68 .word 0xfafeff, 0xfbfcff, 0xfcfcfe, 0xfcfafb, 0xfefaf9, 0xfdfcfa, 0xfcfcfc, 0xfcfdff # row 68 .word 0xf5f9fa, 0xfeffff, 0xf9f8f4, 0xd0c7be, 0xd9c8b8, 0xd7bda6, 0x7d5c3d, 0x99734f # row 68 .word 0x936846, 0x986d4a, 0x9e7351, 0xa17653, 0xa17654, 0xa17653, 0xa27755, 0xa17955 # row 68 .word 0x98704d, 0x98704d, 0x966e4b, 0x936b48, 0x8f6744, 0x8d6743, 0x906845, 0x946946 # row 68 .word 0x986a46, 0x976540, 0xa06c45, 0x94603b, 0x9e6c49, 0xae8363, 0x7c5840, 0x967c6d # row 68 .word 0xe2d3cc, 0xddd9d8, 0xbbbec3, 0xc6cdd5, 0xc6cdd3, 0xbcc1c5, 0xb8b9bb, 0xdad9de # row 68 .word 0xbcbcc4, 0x4d4d55, 0x000005, 0x101113, 0x292a25, 0x15170c, 0xbabbad, 0xabaa98 # row 68 .word 0xb8b6a1, 0xbbb9a2, 0xbfbaa4 # row 69 .word 0xfafbfd, 0xf9fafc, 0xf8f9fb, 0xfafbfd, 0xfcfdff, 0xfeffff, 0xfdfeff, 0xfcfdff # row 69 .word 0xf9fafc, 0xfbfcfe, 0xf9fafc, 0xf7f8fa, 0xf9fafc, 0xfdfeff, 0xfdfeff, 0xf9fafc # row 69 .word 0xfafeff, 0xfbfcfe, 0xfcfcfc, 0xfcfbf9, 0xfefaf9, 0xfdfcfa, 0xfcfcfe, 0xfcfdff # row 69 .word 0xfcffff, 0xe8e9ed, 0xfffdfe, 0xfef6f3, 0xfff7ed, 0xfff9e9, 0x775740, 0x603b20 # row 69 .word 0x815a3b, 0x865f3e, 0x8a6342, 0x8a6342, 0x87603f, 0x875e3e, 0x8b6242, 0x8f6744 # row 69 .word 0x805737, 0x825a37, 0x865e3b, 0x88603d, 0x88603d, 0x88603d, 0x8c613f, 0x906240 # row 69 .word 0x96603c, 0x975f3a, 0x9f6943, 0xa5714c, 0x9c6e4c, 0x957053, 0x745842, 0xccbbab # row 69 .word 0xcfc6bd, 0xc3c3c1, 0xdadfe3, 0xbbc2c8, 0xd1d6dc, 0xc3c6cb, 0xbebcc1, 0xbebcc1 # row 69 .word 0xbdbcc4, 0xf2f2fa, 0xe5e6eb, 0x959698, 0x2b2c27, 0x0d0e06, 0xb3b3a7, 0xc2c3b3 # row 69 .word 0xaead99, 0xb4b29d, 0xbcb7a3 # row 70 .word 0xfafbfd, 0xf9fafc, 0xf8f9fb, 0xfafbfd, 0xfcfdff, 0xfeffff, 0xfdfeff, 0xfcfdff # row 70 .word 0xf9fafc, 0xfbfcfe, 0xf9fafc, 0xf7f8fa, 0xf9fafc, 0xfdfeff, 0xfdfeff, 0xf9fafc # row 70 .word 0xfafeff, 0xfbfcfe, 0xfcfcfc, 0xfcfbf9, 0xfefaf9, 0xfdfcfa, 0xfcfcfe, 0xfcfdff # row 70 .word 0xfcffff, 0xfcffff, 0xfffeff, 0xfffdff, 0xfef1eb, 0x887267, 0x765949, 0x8f6c56 # row 70 .word 0x765337, 0x765232, 0x734f2f, 0x6f4b2b, 0x6d4929, 0x6f4829, 0x714a2b, 0x724b2a # row 70 .word 0x795032, 0x7c5333, 0x835838, 0x855a3a, 0x855a3a, 0x855a3a, 0x86593a, 0x8a5938 # row 70 .word 0x995d39, 0xa66843, 0xa26a45, 0xaa7855, 0x997050, 0x85664a, 0xa28d78, 0xe1d5c5 # row 70 .word 0xd3d0c7, 0xc3c8c4, 0xc6cbce, 0xd7dce2, 0xb4b7be, 0xdfdfe7, 0xcdc8cf, 0xbfbac1 # row 70 .word 0xcac9d1, 0xc0c0c8, 0xcfced4, 0xe9e9eb, 0xeeeeec, 0xe2e3dd, 0xdcdcd2, 0xacad9f # row 70 .word 0xbbb9aa, 0xb6b5a3, 0xb3b09f # row 71 .word 0xfafbfd, 0xf9fafc, 0xf8f9fb, 0xfafbfd, 0xfcfdff, 0xfeffff, 0xfdfeff, 0xfcfdff # row 71 .word 0xf9fafc, 0xfbfcfe, 0xf9fafc, 0xf7f8fa, 0xf9fafc, 0xfdfeff, 0xfdfeff, 0xf9fafc # row 71 .word 0xfafeff, 0xfbfdfc, 0xfcfcfc, 0xfcfbf9, 0xfefaf7, 0xfdfcfa, 0xfdfbfe, 0xfcfdff # row 71 .word 0xf7faff, 0xf6f9ff, 0xfefeff, 0xede8ee, 0xe4d8d8, 0x28150f, 0x664b42, 0x8b6c5a # row 71 .word 0x8a684f, 0x856244, 0x7e5b3d, 0x7d5a3c, 0x825d40, 0x866144, 0x8a6346, 0x8a6344 # row 71 .word 0x82593b, 0x855c3e, 0x8a5f3f, 0x8b6040, 0x8a5d3e, 0x895c3d, 0x885b3c, 0x8c5a39 # row 71 .word 0xa26340, 0xb87854, 0xa76f4c, 0xa07251, 0x957256, 0x866e56, 0xd8cbb8, 0xd0cdbe # row 71 .word 0xcbcec5, 0xd2d8d4, 0xccd1d4, 0xc2c7cb, 0xdddde5, 0xc8c7cf, 0xc8c2cc, 0xdfd9e3 # row 71 .word 0xd2d1d9, 0xc5c6cb, 0xe7e6eb, 0xdfdfe1, 0xd4d4d2, 0xeff0ea, 0xdeded6, 0xedede1 # row 71 .word 0xdcdacd, 0xc8c6b9, 0xb2b0a1 # row 72 .word 0xf7f8fa, 0xfdfeff, 0xf6f7f9, 0xfeffff, 0xfafbfd, 0xfbfcfe, 0xfeffff, 0xedeef0 # row 72 .word 0xfcfdff, 0xfeffff, 0xf8f9fb, 0xf7f8fa, 0xfeffff, 0xfbfcfe, 0xf7f8fa, 0xfcfdff # row 72 .word 0xf8fcfd, 0xfeffff, 0xffffff, 0xfffffd, 0xfbf7f4, 0xf6f5f3, 0xfefcff, 0xfeffff # row 72 .word 0xf7faff, 0xd6dae5, 0xc5c8d1, 0xa6a5ad, 0x988f92, 0x201010, 0x56413c, 0x816559 # row 72 .word 0x83634c, 0x876448, 0x856246, 0x825f43, 0x856045, 0x8a6548, 0x90694c, 0x916a4d # row 72 .word 0x8b6244, 0x875b3e, 0x86593a, 0x895c3d, 0x8c5d3f, 0x8d5e40, 0x966749, 0xa57050 # row 72 .word 0xb57653, 0xbd7e5b, 0xb47d5e, 0x9a7153, 0x94765e, 0xa2917d, 0xe8e1d1, 0xd1d3c8 # row 72 .word 0xc8cfc7, 0xd2dbd8, 0xc9cfcf, 0xc2c7cb, 0xd3d3db, 0xd5d4dc, 0xcfc9d3, 0xd4ced8 # row 72 .word 0xd5d4dc, 0xd4d3d9, 0xd8d7dc, 0xdfdfe1, 0xe3e3e1, 0xe3e4df, 0xe6e5e0, 0xeaeae2 # row 72 .word 0xe7e7dd, 0xe8e8dc, 0xe9e9dd # row 73 .word 0xf6f7f9, 0xfeffff, 0xfeffff, 0xf2f3f5, 0xfeffff, 0xfeffff, 0xfeffff, 0xfeffff # row 73 .word 0xf7f8fa, 0xfdfeff, 0xf9fafc, 0xf6f7f9, 0xfafbfd, 0xf6f7f9, 0xf3f4f6, 0xfafbfd # row 73 .word 0xf9fdfe, 0xf3f5f4, 0xf1f1f1, 0xfdfcfa, 0xfffefb, 0xfffefd, 0xf5f3f6, 0xdedfe4 # row 73 .word 0xbbbec7, 0xafb3be, 0xa6aab5, 0xa1a1ab, 0x8d868d, 0x1a0e10, 0x544240, 0x856d63 # row 73 .word 0x81614c, 0x856147, 0x886348, 0x896449, 0x896449, 0x896147, 0x896245, 0x8c6347 # row 73 .word 0x906447, 0x8d6242, 0x8e6142, 0x926546, 0x956648, 0x956746, 0x9d6c4e, 0xa87353 # row 73 .word 0xb37755, 0xb87c5a, 0xa57456, 0x977359, 0x927b69, 0xdacec0, 0xc8c8be, 0xd9ded7 # row 73 .word 0xc8d1cc, 0xd2dbd8, 0xc5cbcb, 0xcaced1, 0xd1d2d7, 0xd8d7df, 0xccc9d4, 0xd7d4df # row 73 .word 0xdddce2, 0xdbdadf, 0xdcdcde, 0xe1e1e3, 0xe3e3e3, 0xe2e2e0, 0xe4e3df, 0xe8e7e2 # row 73 .word 0xe8e8e0, 0xe8e8e0, 0xe9e9e1 # row 74 .word 0xf7f8fa, 0xf6f7f9, 0xfeffff, 0xedeef0, 0xfbfcfe, 0xf4f5f7, 0xf9fafc, 0xfcfdff # row 74 .word 0xf9fafc, 0xfeffff, 0xfeffff, 0xfbfcfe, 0xfeffff, 0xfcfdff, 0xfafbfd, 0xfeffff # row 74 .word 0xf8fcfd, 0xf8fcfb, 0xfdfdfd, 0xfffffd, 0xfffcf9, 0xf1edea, 0xd8d6d7, 0xc5c6ca # row 74 .word 0xa3a7b0, 0xa4abb5, 0x959ba7, 0xa8abb4, 0x858289, 0x191013, 0x4a3c3b, 0x806961 # row 74 .word 0x876653, 0x89644a, 0x8f674e, 0x976f56, 0x987056, 0x936950, 0x91684c, 0x976b50 # row 74 .word 0x95694c, 0x96694a, 0x996a4c, 0x9d6f4e, 0xa06f4f, 0xa06f4e, 0xa57253, 0xad7858 # row 74 .word 0xb57d5c, 0xaf7859, 0xa4785f, 0x8c6d59, 0xc2b0a4, 0xe7e3da, 0xcfd1ce, 0xd2dbd8 # row 74 .word 0xcdd6d3, 0xced7d6, 0xc4c8c9, 0xd2d3d7, 0xd3d2d8, 0xd6d5dd, 0xcccad5, 0xdcdae5 # row 74 .word 0xe0dfe5, 0xdddddf, 0xdddddf, 0xe1e1e3, 0xe2e2e2, 0xe1e1df, 0xe3e3e1, 0xe7e8e3 # row 74 .word 0xe6e7e2, 0xe7e8e3, 0xe8e9e3 # row 75 .word 0xfeffff, 0xecedef, 0xfeffff, 0xfeffff, 0xf5f6f8, 0xfdfeff, 0xfeffff, 0xf4f5f7 # row 75 .word 0xf4f5f7, 0xfbfcfe, 0xf5f6f8, 0xf0f1f3, 0xf7f8fa, 0xf9fafc, 0xf8f9fb, 0xfbffff # row 75 .word 0xf8fcfd, 0xfcffff, 0xffffff, 0xf5f4f0, 0xded9d6, 0xcac6c3, 0xc4c2c3, 0xc5c6ca # row 75 .word 0xb7bbc4, 0xb3bac4, 0x959ba7, 0xb2b6c1, 0x88878d, 0x262024, 0x3e3232, 0x6b574e # row 75 .word 0x926f5c, 0x8d634b, 0x8d634b, 0x9a7057, 0xa4785f, 0xa1755a, 0xa17359, 0xa6795c # row 75 .word 0x9c6f50, 0x9d6f4e, 0x9f7150, 0xa17351, 0xa47352, 0xa67554, 0xab7958, 0xaf7d5c # row 75 .word 0xb58060, 0xb18266, 0x9e7a64, 0xa99284, 0xe8ddd7, 0xd6d6d4, 0xe0e8ea, 0xc6d0d2 # row 75 .word 0xd2dadc, 0xc9cfcf, 0xcbccce, 0xd1d1d3, 0xd9d8dd, 0xceced6, 0xd0d3dc, 0xdde0e9 # row 75 .word 0xdddce1, 0xdadadc, 0xdbdbdd, 0xdfdfe1, 0xe2e2e2, 0xe1e1e1, 0xe4e4e4, 0xe9e9e7 # row 75 .word 0xe5e5e5, 0xe6e6e4, 0xe6e6e4 # row 76 .word 0xf3f4f6, 0xf0f1f3, 0xf2f3f5, 0xfbfcfe, 0xf3f4f6, 0xfeffff, 0xf6f7f9, 0xf8f9fb # row 76 .word 0xfeffff, 0xfeffff, 0xf9fafc, 0xf3f4f6, 0xfbfcfe, 0xfeffff, 0xfbfcfe, 0xf9fdfe # row 76 .word 0xf4f8fb, 0xe9edee, 0xdcdcdc, 0xd2d1cd, 0xcfcac7, 0xcbc7c4, 0xc7c6c4, 0xc2c3c5 # row 76 .word 0xbabfc5, 0xacb3bb, 0x8f98a1, 0xb3b7c0, 0x94959a, 0x423d41, 0x312927, 0x4a362f # row 76 .word 0x96715f, 0x8e6049, 0x875941, 0x90624a, 0x9c6e56, 0xa17359, 0xa3745a, 0xa6775b # row 76 .word 0xa07153, 0xa37252, 0xa37252, 0xa27150, 0xa47251, 0xa87653, 0xae7c59, 0xb1805f # row 76 .word 0xab7e5f, 0xaa856b, 0x9f8471, 0xe4d3c9, 0xd9d5d4, 0xd9dee2, 0xd8e1e8, 0xc9d3dc # row 76 .word 0xd7dee4, 0xc4c8cb, 0xd5d5d7, 0xcbcbcd, 0xdfdee3, 0xc3c6cb, 0xd6dde7, 0xdbdfe8 # row 76 .word 0xdedfe3, 0xdddbdc, 0xdddddf, 0xe2e2e4, 0xe4e4e6, 0xe3e3e5, 0xe5e5e7, 0xe9e9e9 # row 76 .word 0xe3e3e5, 0xe4e4e4, 0xe4e6e5 # row 77 .word 0xf7f8fa, 0xfeffff, 0xf4f5f7, 0xf4f5f7, 0xfeffff, 0xfafbfd, 0xf4f5f7, 0xfeffff # row 77 .word 0xf8f9fb, 0xfeffff, 0xfcfdff, 0xf5f6f8, 0xfcfdff, 0xfeffff, 0xf6f7f9, 0xf1f5f6 # row 77 .word 0xe2e6e9, 0xd3d7d8, 0xc6c6c6, 0xc2c1bd, 0xc8c3c0, 0xcac6c3, 0xc4c3c1, 0xbcbdbf # row 77 .word 0xb1b6bc, 0x9ca3ab, 0x9ba4ad, 0xb5bcc4, 0xa7aaaf, 0x615f60, 0x241f1c, 0x28150e # row 77 .word 0x946d5c, 0x95624d, 0x8e5c45, 0x8f5d46, 0x96644b, 0x9e6c51, 0xa27055, 0xa27153 # row 77 .word 0xa47353, 0xa67554, 0xa57453, 0xa2724e, 0xa3714e, 0xaa7853, 0xb07e59, 0xaf815d # row 77 .word 0xa98263, 0x977760, 0xceb8aa, 0xeadfd9, 0xd5d6da, 0xd8e1ea, 0xccd6e2, 0xd1dbe7 # row 77 .word 0xd8dfe7, 0xc6c9ce, 0xdad8db, 0xcccacb, 0xd7d8dc, 0xc2c7cb, 0xd9e2eb, 0xd6dfe6 # row 77 .word 0xe2e3e7, 0xe2e0e1, 0xe2e2e4, 0xe7e7e9, 0xe7e7e9, 0xe4e4e6, 0xe4e4e6, 0xe7e7e9 # row 77 .word 0xe3e3e5, 0xe3e3e5, 0xe3e4e6 # row 78 .word 0xcccdcf, 0xdbdcde, 0xdcdddf, 0xdcdddf, 0xedeef0, 0xbdbec0, 0xedeef0, 0xdbdcde # row 78 .word 0xc7c8ca, 0xdedfe1, 0xe6e7e9, 0xe2e3e5, 0xe5e6e8, 0xe4e5e7, 0xdcdddf, 0xd8dcdd # row 78 .word 0xd1d5d8, 0xcfd3d6, 0xcdcdcd, 0xc7c6c2, 0xc4bfbc, 0xc0bcb9, 0xbebdbb, 0xbebebe # row 78 .word 0xadb2b6, 0x959ca2, 0xb5bec5, 0xb9c2c7, 0xb5babd, 0x7b7b7b, 0x231f1c, 0x200e04 # row 78 .word 0x875e4c, 0x9a6650, 0x9d6953, 0x97634d, 0x956149, 0x9d6a4f, 0xa37055, 0xa16e51 # row 78 .word 0xa47152, 0xa97756, 0xab7958, 0xa77552, 0xa87651, 0xae7d55, 0xb18058, 0xad815c # row 78 .word 0xa88567, 0xb0967f, 0xf4e4d7, 0xd9d4d0, 0xe0e5eb, 0xd2dbea, 0xd0dcec, 0xd1dae9 # row 78 .word 0xd7dbe6, 0xd0d0d8, 0xd6d1d5, 0xd6d4d5, 0xc6c7cb, 0xccd1d5, 0xd3e0e8, 0xd3dee4 # row 78 .word 0xdedfe3, 0xdfddde, 0xe1e1e1, 0xe7e7e7, 0xe8e8ea, 0xe4e4e6, 0xe2e1e6, 0xe4e3e8 # row 78 .word 0xe3e4e8, 0xe4e5e9, 0xe5e6ea # row 79 .word 0x35393c, 0x1a1e21, 0x606467, 0x73777a, 0x626669, 0x272b2e, 0x9ea2a3, 0x474b4c # row 79 .word 0xa9aaac, 0xcbccce, 0xe0e1e3, 0xe2e4e3, 0xe3e5e4, 0xe1e1e1, 0xdbdbdb, 0xdbdddc # row 79 .word 0xd1d2d4, 0xcecfd1, 0xcacaca, 0xc8c7c5, 0xc8c4c1, 0xc8c4c1, 0xc5c4c2, 0xc4c4c6 # row 79 .word 0xa8abb0, 0x90959b, 0xc5ccd2, 0xbabfc3, 0xbabebf, 0x8a8a88, 0x2d2926, 0x2e1d15 # row 79 .word 0x704b39, 0x93634f, 0xa5725d, 0x9b6952, 0x946048, 0x9b684d, 0xa46e52, 0xa36d51 # row 79 .word 0xa67152, 0xad7858, 0xae7c5b, 0xab7a59, 0xab7a59, 0xae805e, 0xaf8360, 0xa88162 # row 79 .word 0x9c826b, 0xebdaca, 0xe4dad1, 0xe6e5e3, 0xdadfe5, 0xdae2ef, 0xd7deee, 0xd0d6e4 # row 79 .word 0xd5d8e1, 0xd9d8de, 0xcccacd, 0xe0dedf, 0xb6b7b9, 0xd6dbde, 0xd0dbdf, 0xd3dce1 # row 79 .word 0xd4d5d7, 0xd6d4d5, 0xdbdbdb, 0xe3e3e3, 0xe6e6e6, 0xe3e3e5, 0xe2e2e4, 0xe3e3e5 # row 79 .word 0xe5e6e8, 0xe6e7e9, 0xe7e8ea # row 80 .word 0x434c53, 0x5e676e, 0x616a6f, 0x7b8489, 0x676f72, 0x697174, 0x767b7e, 0x757a7d # row 80 .word 0xe2e6e7, 0xe0e1e3, 0xdcdedd, 0xdddddb, 0xdfdfdd, 0xdfdedc, 0xdad9d5, 0xd4d3cf # row 80 .word 0xd6d5d3, 0xcfcecc, 0xcfcecc, 0xcdccca, 0xc3c1c2, 0xc2c2c2, 0xc6c6c8, 0xc0c1c5 # row 80 .word 0xa2a3a7, 0xa9aaae, 0xd3d4d8, 0xccccce, 0xafadae, 0xbab6b5, 0x443c3a, 0x23140d # row 80 .word 0x5c3f31, 0x855e4d, 0x9b7260, 0x91644f, 0xae7c65, 0xa16b53, 0xa36b52, 0xad7459 # row 80 .word 0xae7558, 0xac7557, 0xa77457, 0xa5765a, 0xa97d62, 0xaa8268, 0xa17d63, 0x8f745f # row 80 .word 0xe7d9d0, 0xe2ddd9, 0xe2dedd, 0xdedede, 0xd9dade, 0xd5d8dd, 0xd7dae1, 0xd9dce1 # row 80 .word 0xdcdde1, 0xcecfd1, 0xd3d3d5, 0xd6d8d7, 0xb6b8b7, 0xdbdfe0, 0xdce2e2, 0xd8dede # row 80 .word 0xdee0df, 0xdfdfdd, 0xe0e0de, 0xe0e0de, 0xe0e0de, 0xe1e1e1, 0xe1e1e1, 0xe1e1e1 # row 80 .word 0xe5e5e5, 0xe6e6e6, 0xe8e8e8 # row 81 .word 0x36434b, 0x849199, 0x545f65, 0x949fa5, 0x60696e, 0x555f61, 0x848c8e, 0xeef3f6 # row 81 .word 0xe1e5e6, 0xdde1e0, 0xdcdcdc, 0xdddddb, 0xe0dfdb, 0xdfdeda, 0xdcd9d4, 0xd7d4cf # row 81 .word 0xdad6d3, 0xd5d1ce, 0xcecdcb, 0xc4c3c1, 0xbfbfc1, 0xcbccce, 0xcecfd3, 0xbdbec2 # row 81 .word 0x8f9094, 0xcccbd0, 0xbab9be, 0xc6c4c7, 0xcbc7c8, 0xa9a3a3, 0x6a6162, 0x1c0d08 # row 81 .word 0x62463a, 0x74513e, 0x926c57, 0x9f725d, 0xa5735c, 0xa26a51, 0xac7358, 0xad7155 # row 81 .word 0xb4785c, 0xb67d60, 0xa77459, 0xa2745a, 0xad856c, 0xa7846e, 0xa88975, 0xbba597 # row 81 .word 0xe4dcd9, 0xe0e0e2, 0xe1e1e3, 0xdfdfe1, 0xdcdcde, 0xdadadc, 0xdbdbdd, 0xdddddf # row 81 .word 0xdcdddf, 0xd0d1d3, 0xd4d6d5, 0xcdcfce, 0xbfc3c2, 0xdadedd, 0xdbdfde, 0xdadedd # row 81 .word 0xdfdfdd, 0xdfdfdd, 0xdfdfdd, 0xdfdfdd, 0xe0e0de, 0xe0e0de, 0xe0e0de, 0xe1e1df # row 81 .word 0xe3e3e1, 0xe4e4e2, 0xe6e6e4 # row 82 .word 0x5e696f, 0x8a959b, 0x59646a, 0x8c979d, 0x576065, 0x566062, 0xdce4e6, 0xd8dde0 # row 82 .word 0xdee2e3, 0xdbdfde, 0xdcdcdc, 0xdcdcda, 0xdfdeda, 0xdeddd9, 0xdad9d4, 0xd7d6d1 # row 82 .word 0xd8d5d0, 0xd6d2cf, 0xcecdcb, 0xc2c1bf, 0xc2c2c4, 0xd3d4d6, 0xcecfd3, 0xaeb1b6 # row 82 .word 0x9da0a5, 0xe2e3e8, 0xd4d5da, 0xc5c4c9, 0xbfbec3, 0xd0ced1, 0x8e898d, 0x120401 # row 82 .word 0x6a4a3b, 0x714832, 0x93664f, 0xb28369, 0xa06a50, 0xa76e51, 0xb27759, 0xab6e51 # row 82 .word 0x9b6042, 0xbb8265, 0xa37055, 0x996b53, 0xb88f79, 0xa8856f, 0xa98a76, 0xebd8ca # row 82 .word 0xe6dedc, 0xe1e0e5, 0xe2e1e6, 0xe0dfe4, 0xdddee0, 0xdcdddf, 0xdcdddf, 0xdddee0 # row 82 .word 0xdcdddf, 0xd3d4d6, 0xd6d8d7, 0xbfc1c0, 0xcfd3d2, 0xd9dddc, 0xd9dddc, 0xdadedd # row 82 .word 0xdededc, 0xdededc, 0xdededc, 0xdfdfdd, 0xdfdfdd, 0xe0e0de, 0xe0e0de, 0xe0e0de # row 82 .word 0xe1e1df, 0xe2e2e0, 0xe3e3e1 # row 83 .word 0x323d43, 0x556066, 0x677278, 0x798488, 0xc3cdcf, 0xe9f1f4, 0xe3e8eb, 0xdbe1e1 # row 83 .word 0xdce0e1, 0xdcdedd, 0xdbdbd9, 0xdcdcda, 0xdeddd9, 0xdddcd8, 0xdad9d4, 0xd7d6d1 # row 83 .word 0xd5d2cd, 0xd2cfca, 0xcfcecc, 0xcbcbcb, 0xcacacc, 0xd0d1d5, 0xc4c7cc, 0xa7acb2 # row 83 .word 0xb7bcc2, 0xccd1d7, 0xebeef5, 0xc7cad1, 0xc1c2c7, 0xabacb1, 0xaeadb2, 0x3a2f2d # row 83 .word 0x603f2e, 0x7f5139, 0x996a50, 0xb8856a, 0xa26b4d, 0xaf7658, 0xaf7456, 0xaa6f51 # row 83 .word 0xb57c5e, 0xa06a4e, 0xaf8066, 0xb48a72, 0x99755f, 0xae8f7b, 0xe6cbba, 0xf4e2d6 # row 83 .word 0xe5dfdf, 0xe1e0e5, 0xe1e0e5, 0xe0dfe4, 0xdedfe3, 0xdddee0, 0xdcdddf, 0xdddee0 # row 83 .word 0xdbdcde, 0xd6d7d9, 0xd9dbda, 0xb3b5b4, 0xdde1e0, 0xd9dddc, 0xd7dbda, 0xdddfde # row 83 .word 0xdededc, 0xdededc, 0xdededc, 0xdededc, 0xdfdfdd, 0xdfdfdd, 0xe0e0de, 0xe0e0de # row 83 .word 0xe0e0de, 0xe1e1df, 0xe1e1df # row 84 .word 0x555e63, 0x555e63, 0x586166, 0xc9d3d5, 0xd9e1e4, 0xe6eef1, 0xdce1e4, 0xd9dfdf # row 84 .word 0xdadedf, 0xdbdddc, 0xdbdbd9, 0xdbdbd9, 0xdcdbd7, 0xdbdad6, 0xd9d8d4, 0xd7d6d2 # row 84 .word 0xd8d5d0, 0xcdcac5, 0xcecdcb, 0xd3d3d3, 0xcdcdcf, 0xc6cacd, 0xc1c6ca, 0xb7bec4 # row 84 .word 0xdfe6ee, 0xadb4be, 0x171e28, 0xb7bec8, 0xccd0d9, 0xcbcfd8, 0xa5a8b1, 0x665c5b # row 84 .word 0x522f1c, 0x905e43, 0xa06d50, 0xaf7a5b, 0xac7557, 0xb98062, 0xa86f51, 0xae7557 # row 84 .word 0xb57f63, 0xa8765b, 0xa1745d, 0x9d7762, 0xa88977, 0xcfb5a4, 0xf3ddcf, 0xf4e6dd # row 84 .word 0xe4e0e1, 0xdfe0e5, 0xdedfe4, 0xdedfe3, 0xdedfe3, 0xdddee2, 0xdcdde1, 0xdbdce0 # row 84 .word 0xdbdcde, 0xd8d9db, 0xdadcdb, 0xafb1b0, 0xe6e8e7, 0xdbdddc, 0xd8dad9, 0xdddfde # row 84 .word 0xdededc, 0xdededc, 0xdededc, 0xdfdfdd, 0xdfdfdd, 0xe0e0de, 0xe0e0de, 0xe0e0de # row 84 .word 0xe1e1df, 0xe1e1df, 0xe1e1df # row 85 .word 0x8e979c, 0x8f999b, 0xa2acae, 0xf4fcff, 0xe5edf0, 0xc7cfd1, 0xe4eaea, 0xe3e7e8 # row 85 .word 0xdcdedd, 0xdbdddc, 0xdcdcda, 0xdbdbd9, 0xdbdad6, 0xd9d8d4, 0xd8d7d3, 0xd6d5d1 # row 85 .word 0xded9d5, 0xcecbc6, 0xcfcbca, 0xd3d3d3, 0xcacbcd, 0xc2c5ca, 0xc9ced4, 0xccd5dc # row 85 .word 0xa9b2bb, 0x5a646e, 0x0f1722, 0x3e4651, 0xdbe3ee, 0xa2aab5, 0xacb2be, 0xb8afb0 # row 85 .word 0x5c3926, 0x97654a, 0xa06f51, 0xa67356, 0xb88266, 0xbc866a, 0xaa7458, 0xb07e63 # row 85 .word 0x986a50, 0xa47a64, 0x9d7865, 0xa68677, 0xd5beb0, 0xf8e6da, 0xf9e8e0, 0xeee5e0 # row 85 .word 0xe3e1e4, 0xdde0e5, 0xdedfe4, 0xdcdfe4, 0xdedfe4, 0xdedfe3, 0xdcdde1, 0xdbdce0 # row 85 .word 0xdcdddf, 0xd8d9db, 0xdbdddc, 0xb3b5b4, 0xe5e7e6, 0xdcdedd, 0xd9dbda, 0xdddfde # row 85 .word 0xdfdfdd, 0xdfdfdd, 0xe0e0de, 0xe0e0de, 0xe0e0de, 0xe1e1df, 0xe1e1df, 0xe1e1df # row 85 .word 0xe2e2e0, 0xe1e1df, 0xe0e0de # row 86 .word 0x2d3538, 0x2f3739, 0xeaf2f4, 0xe2e7ea, 0xc7cccf, 0xe9efef, 0xe6eaeb, 0xc9cdce # row 86 .word 0xdcdedd, 0xdcdedd, 0xdddddb, 0xdbdbd9, 0xd9d9d7, 0xd6d6d4, 0xd6d5d1, 0xd5d4d0 # row 86 .word 0xdbd6d2, 0xd1cec9, 0xd3cfce, 0xd1d1d1, 0xc7c8ca, 0xc4c9cd, 0xc8cfd7, 0xc7d0d9 # row 86 .word 0x727c86, 0x2f3b47, 0x36404c, 0x1b2531, 0x9fa9b5, 0xc6d0dc, 0xb2bac7, 0xbcb7bb # row 86 .word 0x8b6b5c, 0x97694f, 0xa2745a, 0xad7f65, 0xc09278, 0xb78971, 0xb0836c, 0xac836d # row 86 .word 0xad8875, 0x9a7b69, 0xc3a99c, 0xd5c1b8, 0xb6a7a0, 0xd5ccc7, 0xfffaf8, 0xe3e1e2 # row 86 .word 0xe3e4e9, 0xdee3e9, 0xdde0e7, 0xdce1e5, 0xdee1e6, 0xdee1e6, 0xdce0e3, 0xdadee1 # row 86 .word 0xdadedf, 0xd5d9da, 0xdcdedd, 0xbbbdbc, 0xdfe1e0, 0xdee0df, 0xdbddda, 0xdddfdc # row 86 .word 0xe0e0de, 0xe0e0de, 0xe1e1df, 0xe1e1df, 0xe2e2e0, 0xe2e2e0, 0xe2e2e0, 0xe2e2e0 # row 86 .word 0xe2e2e0, 0xe1e1df, 0xdfdfdd # row 87 .word 0x000104, 0xd0d5d8, 0xd4d9dc, 0xdae0e0, 0xebf1f1, 0xccd0d1, 0xd4d8d9, 0xe1e5e4 # row 87 .word 0xdcdedd, 0xdddfde, 0xdededc, 0xdbdbd9, 0xd8d8d6, 0xd5d5d3, 0xd4d3cf, 0xd4d3cf # row 87 .word 0xd2cecb, 0xd3cfcc, 0xd7d6d4, 0xd1d1d1, 0xc8c9cd, 0xc7ccd0, 0xc1c8d0, 0xafb9c3 # row 87 .word 0x4c5864, 0x333f4b, 0x4a5664, 0x626e7c, 0x636f7d, 0xaab6c4, 0xc0c9d8, 0xa29fa6 # row 87 .word 0xbb9f93, 0x956f58, 0xa37d68, 0xb8927d, 0xc39f89, 0xad8a76, 0xb2917e, 0xa18474 # row 87 .word 0xa08679, 0xe1cdc2, 0xbeafa8, 0x867c7a, 0x8c8887, 0x737375, 0x84878c, 0xf4f9ff # row 87 .word 0xe2e6ef, 0xdfe3ec, 0xdde1ea, 0xdde2e8, 0xdfe4ea, 0xdfe4e8, 0xdee1e6, 0xdbdfe2 # row 87 .word 0xdadee1, 0xd4d8d9, 0xdbdddc, 0xc2c4c3, 0xd9dbda, 0xdee0df, 0xdcdedb, 0xdddfdc # row 87 .word 0xe1e1df, 0xe1e1df, 0xe2e2e0, 0xe2e2e0, 0xe2e2e0, 0xe3e3e1, 0xe3e3e1, 0xe3e3e1 # row 87 .word 0xe1e1df, 0xe0e0de, 0xdededc # row 88 .word 0x4f5354, 0xe1e5e6, 0xe3e7e8, 0xe0e4e5, 0xd6dadb, 0xd6d8d7, 0xe1e3e2, 0xdddfde # row 88 .word 0xd7d9d8, 0xd8dad7, 0xd9d9d7, 0xd9d9d7, 0xd9d9d7, 0xd8d8d6, 0xd7d7d5, 0xd7d6d2 # row 88 .word 0xd5d1ce, 0xdcd8d5, 0xcccbc9, 0xcbcdcc, 0xcdd1d4, 0xc7ced4, 0xdde6ed, 0x656f79 # row 88 .word 0x333f4b, 0x495563, 0x677484, 0x7f8c9c, 0x8794a4, 0x8a97a7, 0x96a2b2, 0xababb3 # row 88 .word 0xc6b2ab, 0xccaf9f, 0x997c6e, 0xae9284, 0xb2988b, 0xad978a, 0xa9958a, 0xb4a69d # row 88 .word 0xc2b7b1, 0xa49f9b, 0x8f8d8e, 0x8c9093, 0x868d93, 0x757f88, 0x697581, 0x6a7682 # row 88 .word 0xe1eaf3, 0xd1d8e2, 0xe8eff9, 0xdde4ec, 0xd5dce4, 0xdde4ea, 0xe0e5e9, 0xd9dee1 # row 88 .word 0xdbdfe2, 0xd6dadb, 0xc0c2c1, 0xd7d9d8, 0xd7d9d6, 0xe1e3e0, 0xdfdfdd, 0xdfdfdd # row 88 .word 0xe1e1df, 0xdfdfdd, 0xdededc, 0xe0e0de, 0xe3e3e1, 0xe5e5e3, 0xe2e2e0, 0xe0e0de # row 88 .word 0xdededc, 0xdededc, 0xdfdfdd # row 89 .word 0xc6c7c9, 0xecf0ef, 0xcccdcf, 0xd3d5d4, 0xe6e8e7, 0xdee0df, 0xdbdddc, 0xdbdddc # row 89 .word 0xd7d9d6, 0xd8dad7, 0xd9d9d7, 0xd9d9d7, 0xd9d9d7, 0xd8d8d6, 0xd7d7d5, 0xd6d6d4 # row 89 .word 0xd9d8d4, 0xd3d2d0, 0xd2d2d2, 0xc5c6c8, 0xc7cbce, 0xe7eef4, 0x8f989f, 0x525c66 # row 89 .word 0x57616d, 0x697583, 0x84909e, 0x919dab, 0x8c98a8, 0x85919f, 0x8c98a6, 0x9fa2ab # row 89 .word 0xd4c6c5, 0xd0bcb3, 0xb09c93, 0x9f8e86, 0xb9aaa3, 0xa59a94, 0xb6aeab, 0xb2aeab # row 89 .word 0xaaaaaa, 0x989da0, 0x8c959a, 0x89969e, 0x86949f, 0x7b8d9b, 0x788999, 0x7d8d9c # row 89 .word 0x798591, 0xe0e9f2, 0xd0d9e2, 0xd9e0ea, 0xd8dfe9, 0xdce3eb, 0xe1e6ec, 0xd4d9dd # row 89 .word 0xd9dde0, 0xdde1e2, 0xb8b9bb, 0xd8dad9, 0xd9dbd8, 0xe1e3e0, 0xdededc, 0xdfdfdd # row 89 .word 0xe1e1df, 0xdfdfdd, 0xdfdfdd, 0xe0e0de, 0xe3e3e1, 0xe4e4e2, 0xe2e2e0, 0xe0e0de # row 89 .word 0xdfdfdd, 0xdfdfdd, 0xdfdfdd # row 90 .word 0xeaeaea, 0xdddfdc, 0xd4d4d4, 0xd7d7d5, 0xebebe9, 0xdcdcda, 0xd6d6d4, 0xdcdcda # row 90 .word 0xd8d8d6, 0xd9d9d7, 0xd9d9d7, 0xd9d9d7, 0xd9d9d7, 0xd8d8d6, 0xd7d7d5, 0xd6d6d4 # row 90 .word 0xdad9d7, 0xd0cfcd, 0xd5d5d5, 0xc9cacc, 0xd4d8db, 0xcfd6dc, 0x565f66, 0x57616b # row 90 .word 0x6b7581, 0x808a96, 0x98a2ae, 0xa3adb9, 0x9ca5b4, 0x939da9, 0x9aa4b0, 0xacb0b9 # row 90 .word 0xd7ced1, 0xd8cdcb, 0xc0b6b4, 0x9f9795, 0xafa9a9, 0xa5a3a4, 0xb4b5b9, 0xa7acb0 # row 90 .word 0x98a1a6, 0x95a2aa, 0x91a2ac, 0x8d9fab, 0x899caa, 0x879cad, 0x8ba0b3, 0x90a3b4 # row 90 .word 0x798593, 0x7f8993, 0xd9e3ed, 0xd3dce5, 0xe4edf6, 0xdae3ea, 0xd2d9df, 0xe0e8eb # row 90 .word 0xd5dadd, 0xe6eaeb, 0xaeafb1, 0xdadcdb, 0xdcdedb, 0xe1e3e0, 0xddded9, 0xe0e1dc # row 90 .word 0xe0e0de, 0xe0e0de, 0xe0e0de, 0xe1e1df, 0xe3e3e1, 0xe3e3e1, 0xe2e2e0, 0xe0e0de # row 90 .word 0xe0e0de, 0xdededc, 0xdddddb # row 91 .word 0xd0d0ce, 0xcbcbc9, 0xebebe9, 0xd6d6d4, 0xdddddb, 0xdddddb, 0xdcdcda, 0xd9d9d7 # row 91 .word 0xd8d8d6, 0xd9d9d7, 0xd9d9d7, 0xd9d9d7, 0xd9d9d7, 0xd8d8d6, 0xd7d7d5, 0xd6d6d4 # row 91 .word 0xd2d1cf, 0xd3d3d3, 0xcfd0d2, 0xd4d8db, 0xdde2e6, 0x858c92, 0x6b727a, 0x818a93 # row 91 .word 0x96a0aa, 0xa1abb5, 0xafb9c5, 0xb3bbc6, 0xa7afba, 0x9aa0ac, 0x999fab, 0xa3a6af # row 91 .word 0xc4c2c7, 0xdcd7db, 0xc4c2c5, 0xb4b3b8, 0x9a9da2, 0xaeb3b9, 0xa4adb4, 0x9aa7af # row 91 .word 0x98a9b1, 0x9dafb9, 0x9bafba, 0x93a6b4, 0x8fa5b3, 0x95aabb, 0x96abbc, 0x95a6b8 # row 91 .word 0x97a5b2, 0x828c98, 0x858f9b, 0xe6f0fa, 0xd7dfea, 0xd7e0e9, 0xd8dfe7, 0xdee5eb # row 91 .word 0xd4d9dd, 0xe7ecef, 0xa9aaac, 0xdcdedd, 0xdfe1de, 0xe1e3e0, 0xddded9, 0xe0e1dc # row 91 .word 0xe0e0de, 0xe0e0de, 0xe1e1df, 0xe1e1df, 0xe2e2e0, 0xe2e2e0, 0xe1e1df, 0xe0e0de # row 91 .word 0xdfdfdd, 0xdddddb, 0xdadad8 # row 92 .word 0xe3e2de, 0xd0cfcb, 0xeae9e5, 0xcbcac6, 0xd5d4d0, 0xe8e7e3, 0xe3e3e1, 0xd5d5d3 # row 92 .word 0xd8d8d6, 0xd9d9d7, 0xd9d9d7, 0xd9d9d7, 0xd9d9d7, 0xd8d8d6, 0xd6d8d5, 0xd5d7d4 # row 92 .word 0xcecece, 0xd9d9d9, 0xcecfd1, 0xd3d7da, 0xbdc2c6, 0x6f767c, 0x9ba2aa, 0xa8b1ba # row 92 .word 0xadb6bf, 0xafb8c1, 0xb5bdc8, 0xb9c0ca, 0xb6bac5, 0xabafb8, 0xa6a9b2, 0xa7a7af # row 92 .word 0xacabb3, 0xcac9d1, 0xceced6, 0xc1c6cc, 0x9ea7ae, 0xafbac0, 0xa1b0b7, 0x9aabb3 # row 92 .word 0xa5b8bf, 0xa6bac3, 0xa0b4bf, 0x98acb7, 0x9aadbb, 0xa3b5c3, 0xa0b2c0, 0x96a6b5 # row 92 .word 0x9ba7b5, 0x99a5b1, 0x8995a1, 0x87949d, 0xdae4ee, 0xd2dbe4, 0xdfe6ee, 0xd1d8de # row 92 .word 0xd4d9dd, 0xdee3e6, 0xafb0b2, 0xdddfde, 0xe1e1df, 0xe1e1df, 0xddded9, 0xe0e1dc # row 92 .word 0xe0e0de, 0xe1e1df, 0xe2e2e0, 0xe2e2e0, 0xe1e1df, 0xe1e1df, 0xe0e0de, 0xe0e0de # row 92 .word 0xe1e1df, 0xdfdfdd, 0xdcdcda # row 93 .word 0xe7e6e2, 0xd0cfcb, 0xe2e1dd, 0xd8d7d3, 0xdcdbd7, 0xe4e3df, 0xdadad8, 0xdbdbd9 # row 93 .word 0xd8d8d6, 0xd9d9d7, 0xd9d9d7, 0xd9d9d7, 0xd9d9d7, 0xd8d8d6, 0xd6d8d5, 0xd5d7d4 # row 93 .word 0xd4d4d4, 0xd9dbda, 0xd1d5d6, 0xc6cacd, 0x91969a, 0xa2a7ad, 0xb2b9c1, 0xb5bec5 # row 93 .word 0xb0b9c2, 0xafb6c0, 0xb3bac4, 0xbdc1ca, 0xc2c5ce, 0xbfbfc7, 0xbabac2, 0xb8b8c0 # row 93 .word 0x9e9ea8, 0xa6a9b2, 0xcdd1da, 0xb5bcc4, 0xadb7c0, 0xa4b3ba, 0xaabbc3, 0xa0b3ba # row 93 .word 0xafc3ca, 0xa9bdc6, 0xa1b3bd, 0x9dafb9, 0xa5b6c0, 0xb0bec9, 0xacb8c4, 0xa0acb8 # row 93 .word 0x9fabb9, 0x99a5b3, 0x96a2b0, 0x8e9aa6, 0x9aa4ae, 0xe6f0f9, 0xcad3dc, 0xdce3e9 # row 93 .word 0xd8dde1, 0xcbd0d3, 0xbfc0c2, 0xdfe1e0, 0xe2e2e2, 0xe0e0de, 0xdedfda, 0xdedfda # row 93 .word 0xe0e0de, 0xe2e2e0, 0xe3e3e1, 0xe3e3e1, 0xe1e1df, 0xe0e0de, 0xe0e0de, 0xe0e0de # row 93 .word 0xe3e3e1, 0xe2e2e0, 0xe0e0de # row 94 .word 0xd2cfca, 0xd3d0cb, 0xdddcd8, 0xe6e5e1, 0xdeddd9, 0xdddcd8, 0xd2d1cd, 0xdfdeda # row 94 .word 0xd8d8d6, 0xd9d9d7, 0xd9d9d7, 0xd9d9d7, 0xd9d9d7, 0xd8d8d6, 0xd6d8d7, 0xd5d7d6 # row 94 .word 0xd6d7d9, 0xd6d7d9, 0xd6dadd, 0xc0c4c7, 0x9da2a6, 0xc1c6cc, 0xb6bdc5, 0xb8bfc7 # row 94 .word 0xc7ced6, 0xc3cad2, 0xc4c8d1, 0xc7cad1, 0xc5c6cb, 0xbdbcc1, 0xb6b4b9, 0xb3b2b8 # row 94 .word 0xacacb6, 0x9a9ca8, 0xbec2cd, 0xaeb7c0, 0xaab7bf, 0xa5b4bb, 0xadbec6, 0xaec1c8 # row 94 .word 0xb4c7ce, 0xabbec4, 0xa3b4bb, 0xa5b4bb, 0xafbcc2, 0xb9c4ca, 0xb7c0c7, 0xb0b9c2 # row 94 .word 0xadb9c5, 0x9fadba, 0x9aa6b4, 0xa6b2be, 0xa2acb6, 0x97a1aa, 0xe6eff8, 0xd7dee4 # row 94 .word 0xdce1e5, 0xb6bbbe, 0xd2d3d5, 0xdfe1e0, 0xe1e1e1, 0xdededc, 0xdfe0db, 0xddded9 # row 94 .word 0xe0e0de, 0xe2e2e0, 0xe4e4e2, 0xe3e3e1, 0xe0e0de, 0xdfdfdd, 0xdfdfdd, 0xe1e1df # row 94 .word 0xe2e2e0, 0xe2e2e0, 0xe1e1df # row 95 .word 0xd5d4d0, 0xe2e1dd, 0xd3d2d0, 0xdadad8, 0xd6d5d3, 0xe2e2e0, 0xd6d5d3, 0xd7d7d5 # row 95 .word 0xd8d8d6, 0xd9d9d7, 0xd9d9d7, 0xd9d9d7, 0xd9d9d7, 0xd8d8d6, 0xd6d8d5, 0xd5d7d6 # row 95 .word 0xd4d6d5, 0xd3d4d6, 0xd8d9db, 0xc5c9cc, 0xcccfd4, 0xb4b7bc, 0xbcc1c7, 0xbec3c9 # row 95 .word 0xc2c7cd, 0xc2c7cd, 0xc7cad1, 0xcccdd2, 0xcac9ce, 0xc3c2c7, 0xc2c0c5, 0xc4c2c7 # row 95 .word 0xc5c5cd, 0xa6aab3, 0xacb3bb, 0xbac3ca, 0xa2adb3, 0xb5c4c9, 0xabbcc3, 0xbecfd6 # row 95 .word 0xb8cace, 0xafbec3, 0xa8b5bb, 0xadb8bc, 0xb6bfc4, 0xbbc2c8, 0xbdc2c6, 0xbcc1c7 # row 95 .word 0xb2bcc6, 0xb2beca, 0xacb6c2, 0x9aa4ae, 0x959ea7, 0xa1aab1, 0xadb4ba, 0xe6edf3 # row 95 .word 0xdee3e7, 0xa9adb0, 0xdedfe1, 0xe0e2e1, 0xe0e0e0, 0xdddddb, 0xe0e0de, 0xdcdcda # row 95 .word 0xe0e0de, 0xe2e2e0, 0xe5e5e3, 0xe3e3e1, 0xe0e0de, 0xdededc, 0xdfdfdd, 0xe1e1df # row 95 .word 0xdededc, 0xdededc, 0xdfdfdd # row 96 .word 0xd4d4d6, 0xd6d6d8, 0xd9d9d9, 0xdadcdb, 0xdbdbdb, 0xd9dbda, 0xd7d7d7, 0xd5d7d6 # row 96 .word 0xd6d8d7, 0xd7d9d8, 0xd9dbd8, 0xdadcd9, 0xdadcd9, 0xd9dbd8, 0xd7d9d6, 0xd6d8d5 # row 96 .word 0xd5d5d5, 0xd4d4d4, 0xd3d3d3, 0xd2d3d5, 0xd0d1d3, 0xcccdcf, 0xc6c7cb, 0xc1c2c6 # row 96 .word 0xbbbcc0, 0xbebfc3, 0xc3c4c8, 0xcac9ce, 0xcecdd2, 0xcccbd0, 0xc8c7cc, 0xc3c2c8 # row 96 .word 0xbec1c6, 0xbec3c9, 0xaab1b7, 0xb2b9bf, 0xb0b9be, 0xbbc6ca, 0xb3c1c4, 0xc3d1d4 # row 96 .word 0xc0cbcf, 0xb6c1c5, 0xb2bbc0, 0xb8c0c3, 0xbfc4c8, 0xbec1c6, 0xc0c1c6, 0xc0c3c8 # row 96 .word 0xc0c5cb, 0xb7bec4, 0xb7bcc2, 0xb6bbc1, 0xa8adb1, 0x9ba0a4, 0xa9adb0, 0xc2c6c9 # row 96 .word 0xc4c8cb, 0xcccdcf, 0xd6d7d9, 0xe0e0e0, 0xe3e3e3, 0xdfdfdf, 0xdadada, 0xd9d9d9 # row 96 .word 0xe2e2e2, 0xe4e4e4, 0xe3e3e3, 0xdedede, 0xdddddd, 0xe0e0e0, 0xe3e3e3, 0xe2e2e2 # row 96 .word 0xdcdcdc, 0xdedede, 0xdfdfdf # row 97 .word 0xd4d5d9, 0xd6d7db, 0xd8d9db, 0xdadbdd, 0xdbdcde, 0xd9dadc, 0xd7d9d8, 0xd6d8d7 # row 97 .word 0xd6d8d7, 0xd7d9d8, 0xd9dbd8, 0xdadcd9, 0xdadcd9, 0xd9dbd8, 0xd7d9d4, 0xd6d8d3 # row 97 .word 0xd4d4d4, 0xd3d3d3, 0xd2d2d2, 0xd2d2d2, 0xd2d2d2, 0xcfcfcf, 0xcbcbcd, 0xc8c8ca # row 97 .word 0xc3c3c5, 0xc3c3c5, 0xc4c3c8, 0xc8c7cc, 0xcac9ce, 0xcbcacf, 0xc9c8ce, 0xc6c7cc # row 97 .word 0xc2c5ca, 0xc4c9cd, 0xb4bcbf, 0xc0c8cb, 0xbec8ca, 0xc7d1d3, 0xbcc7c9, 0xc8d3d5 # row 97 .word 0xbac4c6, 0xb4bec0, 0xb6bbbf, 0xbbc0c4, 0xc2c3c8, 0xc1c2c7, 0xc3c2c8, 0xc5c6cb # row 97 .word 0xbfc2c7, 0xbbc0c4, 0xbdc1c4, 0xbfc3c6, 0xb7bbbe, 0xaaaeb1, 0xabacae, 0xb3b4b6 # row 97 .word 0xbcbdbf, 0xcfd0d2, 0xdcdcdc, 0xdbdbdb, 0xdadada, 0xdfdfdf, 0xe0e0e0, 0xd9d9d9 # row 97 .word 0xe2e2e2, 0xe4e4e4, 0xe2e2e2, 0xdddddd, 0xdcdcdc, 0xe0e0e0, 0xe2e2e2, 0xe1e1e1 # row 97 .word 0xdcdcdc, 0xdedede, 0xe0e0e0 # row 98 .word 0xd5d6da, 0xd7d8dc, 0xd9dadc, 0xdbdcde, 0xdcdddf, 0xdbdcde, 0xd9dbda, 0xd7d9d8 # row 98 .word 0xd7d9d8, 0xd8dad9, 0xd9dbd8, 0xdadcd9, 0xdadcd9, 0xd9dbd8, 0xd8dad5, 0xd7d9d4 # row 98 .word 0xd4d4d4, 0xd2d2d2, 0xd1d1d1, 0xd1d1d1, 0xd3d3d3, 0xd3d3d3, 0xd1d1d3, 0xcfcfd1 # row 98 .word 0xcbcbcd, 0xc9c9cb, 0xc6c5ca, 0xc6c5ca, 0xc7c6cb, 0xcac9ce, 0xcbcad0, 0xc9cacf # row 98 .word 0xc4c7cc, 0xc9ced2, 0xbec6c9, 0xcdd5d8, 0xccd6d8, 0xd1dbdd, 0xc0cbcd, 0xc8d3d5 # row 98 .word 0xb6c0c2, 0xb6c0c2, 0xbcc1c5, 0xc1c6ca, 0xc5c6cb, 0xc5c6cb, 0xc8c7cd, 0xcccdd2 # row 98 .word 0xc2c5ca, 0xc1c6ca, 0xc3c7ca, 0xc3c7ca, 0xc3c7ca, 0xbdc1c4, 0xb7b8ba, 0xb0b1b3 # row 98 .word 0xbebfc1, 0xd8d9db, 0xe4e4e4, 0xd8d8d8, 0xd4d4d4, 0xe0e0e0, 0xe3e3e3, 0xd9d9d9 # row 98 .word 0xe1e1e1, 0xe3e3e3, 0xe0e0e0, 0xdbdbdb, 0xdbdbdb, 0xdfdfdf, 0xe1e1e1, 0xdfdfdf # row 98 .word 0xdbdbdb, 0xdddddd, 0xe0e0e0 # row 99 .word 0xd7d8dc, 0xd8d9dd, 0xdadbdd, 0xdcdddf, 0xdcdddf, 0xdbdcde, 0xdadcdb, 0xd9dbda # row 99 .word 0xd7d9d8, 0xd8dad9, 0xd9dbd8, 0xdadcd9, 0xdadcd9, 0xd9dbd8, 0xd8dad5, 0xd7d9d4 # row 99 .word 0xd6d6d6, 0xd4d4d4, 0xd1d1d1, 0xd1d1d1, 0xd3d3d3, 0xd4d4d4, 0xd5d5d7, 0xd4d4d6 # row 99 .word 0xd1d1d3, 0xcdcdcf, 0xc9c8cd, 0xc7c6cb, 0xc8c7cc, 0xcac9ce, 0xcbcad0, 0xcacbd0 # row 99 .word 0xc4c7cc, 0xcacfd3, 0xc0c8cb, 0xd1d9dc, 0xd1dbdd, 0xd5dfe1, 0xc1ccce, 0xc6d1d3 # row 99 .word 0xb7c1c3, 0xbcc6c8, 0xc6cbcf, 0xc9ced2, 0xcacbd0, 0xc9cacf, 0xcdccd2, 0xd1d2d7 # row 99 .word 0xc8cbd0, 0xc9ced2, 0xc7cbce, 0xc1c5c8, 0xc4c8cb, 0xcaced1, 0xc9cacc, 0xc0c1c3 # row 99 .word 0xcecfd1, 0xdfe0e2, 0xe7e7e7, 0xdcdcdc, 0xd8d8d8, 0xe0e0e0, 0xe1e1e1, 0xd9d9d9 # row 99 .word 0xe2e2e2, 0xe2e2e2, 0xdfdfdf, 0xdadada, 0xdadada, 0xdedede, 0xdfdfdf, 0xdcdcdc # row 99 .word 0xdadada, 0xdddddd, 0xe0e0e0 .end
source_codes/s/asmsim_examples.s/pointer.s
/************************************************ The MIPS ASM code shown here is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ /* main() { int num; // an integer variable num int *ptr; // a pointer variable ptr pointing to num num = 1; // let the value of num be a 1 ptr = # // let the value of ptr be the address of num printf ("The address of num is %p\n", ptr); // print ptr out } */ .data # data segment $LC0: # address of string .ascii "The address of num is %p\n" # string .text # code segment main: # program entry subi $sp, $sp, 32 # reserve stack space sw $ra, 24($sp) # save return address li $2, 0x00000001 # num = 1 sw $2, 16($sp) # store num into stack la $4, $LC0 # $4: address of string addi $5, $sp, 16 # $5: ptr = &num jal printf # call printf lw $ra, 24($sp) # restore return address addi $sp, $sp, 32 # release stack space jr $ra # return to operating system .end # end of program
source_codes/s/asmsim_examples.s/printf.s
/* * printf.s * The printf() function prints output to STDOUT, according * to format and other arguments passed to printf(). * Inputs: $4: address of the string in which %d, $x, ... may * be included. The corresponding data are given in $5, $6, ... * The current version of this simulator supports %d, %x, and %s. */ .text # code segment main: # program entry subi $sp, $sp, 64 # reserve stack space sw $ra, 60($sp) # save return address sw $fp, 56($sp) # save frame pointer move $fp, $sp # new frame pointer user_main: la $4, print_dec # prepare to print out la $6, a_word # address of the word lw $5, 0($6) # load the word move $6, $5 # the same jal printf # print out in dec print_out_in_hexadecimal: la $4, print_hex # prepare to print out la $6, a_word # address of the word lw $5, 0($6) # load the word move $6, $5 # the same jal printf # print out in hex print_out_in_string: la $4, print_ascii # prepare to print out la $6, a_word # address of the word lw $5, 0($6) # load the word jal printf # print out in string return_to_caller(os): # exit(); move $sp, $fp # restore stack pointer lw $fp, 56($sp) # restore frame pointer lw $ra, 60($sp) # restore return address addi $sp, $sp, 64 # release stack space jr $ra # return to operating system .data # data segment print_dec: # a string address .ascii "0x%x in decimal: %d\n" print_hex: # a string address .ascii "0x%x in hexadecimal: 0x%x\n" print_ascii: # a string address .ascii "0x%x in string: %s\n" a_word: # the word address .word 0x476f6f64 # the word .end
source_codes/s/asmsim_examples.s/putchar.s
/* * getchar.s * getchar(): gets a character from STDIN * Output: $2: the ASCII of the character */ .text # code segment main: # program entry subi $sp, $sp, 64 # reserve stack space sw $ra, 60($sp) # save return address sw $fp, 56($sp) # save frame pointer move $fp, $sp # new frame pointer user_main: la $4, input_char_msg # address of message jal printf # print out message jal getchar # input a character la $4, a_word # address of word sw $2, 0($4) # store the character print_out_the_string: la $4, output_msg # output message address jal printf # print out message move $4, $2 # prepare to print jal putchar # print out character la $4, enter # the place of the string [enter] jal printf # print out message return_to_caller(os): # exit(); move $sp, $fp # restore stack pointer lw $fp, 56($sp) # restore frame pointer lw $ra, 60($sp) # restore return address addi $sp, $sp, 64 # release stack space jr $ra # return to operating system .data # data segment input_char_msg: .ascii "Input a character (no need to press [Enter] key): " a_word: # the word address .word 0 # the word output_msg: .ascii "The character you inputted is " enter: .ascii "\n" # the character [enter] .end
source_codes/s/asmsim_examples.s/README.txt
Please download the newest version of AsmSim.jar from http://cis.k.hosei.ac.jp/~yamin/asm/
source_codes/s/asmsim_examples.s/recursive.s
/* * recursive.s * This example shows the recursive call with Fibonacci Numbers. * A recursive call is one where procedure A calls itself * or calls procedure B which then calls procedure A again. * The Fibonacci numbers are the numbers in the following sequence: * 0,1,1,2,3,5,8,13,21,34,55,89,144,..., i.e. f(n) = f(n-2) + f(n-1) */ .text # code segment main: # program entry subu $sp, $sp, 32 # reserve stack space sw $ra, 28($sp) # save return address sw $fp, 24($sp) # save frame pointer move $fp, $sp # new frame pointer user_main: # f = fib(n) for n: [0, 20] li $2, -1 # a while guard for inputting n sw $2, 16($fp) # place for storing n la $4, what_is_this # show it is a fibonacci calc. jal printf # print out check_n: # n: [0, 20] ? lw $2, 16($fp) # if n bltz $2, input_n # < 0, input again lw $2, 16($fp) # if n slt $3, $2, 21 # >= 21 beq $3, $0, input_n # input again j n_is_ok # n: [0, 20] input_n: # try to input n la $4, input_msg # address of input message jal printf # print out la $4, data_format # in dec format addu $5, $fp, 16 # place for storing n jal scanf # input n j check_n # to check n n_is_ok: # ready to call lw $4, 16($fp) # fib(n) jal fib # call fib function la $4, result_msg # address of result message lw $5, 16($fp) # n move $6, $2 # f = fib(n) jal printf # print out result return_to_caller(os): # exit(); move $sp, $fp # restore stack pointer lw $ra, 28($sp) # restore return address lw $fp, 24($sp) # restore frame pointer addu $sp, $sp, 32 # release stack space jr $ra # return to operating system fib: # f = fib(n)function entry subu $sp, $sp, 32 # reserve stack space sw $ra, 24($sp) # save return address sw $fp, 20($sp) # save frame pointer sw $16, 16($sp) # store f = fib(n - 1) move $fp, $sp # new frame pointer sw $4, 32($fp) # store n lw $2, 32($fp) # load n bne $2, $0, check_1 # if (n != 0) check 1 li $2, 0x00000000 # else j return_to_caller # return(0) check_1: # check if n == 1 lw $2, 32($fp) # if n li $3, 0x00000001 # != 1 bne $2, $3, go_on # go on li $2, 0x00000001 # else j return_to_caller # return(1) go_on: # start recursive call lw $3, 32($fp) # load n subu $2, $3, 1 # n - 1 move $4, $2 # fib(n - 1) jal fib # recursive call move $16, $2 # f = fib(n - 1) lw $3, 32($fp) # n subu $2, $3, 2 # n - 2 move $4, $2 # fib(n - 2) jal fib # recursive call addu $3, $16, $2 # fib(n) = fib(n -1) + fib(n - 2) move $2, $3 # f = fib(n) return_to_caller: # return() move $sp, $fp # restore stack pointer lw $ra, 24($sp) # restore return address lw $fp, 20($sp) # restore frame pointer lw $16, 16($sp) # restore f = fib(n - 1) addu $sp, $sp, 32 # release stack space jr $ra # return to caller .data # data segment what_is_this: .ascii "Calculating Fibonacci number by recursive calls\n" input_msg: .ascii "Input an integer [ 0 - 20 ]: " data_format: .ascii "%d" # in dec format result_msg: .ascii "The Fibonacci number of %d is %d\n" .end
source_codes/s/asmsim_examples.s/root_nonrestoring.s
/************************************************ The MIPS ASM code shown here is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ /* // Non-Restoring Square Root, Copyright by Li Yamin, [email protected] #include <stdio.h> // root_nonrestoring.c unsigned squart(unsigned d, int *remainder) { unsigned q = 0; // q: 16-bit unsigned integer (root) int r = 0; // r: 17-bit integer (remainder) int i; for (i = 15; i >= 0; i--) { printf("%02d: q=%04x ", i, q); if (r >= 0) { r = ((r << 2) | ((d >> (i+i)) & 3)) - ((q << 2) | 1); // -q01 printf("r=((r<<2)|((d>>(i+i))&3))-((q<<2)|1)=%08x ", r); } else { r = ((r << 2) | ((d >> (i+i)) & 3)) + ((q << 2) | 3); // +q11 printf("r=((r<<2)|((d>>(i+i))&3))+((q<<2)|3)=%08x ", r); } if (r >= 0) {q = (q << 1) | 1; printf("q=q*2+1=%04x\n", q);} else {q = (q << 1) | 0; printf("q=q*2+0=%04x\n", q);} } if (r < 0) {r = r + ((q << 1) | 1);} // remainder adjusting *remainder = r; // return remainder return(q); // return root } int main() { unsigned radicand, root; int remainder; printf("Input an unsigned integer in hex (ex. c0000000): d = "); scanf("%x", &radicand); root = squart(radicand, & remainder); printf("hex: q = %08x, r = %08x, d = q*q + r = %08x\n", root, remainder, root * root + remainder); printf("dec: q = %08d, r = %08d, d = q*q + r = %u\n", root, remainder, root * root + remainder); } */ .data $LC0: .ascii "%02d: q=%04x " $LC1: .ascii "r=((r<<2)|((d>>(i+i))&3))-((q<<2)|1)=%08x " $LC2: .ascii "r=((r<<2)|((d>>(i+i))&3))+((q<<2)|3)=%08x " $LC3: .ascii "q=q*2+1=%04x\n" $LC4: .ascii "q=q*2+0=%04x\n" $LC5: .ascii "Input an unsigned integer in hex (ex. c0000000): d = " $LC6: .ascii "%x" $LC7: .ascii "hex: q = %08x, r = %08x, d = q*q + r = %08x\n" $LC8: .ascii "dec: q = %08d, r = %08d, d = q*q + r = %u\n" .text squart: subi $sp, $sp, 40 # sw $19, 28($sp) # move $19, $4 # sw $20, 32($sp) # move $20, $5 # sw $17, 20($sp) # move $17, $0 # sw $16, 16($sp) # move $16, $0 # sw $18, 24($sp) # li $18, 0x0000000f # sw $31, 36($sp) # $L5: la $4, $LC0 # move $5, $18 # move $6, $17 # jal printf # bltz $16, $L6 # sll $2, $16, 2 # sll $3, $18, 1 # srl $3, $19, $3 # andi $3, $3, 0x0003 # or $2, $2, $3 # sll $3, $17, 2 # ori $3, $3, 0x0001 # subu $16, $2, $3 # la $4, $LC1 # j $L12 # $L6: sll $2, $16, 2 # sll $3, $18, 1 # srl $3, $19, $3 # andi $3, $3, 0x0003 # or $2, $2, $3 # sll $3, $17, 2 # ori $3, $3, 0x0003 # addu $16, $2, $3 # la $4, $LC2 # $L12: move $5, $16 # jal printf # bltz $16, $L8 # sll $2, $17, 1 # ori $17, $2, 0x0001 # la $4, $LC3 # j $L13 # $L8: sll $17, $17, 1 # la $4, $LC4 # $L13: move $5, $17 # jal printf # subi $18, $18, 1 # bgez $18, $L5 # bgez $16, $L11 # sll $2, $17, 1 # ori $2, $2, 0x0001 # addu $16, $16, $2 # $L11: sw $16, 0($20) # move $2, $17 # lw $31, 36($sp) # lw $20, 32($sp) # lw $19, 28($sp) # lw $18, 24($sp) # lw $17, 20($sp) # lw $16, 16($sp) # addi $sp, $sp, 40 # jr $31 # main: subi $sp, $sp, 40 # sw $31, 32($sp) # sw $17, 28($sp) # sw $16, 24($sp) # la $4, $LC5 # jal printf # la $4, $LC6 # addi $5, $sp, 16 # jal scanf # lw $4, 16($sp) # addi $5, $sp, 20 # jal squart # move $16, $2 # mult $16, $16 # mflo $17 # lw $7, 20($sp) # la $4, $LC7 # move $5, $16 # move $6, $7 # addu $7, $17, $7 # jal printf # lw $7, 20($sp) # la $4, $LC8 # move $5, $16 # move $6, $7 # addu $7, $17, $7 # jal printf # lw $31, 32($sp) # lw $17, 28($sp) # lw $16, 24($sp) # addi $sp, $sp, 40 # jr $31 # .end
source_codes/s/asmsim_examples.s/scanf.s
/* * scanf.s * The scanf() function reads input from STDIN, according * to format and other arguments passed to scanf(). * Inputs: $4: address of the string: %d, $x, or %s * $5: the address where the value is stored * The current version of this simulator supports %d, %x, and %s. */ .text # code segment main: # program entry subi $sp, $sp, 64 # reserve stack space sw $ra, 60($sp) # save return address sw $fp, 56($sp) # save frame pointer move $fp, $sp # new frame pointer user_main: la $4, input_msg_dec # input message address jal printf # print out message input_an_integer_dec: la $4, format_dec # %d: decimal format la $5, n # n: the place to store integer jal scanf # input integer in dec print_out_the_integer_dec: la $4, output_msg_dec # output message address la $5, n # n: the place of the integer lw $5, 0($5) # load the integer jal printf # print out message print_out_msg_hex: la $4, input_msg_hex # input message address jal printf # print out message input_an_integer_hex: la $4, format_hex # %x: hexadecimal format la $5, n # n: the place to store integer jal scanf # input integer in hex print_out_the_integer_hex: la $4, output_msg_hex # output message address la $5, n # n: the place of the integer lw $5, 0($5) # load the integer jal printf # print out message print_out_msg_str: la $4, input_msg_str # input message address jal printf # print out message input_a_string: la $4, format_str # %s: string format la $5, s # s: the place to store string jal scanf # input string print_out_the_string: la $4, output_msg_str # output message address jal printf # print out message la $4, s # s: the place of the string jal printf # print out message la $4, enter # the place of the string [enter] jal printf # print out message print_out_the_string_all_in_one: la $4, output_msg_s1 # output message address la $5, s # s: the place of the string jal printf # print out message return_to_caller(os): # exit() move $sp, $fp # restore stack pointer lw $fp, 56($sp) # restore frame pointer lw $ra, 60($sp) # restore return address addi $sp, $sp, 64 # release stack space jr $ra # return to operating system .data # data segment input_msg_dec: .ascii "Input an integer: " input_msg_hex: .ascii "Input an integer in hex: " input_msg_str: .ascii "Input a string: " format_dec: .ascii "%d" # "for decimal" format_hex: .ascii "%x" # "for hexadecimal" format_str: .ascii "%s" # "for string" output_msg_dec: .ascii "The integer you inputted is %d\n" output_msg_hex: .ascii "The integer you inputted is %x\n" output_msg_str: .ascii "The string you inputted is " output_msg_s1: .ascii "The string you inputted is %s (1 printf call)\n" n: .word 0 # the integer enter: .ascii "(3 printf calls)\n" # the character [enter] s: .ascii " " # the string in the last .end
source_codes/s/asmsim_examples.s/sleep.s
/* * sleep.s * sleep(): suspends execution for an interval of time * Input: $4: interval in ms */ .text # code segment main: # program entry subi $sp, $sp, 64 # reserve stack space sw $ra, 60($sp) # save return address sw $fp, 56($sp) # save frame pointer move $fp, $sp # new frame pointer user_main: li $4, 5 # n = 5 sw $4, 52($fp) # store n to stack tired: la $4, message # address of message jal printf # print out message sleeping: li $4, 2000 # sleep time (ms) jal sleep # do sleep woke_up: lw $3, 52($fp) # load n subi $3, $3, 1 # n-- sw $3, 52($fp) # store i bgtz $3, tired # sleep again return_to_caller(os): # exit(); move $sp, $fp # restore stack pointer lw $fp, 56($sp) # restore frame pointer lw $ra, 60($sp) # restore return address addi $sp, $sp, 64 # release stack space jr $ra # return to operating system .data # data segment message: # program entry .ascii "Zzzz...(2s)\n" .end
source_codes/s/asmsim_examples.s/sprintf.s
/* * sprintf.s * The fprintf() function prints output to a buffer, according * to format and other arguments passed to sprintf(). * Inputs: $4: the buffer address, $5: address of the string in * which %d, $x, ... may be included. The corresponding data are * given in $6, $7, ... Return: $2: the number of characters. * The current version of this simulator supports %d, %x, and %s. */ .text # code segment main: # program entry subu $sp, $sp, 104 # reserve stack space sw $ra, 100($sp) # save return address sw $fp, 96($sp) # save frame pointer move $fp, $sp # new frame pointer user_main: li $2, 0x7fffffff # translate 0x7fffffff sw $2, 16($fp) # and li $2, -1 # -1 sw $2, 20($fp) # to string addu $2, $fp, 24 move $4, $2 # result string address la $5, data_format # in dec and hex format lw $6, 16($fp) # 0x7fffffff lw $7, 20($fp) # -1 jal sprintf # do translation sw $2, 88($fp) # str length in $2 addu $2, $fp, 24 la $4, string # printf string address move $5, $2 # result string address lw $6, 88($fp) # length jal printf # print out return_to_caller(os): # exit(); move $sp, $fp # restore stack pointer lw $ra, 100($sp) # restore frame pointer lw $fp, 96($sp) # restore return address addu $sp, $sp, 104 # release stack space jr $ra # return to operating system .data # data segment data_format: # for sprintf .ascii "%d, %x" # format string: # for printf .ascii "str = "%s", length = %d\n" # printf .end
source_codes/s/asmsim_examples.s/subroutine_call.s
/************************************************ The MIPS ASM code shown here is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ /* int sum(int *array, int n) { int i; int total = 0; for (i = 0; i < n; i++) { total += array[i]; } return(total); } int main() { int a[] = {1, 2, 3}; printf ("The sum is %d\n", sum(a, 3)); return(0); } */ .data # data segment $LC0: # address of array a .word 1, 2, 3 # elements of array a $LC1: # address of string .ascii "The sum is %d\n" # string .text # code segment sum: # entry of subroutine sum subi $sp, $sp, 8 # reserve stack space move $3, $0 # i = 0 move $6, $0 # total = 0 blez $5, $L3 # goto $L3 if n <= 0 $L5: # for loop sll $2, $3, 2 # i * 4 (4 bytes per word) add $2, $2, $4 # base address + i * 4 lw $2, 0($2) # load a[i] addi $3, $3, 1 # i++ add $6, $6, $2 # total += a[i] bne $3, $5, $L5 # goto $L5 if i != n $L3: # end of loop move $2, $6 # move total to $2 addi $sp, $sp, 8 # release stack space jr $ra # return from subroutine main: # program entry subi $sp, $sp, 40 # reserve stack space sw $ra, 32($sp) # save return address la $5, $LC0 # address of array a lw $2, 0($5) # load a[0] lw $3, 4($5) # load a[1] lw $4, 8($5) # load a[2] sw $2, 16($sp) # store a[0] to stack sw $3, 20($sp) # store a[1] to stack sw $4, 24($sp) # store a[2] to stack addi $4, $sp, 16 # $4: address of a[0] li $5, 3 # $5: n = 3 jal sum # call subroutine sum la $4, $LC1 # $4: address of string move $5, $2 # $5: total jal printf # call printf move $2, $0 # return value 0 lw $ra, 32($sp) # restore return address addi $sp, $sp, 40 # release stack space jr $ra # return to operating system .end # end of program
source_codes/s/asmsim_examples.s/vram.s
/* * vram.s * writes/reads pixels to/from vram directly with sw/lw instructions * video ram address: (y << 10) + x; x: 0 - 639; y: 0 - 479 * pixel: (r << 16) + (g << 8) + b; 24-bit true color */ `define _Video_RAM 0xd0000000 # 0xd0000000 - 0xd007ffff .text # code segment main: # program entry subi $sp, $sp, 64 # reserve stack space sw $ra, 60($sp) # save return address sw $fp, 56($sp) # save frame pointer move $fp, $sp # new frame pointer user_main: jal refresh_vga_manu # refresh VGA manually # jal refresh_vga_auto # refresh automatically la $4, _Video_RAM # vram start address write_pixels: sll $5, $0, 0 # color = black li $6, 0 # for (y = 0; y < 240(480); y++) write_a_row: li $7, 0 # for (x = 0; x < 640; x++) write_a_col: sll $8, $6, 10 # y << 10 add $8, $8, $7 # + x add $9, $4, $8 # + base sw $5, 0($9) # write pixel addi $7, $7, 1 # x++ addi $5, $5, 109 # 2^24/(640*480) = 54.613333 subi $8, $7, 640 # if (x < 640) bltz $8, write_a_col # goto next col jal paint # refresh VGA manually sleep_after_paint: move $10, $4 # save $4 li $4, 50 # sleep time (ms) jal sleep # do sleep move $4, $10 # restore $4 addi $6, $6, 1 # y++ subi $8, $6, 240 # if (y < 240 (480)) bltz $8, write_a_row # goto next row scroll_up: la $4, _Video_RAM # vram start address scroll_up_60_times: li $3, 0 # for (i = 0; i < 30; i++) scroll_up_one_time: li $6, 8 # for (y = 8; y < 240(480); y++) scroll_up_8rows: li $7, 0 # for (x = 0; x < 640; x++) scroll_up_a_col: sll $8, $6, 10 # y << 10 add $8, $8, $7 # + x add $9, $4, $8 # + base lw $5, 0($9) # read a pixel subi $8, $6, 8 # scroll up 8 rows sll $8, $8, 10 # y << 10 add $8, $8, $7 # + x add $9, $4, $8 # + base sw $5, 0($9) # write the pixel addi $7, $7, 1 # x++ subi $8, $7, 640 # if (x < 640) bltz $8, scroll_up_a_col # goto next col fill_8rows_with_black: la $14, _Video_RAM # vram start address sll $15, $0, 0 # black li $16, 232 # for (y = 472; y < 240(480); y++) black_a_row: li $17, 0 # for (x = 0; x < 640; x++) black_a_col: sll $18, $16, 10 # y << 10 add $18, $18, $17 # + x add $19, $14, $18 # + base sw $15, 0($19) # write pixel addi $17, $17, 1 # x++ subi $18, $17, 640 # if (x < 640) bltz $18, black_a_col # goto next col addi $16, $16, 1 # y++ subi $18, $16, 240 # if (y < 240(480)) bltz $18, black_a_row # goto next row addi $6, $6, 1 # y++ subi $8, $6, 240 # if (y < 240(480)) bltz $8, scroll_up_8rows # goto next row jal paint # refresh VGA manually sleep_for_a_while: move $10, $4 # save $4 li $4, 50 # sleep time (ms) jal sleep # do sleep move $4, $10 # restore $4 addi $3, $3, 1 # i++ subi $8, $3, 30 # if (i < 30(60)) bltz $8, scroll_up_one_time # goto next time return_to_caller(os): # exit(); move $sp, $fp # restore stack pointer lw $fp, 56($sp) # restore frame pointer lw $ra, 60($sp) # restore return address addi $sp, $sp, 64 # release stack space jr $ra # return to operating system .data # data segment .end
source_codes/s/display_scan_codes.s
/************************************************ The MIPS ASM code shown here is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ .text # code segment main: lui $3, 0xc000 # vram space: c0000000 - dfffffff lui $4, 0xa000 # i/o space: a0000000 - bfffffff read_kbd: lw $5, 0($4) # read kbd: {0,ready,byte} andi $6, $5, 0x100 # check if ready beq $6, $0, read_kbd # if no key pressed, wait andi $6, $5, 0xff # ready, get data srl $5, $6, 4 # first digit addi $7, $5, -10 srl $7, $7, 31 beq $7, $0, abcdef1 addi $5, $5, 0x30 # to ascii [0-9] j print1 abcdef1: addi $5, $5, 0x37 # to ascii [a-f] print1: jal display # display char andi $5, $6, 0xf # second digit addi $7, $5, -10 srl $7, $7, 31 beq $7, $0, abcdef2 addi $5, $5, 0x30 # to ascii [0-9] j print2 abcdef2: addi $5, $5, 0x37 # to ascii [a-f] print2: jal display # display char addi $5, $0, 0x20 # [Space] print3: jal display # display char j read_kbd # check next display: sw $5, 0($3) # to display addi $3, $3, 4 jr $ra .end
source_codes/s/i2c_eeprom.s
/************************************************ The MIPS ASM code shown here is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ .text 0 # 0: starting address of instruction memory main: ori $sp, $0, 0x0100 # stack pointer, 256-byte data memory lui $8, 0xc000 # vram space: c0000000 - dfffffff lui $9, 0xa001 # i/o space: a0000000 - bfffffff la $1, msg # address of data ori $4, $0, 0x0a55 # eeprom address ori $7, $0, 1 #45 # number of chars = 1 for simulation write_data: # write chars to i2c eeprom lw $6, 0($1) # 4 bytes (chars) srl $5, $6, 24 # 1st byte jal write_eeprom # write the byte to eeprom addi $7, $7, -1 # counter-- beq $7, $0, w_finished # if counter is 0, go to w_finished addi $4, $4, 1 # eeprom addr + 1 sll $5, $6, 8 # 2nd byte srl $5, $5, 24 # 2nd byte jal write_eeprom # write the byte to eeprom addi $7, $7, -1 # counter-- beq $7, $0, w_finished # if counter is 0, go to w_finished addi $4, $4, 1 # eeprom addr + 1 sll $5, $6, 16 # 3rd byte srl $5, $5, 24 # 3rd byte jal write_eeprom # write the byte to eeprom addi $7, $7, -1 # counter-- beq $7, $0, w_finished # if counter is 0, go to w_finished addi $4, $4, 1 # eeprom addr + 1 sll $5, $6, 24 # 4th byte srl $5, $5, 24 # 4th byte jal write_eeprom # write the byte to eeprom addi $7, $7, -1 # counter-- beq $7, $0, w_finished # if counter is 0, go to w_finished addi $4, $4, 1 # eeprom addr + 1 addi $1, $1, 4 # next word j write_data w_finished: ori $4, $0, 0x0a55 # eeprom address ori $7, $0, 1 #45 # number of chars = 1 for simulation read_data: jal read_eeprom # read a byte from i2c eeprom sw $2, 0($8) # to display on vga addi $8, $8, 4 # vram addr + 4 addi $4, $4, 1 # eeprom addr + 1 addi $7, $7, -1 # counter-- beq $7, $0, r_finished # if counter is 0, go to r_finished j read_data # continue to read r_finished: j r_finished # should return to os write_eeprom: # $4: addr, $5: data addi $sp, $sp, -16 # reserve stack space sw $ra, 12($sp) # save return address sw $fp, 08($sp) # save frame pointer move $fp, $sp # new frame pointer jal write_eeprom_addr # write eeprom addr jal wait_ready # wait for ready sw $5, 4($9) # send byte to store jal wait_ready # wait for ready sw $0, 12($9) # send stop bit move $sp, $fp # restore stack pointer lw $fp, 08($sp) # restore frame pointer lw $ra, 12($sp) # restore return address addi $sp, $sp, 16 # release stack space jr $ra # return read_eeprom: # $4, addr, $2: data (return value) addi $sp, $sp, -16 # reserve stack space sw $ra, 12($sp) # save return address sw $fp, 08($sp) # save frame pointer move $fp, $sp # new frame pointer jal write_eeprom_addr # write eeprom addr jal wait_ready # wait for ready sw $0, 0($9) # send repeat start bit ori $2, $0, 0xa1 # i2c eeprom slave addr, read jal wait_ready # wait for ready sw $2, 4($9) # send slave address, read ori $2, $0, 1 # not-ack jal wait_ready # wait for ready sw $2, 8($9) # go to RX state, not-ack jal wait_ready # wait for ready lw $2, 0($9) # get data of eeprom sw $0, 12($9) # send stop bit move $sp, $fp # restore stack pointer lw $fp, 08($sp) # restore frame pointer lw $ra, 12($sp) # restore return address addi $sp, $sp, 16 # release stack space jr $ra # return write_eeprom_addr: # $4: addr, $9: i/o addr addi $sp, $sp, -20 # reserve stack space sw $ra, 16($sp) # save return address sw $fp, 12($sp) # save frame pointer sw $6, 08($sp) # save $6 sw $2, 04($sp) # save $2 move $fp, $sp # new frame pointer jal wait_ready # wait for ready send_start: sw $0, 0($9) # send start bit ori $2, $0, 0xa0 # i2c eeprom slave addr, w jal wait_ready # wait for ready sw $2, 4($9) # send slave address, w jal wait_ready # wait for ready lw $6, 4($9) # get i2c status, check ack andi $6, $6, 0x08 # check rx_ack {0,0,x,0,rx_ack,xxx} bne $6, $0, send_start # if received not-ack srl $2, $4, 8 # high 8-bit eeprom addr andi $2, $2, 0x0f # high 4-bit eeprom addr = 0 sw $2, 4($9) # send eeprom high 8-bit addr andi $2, $4, 0xff # low 8-bit eeprom addr jal wait_ready # wait for ready sw $2, 4($9) # send eeprom low 8-bit addr move $sp, $fp # restore stack pointer lw $2, 04($sp) # restore $2 lw $6, 08($sp) # restore $6 lw $fp, 12($sp) # restore frame pointer lw $ra, 16($sp) # restore return address addi $sp, $sp, 20 # release stack space jr $ra # return wait_ready: # wait for ready addi $sp, $sp, -20 # reserve stack space sw $ra, 16($sp) # save return address sw $fp, 12($sp) # save frame pointer sw $6, 08($sp) # save $6 move $fp, $sp # new frame pointer check_status: lw $6, 4($9) # get i2c status andi $6, $6, 0x20 # check ready {0,0,ready,0,x,xxx} beq $6, $0, check_status # if not ready, continue to check move $sp, $fp # restore stack pointer lw $6, 08($sp) # restore $6 lw $fp, 12($sp) # restore frame pointer lw $ra, 16($sp) # restore return address addi $sp, $sp, 20 # release stack space jr $ra # return .data 0 # 0: starting address of data memory msg: # address of ascii characters .ascii "Computer Principles and Design in Verilog HDL" .end
source_codes/v/add.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module add (a, b, c, g, p, s); // adder and g, p input a, b, c; // inputs: a, b, c; output g, p, s; // outputs: g, p, s; assign s = a ^ b ^ c; // output: sum of inputs assign g = a & b; // output: carry generator assign p = a | b; // output: carry propagator endmodule
source_codes/v/add1.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module add1 (a,b,ci,s,co); // full adder, dataflow style input a, b, ci; // inputs: a, b, carry_in output s, co; // outputs: sum, carry_out assign s = a ^ b ^ ci; // sum of inputs assign co = a & b | b & ci | ci & a; // carry_out endmodule
source_codes/v/add1_tb.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ `timescale 1ns/1ns module add1_tb; reg a,b,ci; wire co,s; add1 i1 (a,b,ci,s,co); initial begin a = 0; b = 0; ci = 0; #8 $finish; end always #4 a = !a; always #2 b = !b; always #1 ci = !ci; endmodule
source_codes/v/add4.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module add4 (a,b,ci,s,co); // 4-bit adder using four add1 input [3:0] a, b; // inputs: a and b input ci; // input: carry_in output [3:0] s; // output: sum output co; // output: carry_out wire [2:0] c; // internal carries // add1 (a, b, ci, s, co); add1 a0 (a[0], b[0], ci, s[0], c[0]); // ci: ci; s: s[0]; co: c[0] add1 a1 (a[1], b[1], c[0], s[1], c[1]); // ci: c[0]; s: s[1]; co: c[1] add1 a2 (a[2], b[2], c[1], s[2], c[2]); // ci: c[1]; s: s[2]; co: c[2] add1 a3 (a[3], b[3], c[2], s[3], co); // ci: c[2]; s: s[3]; co: co endmodule
source_codes/v/addsub32.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module addsub32 (a,b,sub,s); // 32-bit adder/subtracter input [31:0] a, b; // inputs: a, b input sub; // sub == 1: s = a - b // sub == 0: s = a + b output [31:0] s; // output sum s // sub == 1: a - b = a + (-b) = a + not(b) + 1 = a + (b xor sub) + sub // sub == 0: a + b = a + b = a + b + 0 = a + (b xor sub) + sub wire [31:0] b_xor_sub = b ^ {32{sub}}; // (b xor sub) // cla32 (a, b, ci, s); cla32 as32 (a, b_xor_sub, sub, s); // b: (b xor sub); ci: sub endmodule
source_codes/v/addsub4.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module addsub4 (a,b,ci,sub,s,co); // 4-bit adder/subtracter input [3:0] a, b; // inputs: a, b input ci; // input: carry_in input sub; // input: sub==1: s=a-b-ci // input: sub==0: s=a+b+ci output [3:0] s; // output: sum output co; // output: carry_out // sub==1, ci==0: a-b-ci = a+(-b)-0 = a+(~b+1)-0 = a+(b^sub)+(ci^sub) // sub==1, ci==1: a-b-ci = a+(-b)-1 = a+(~b+1)-1 = a+(b^sub)+(ci^sub) // sub==0, ci==0: a+b+ci = a+ b +0 = a+ b +0 = a+(b^sub)+(ci^sub) // sub==0, ci==1: a+b+ci = a+ b +1 = a+ b +1 = a+(b^sub)+(ci^sub) wire [3:0] bx = b ^ {4{sub}}; // b xor sub wire cix = ci ^ sub; // ci xor sub wire [2:0] c; // internal carries // add1 (a, b, ci, s, co); add1 a0 (a[0], bx[0], cix, s[0], c[0]); // b: bx[0], ci: cix; co: c[0] add1 a1 (a[1], bx[1], c[0], s[1], c[1]); // b: bx[1], ci: c[0]; co: c[1] add1 a2 (a[2], bx[2], c[1], s[2], c[2]); // b: bx[2], ci: c[1]; co: c[2] add1 a3 (a[3], bx[3], c[2], s[3], co); // b: bx[3], ci: c[2]; co: co endmodule
source_codes/v/addsub4_tb.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ `timescale 1ns/1ns module addsub4_tb; reg [3:0] a,b; reg ci; reg sub; wire [3:0] s; wire co; addsub4 as4 (a,b,ci,sub,s,co); initial begin a = 4'h2; // +2 b = 4'h3; // +3 ci = 0; sub = 0; #20 a = 4'he; // -2 b = 4'hd; // -3 end always #5 ci = !ci; always #10 sub = !sub; endmodule
source_codes/v/alu.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module alu (a,b,aluc,r,z); // 32-bit alu with a zero flag input [31:0] a, b; // inputs: a, b input [3:0] aluc; // input: alu control: // aluc[3:0]: output [31:0] r; // output: alu result // x 0 0 0 ADD output z; // output: zero flag // x 1 0 0 SUB wire [31:0] d_and = a & b; // x 0 0 1 AND wire [31:0] d_or = a | b; // x 1 0 1 OR wire [31:0] d_xor = a ^ b; // x 0 1 0 XOR wire [31:0] d_lui = {b[15:0],16'h0}; // x 1 1 0 LUI wire [31:0] d_and_or = aluc[2]? d_or : d_and; // 0 0 1 1 SLL wire [31:0] d_xor_lui = aluc[2]? d_lui : d_xor; // 0 1 1 1 SRL wire [31:0] d_as, d_sh; // 1 1 1 1 SRA // addsub32 (a,b,sub, s); addsub32 as32 (a,b,aluc[2],d_as); // add/sub // shift (d,sa, right, arith, sh); shift shifter (b,a[4:0],aluc[2],aluc[3],d_sh); // shift // mux4x32 (a0, a1, a2, a3, s, y); mux4x32 res (d_as,d_and_or,d_xor_lui,d_sh,aluc[1:0],r); // alu result assign z = ~|r; // z = (r == 0) endmodule
source_codes/v/alu_ov.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module alu_ov (a,b,aluc,r,z,v); // 32-bit alu with zero and overflow flags input [31:0] a, b; // inputs: a, b input [3:0] aluc; // input: alu control: // aluc[3:0]: output [31:0] r; // output: alu result // x 0 0 0 ADD output z, v; // outputs: zero, overflow // x 1 0 0 SUB wire [31:0] d_and = a & b; // x 0 0 1 AND wire [31:0] d_or = a | b; // x 1 0 1 OR wire [31:0] d_xor = a ^ b; // x 0 1 0 XOR wire [31:0] d_lui = {b[15:0],16'h0}; // x 1 1 0 LUI wire [31:0] d_and_or = aluc[2]? d_or : d_and; // 0 0 1 1 SLL wire [31:0] d_xor_lui = aluc[2]? d_lui : d_xor; // 0 1 1 1 SRL wire [31:0] d_as,d_sh; // 1 1 1 1 SRA // addsub32 (a,b,sub, s); addsub32 as32 (a,b,aluc[2],d_as); // add/sub // shift (d,sa, right, arith, sh); shift shifter (b,a[4:0],aluc[2],aluc[3],d_sh); // shift // mux4x32 (a0, a1, a2, a3, s, y); mux4x32 res (d_as,d_and_or,d_xor_lui,d_sh,aluc[1:0],r); // alu result assign z = ~|r; // z = (r == 0) assign v = ~aluc[2] & ~a[31] & ~b[31] & r[31] & ~aluc[1] & ~aluc[0] | ~aluc[2] & a[31] & b[31] & ~r[31] & ~aluc[1] & ~aluc[0] | aluc[2] & ~a[31] & b[31] & r[31] & ~aluc[1] & ~aluc[0] | aluc[2] & a[31] & ~b[31] & ~r[31] & ~aluc[1] & ~aluc[0]; endmodule
source_codes/v/alu_tb.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ `timescale 1ns/1ns module alu_tb; reg [31:0] a,b; reg [3:0] aluc; wire [31:0] r; wire z; alu al (a,b,aluc,r,z); initial begin aluc = 4'b0000; // ADD a = 32'h1; b = 32'h2; #10 aluc = 4'b0100; // SUB #10 aluc = 4'b0001; // AND a = 32'hcccccccc; b = 32'haaaaaaaa; #10 aluc = 4'b0101; // OR #10 aluc = 4'b0010; // XOR a = 32'h33333333; b = 32'hff005555; #10 aluc = 4'b0110; // LUI #10 aluc = 4'b0011; // SLL a = 32'h0000000f; b = 32'hffffffff; #10 aluc = 4'b0111; // SRL #10 aluc = 4'b1111; // SRA a = 32'h00000010; b = 32'h7f000000; #10 b = 32'hffffff00; #10 aluc = 4'b0100; // SUB a = 32'hffffffff; b = 32'hffffffff; #10 aluc = 4'b0000; // ADD #10 $finish; end endmodule
source_codes/v/cam8x21.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module cam8x21 (clk,pattern,wraddress,wren,maddress,mfound); // cam input clk; // clock input wren; // cam write enable input [19:0] pattern; // vpn to be compared to all 8 lines input [2:0] wraddress; // write address output [2:0] maddress; // matched address output mfound; // a match was found reg [20:0] ram [0:7]; // ram 8-line * 21-bit: valid (1), vpn (20) // write cam, update a line with pattern, valid bit <-- 1 always @ (posedge clk) begin if (wren) ram[wraddress] <= {1'b1,pattern}; // valid, pattern end // fully associative search, should be implemented with CAM cells wire [7:0] match_line; // match line assign match_line[7] = (ram[7] == {1'b1,pattern}); // valid, pattern assign match_line[6] = (ram[6] == {1'b1,pattern}); // valid, pattern assign match_line[5] = (ram[5] == {1'b1,pattern}); // valid, pattern assign match_line[4] = (ram[4] == {1'b1,pattern}); // valid, pattern assign match_line[3] = (ram[3] == {1'b1,pattern}); // valid, pattern assign match_line[2] = (ram[2] == {1'b1,pattern}); // valid, pattern assign match_line[1] = (ram[1] == {1'b1,pattern}); // valid, pattern assign match_line[0] = (ram[0] == {1'b1,pattern}); // valid, pattern assign mfound = |match_line; // a match was found // encoder for matched address, no multiple-match is allowed assign maddress[2] = match_line[7] | match_line[6] | match_line[5] | match_line[4]; assign maddress[1] = match_line[7] | match_line[6] | match_line[3] | match_line[2]; assign maddress[0] = match_line[7] | match_line[5] | match_line[3] | match_line[1]; // initialize cam, mainly clear valid bit of each line integer i; initial begin for (i = 0; i < 8; i = i + 1) ram[i] = 0; end endmodule
source_codes/v/cla_16.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module cla_16 (a,b,c_in,g_out,p_out,s); // 16-bit carry lookahead adder input [15:0] a, b; // inputs: a, b input c_in; // input: carry_in output g_out, p_out; // outputs: g, p output [15:0] s; // output: sum wire [1:0] g, p; // internal wires wire c_out; // internal wire cla_8 a0 (a[7:0], b[7:0], c_in, g[0],p[0],s[7:0]); // add on bits 0-7 cla_8 a1 (a[15:8],b[15:8],c_out,g[1],p[1],s[15:8]); // add on bits 8-15 gp gp0 (g,p,c_in, g_out,p_out,c_out); // higher level g,p endmodule
source_codes/v/cla_2.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module cla_2 (a, b, c_in, g_out, p_out, s); // 2-bit carry lookahead adder input [1:0] a, b; // inputs: a, b input c_in; // input: carry_in output g_out, p_out; // outputs: g, p output [1:0] s; // output: sum wire [1:0] g, p; // internal wires wire c_out; // internal wire // add (a, b, c, g, p, s); // generates g,p,s add a0 (a[0], b[0], c_in, g[0], p[0], s[0]); // add on bit 0 add a1 (a[1], b[1], c_out, g[1], p[1], s[1]); // add on bit 1 // gp (g, p, c_in, g_out, p_out, c_out); // higher level g,p gp gp0 (g, p, c_in, g_out, p_out, c_out); // higher level g,p endmodule
source_codes/v/cla_32.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module cla_32 (a,b,c_in,g_out,p_out,s); // 32-bit carry lookahead adder input [31:0] a, b; // inputs: a, b input c_in; // input: carry_in output g_out, p_out; // outputs: g, p output [31:0] s; // output: sum wire [1:0] g, p; // internal wires wire c_out; // internal wire cla_16 a0 (a[15:0], b[15:0], c_in, g[0],p[0],s[15:0]); // + bits 0-15 cla_16 a1 (a[31:16],b[31:16],c_out,g[1],p[1],s[31:16]); // + bits 16-31 gp gp0 (g,p,c_in,g_out,p_out,c_out); endmodule
source_codes/v/cla_4.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module cla_4 (a,b,c_in,g_out,p_out,s); // 4-bit carry lookahead adder input [3:0] a, b; // inputs: a, b input c_in; // input: carry_in output g_out, p_out; // outputs: g, p output [3:0] s; // output: sum wire [1:0] g, p; // internal wires wire c_out; // internal wire cla_2 a0 (a[1:0],b[1:0],c_in, g[0],p[0],s[1:0]); // add on bits 0,1 cla_2 a1 (a[3:2],b[3:2],c_out,g[1],p[1],s[3:2]); // add on bits 2,3 gp gp0 (g,p,c_in, g_out,p_out,c_out); // higher level g,p endmodule
source_codes/v/cla_8.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module cla_8 (a,b,c_in,g_out,p_out,s); // 8-bit carry lookahead adder input [7:0] a, b; // inputs: a, b input c_in; // input: carry_in output g_out, p_out; // outputs: g, p output [7:0] s; // output: sum wire [1:0] g, p; // internal wires wire c_out; // internal wire cla_4 a0 (a[3:0],b[3:0],c_in, g[0],p[0],s[3:0]); // add on bits 0-3 cla_4 a1 (a[7:4],b[7:4],c_out,g[1],p[1],s[7:4]); // add on bits 4-7 gp gp0 (g,p,c_in, g_out,p_out,c_out); // higher level g,p endmodule
source_codes/v/cla32.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module cla32 (a,b,ci,s); // 32-bit carry lookahead adder, no g, p outputs input [31:0] a, b; // inputs: a, b input ci; // input: carry_in output [31:0] s; // output: sum wire g_out, p_out; // internal wires cla_32 cla (a, b, ci, g_out, p_out, s); // use cla_32 module endmodule
source_codes/v/cla32_tb.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ `timescale 1ns/1ns module cla32_tb; reg [31:0] a,b; reg ci; wire [31:0] s; cla32 adder (a,b,ci,s); initial begin a = 32'h77777777; b = 32'hffffffff; ci = 0; #10 a = 32'haaaaaaaa; b = 32'h55555555; #10 a = 32'hcccccccc; b = 32'hcccccccc; #10 a = 32'h00000000; b = 32'h00000000; end always #5 ci = !ci; endmodule
source_codes/v/clas16.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module clas16 (sub,a,b,ci,s); // 16-bit carry lookahead adder/subtracter input sub; // 1: sub; 0: add input [15:0] a, b; // inputs: a, b input ci; // active low for sub output [15:0] s; // output: sum wire g_out, p_out; // internal wires // cla_16 (a,b, c_in,g_out,p_out,s); cla_16 cla (a,b^{16{sub}},ci, g_out,p_out,s); // use cla_16 module endmodule
source_codes/v/cmoscmos.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module cmoscmos (drain, source, n_gate, p_gate); // cmos gate input source, n_gate, p_gate; output drain; pmos p1 (drain, source, p_gate); // pmos name (drain, source, gate); nmos n1 (drain, source, n_gate); // nmos name (drain, source, gate); endmodule
source_codes/v/cmosnand.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module cmosnand (f, a, b); // cmos nand input a, b; // inputs: a, b output f; // output: f = ~(a & b) supply1 vdd; // logic 1 (power) supply0 gnd; // logic 0 (ground) wire w_n; // wire: connects 2 nmos transistors // pmos (drain, source, gate); pmos p1 (f, vdd, a); pmos p2 (f, vdd, b); // nmos (drain, source, gate); nmos n1 (f, w_n, a); nmos n2 (w_n, gnd, b); endmodule
source_codes/v/cmosnand_tb.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ `timescale 1ns/1ns module cmosnand_tb; reg a,b; wire f; cmosnand not_and (f,a,b); initial begin a = 0; b = 0; end always #1 a = !a; always #2 b = !b; endmodule
source_codes/v/cmosnor.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module cmosnor (f, a, b); // cmos nor input a, b; // inputs: a, b output f; // output: f = ~(a | b) supply1 vdd; // logic 1 (power) supply0 gnd; // logic 0 (ground) wire w_p; // wire: connects 2 pmos transistors // nmos (drain, source, gate); nmos n1 (f, gnd, a); nmos n2 (f, gnd, b); // pmos (drain, source, gate); pmos p1 (w_p, vdd, a); pmos p2 (f, w_p, b); endmodule
source_codes/v/cmosnor_tb.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ `timescale 1ns/1ns module cmosnor_tb; reg a,b; wire f; cmosnor not_or (f,a,b); initial begin a = 0; b = 0; end always #1 a = !a; always #2 b = !b; endmodule
source_codes/v/cmosnot.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module cmosnot (f, a); // cmos inverter input a; // input a output f; // output f = ~a supply1 vdd; // logic 1 (power) supply0 gnd; // logic 0 (ground) // pmos (drain, source, gate); pmos p1 (f, vdd, a); // nmos (drain, source, gate); nmos n1 (f, gnd, a); endmodule
source_codes/v/cmosnot_tb.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ `timescale 1ns/1ns module cmosnot_tb; reg a; wire f; cmosnot cmos_not (f,a); initial begin a = 0; #1 a = 1; #1 a = 0; #1 $finish; end initial begin $monitor("%2d:\ta = %b\tf = %b",$time,a,f); end endmodule
source_codes/v/core2_cache_tlb_memory.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module core2_cache_tlb_memory // dual-core cpu with cache and tlb + memory (v_pc1,pc1,inst1,ealu1,malu1,wdi1,wn1,wd1,ww1, stall_lw1,stall_fp1,stall_lwc11,stall_swc11,stall1, v_pc2,pc2,inst2,ealu2,malu2,wdi2,wn2,wd2,ww2, stall_lw2,stall_fp2,stall_lwc12,stall_swc12,stall2, clk,memclk,clrn,m_a,m_d_r,m_d_w,m_access,m_write,m_ready); input clk, memclk, clrn; // clocks and reset output [31:0] v_pc1, v_pc2; // virtual pc output [31:0] pc1, pc2; // real pc output [31:0] inst1, inst2; // instruction output [31:0] ealu1, ealu2; // exe stage result output [31:0] malu1, malu2; // mem stage result output [31:0] wdi1, wdi2; // wb stage result output [31:0] wd1, wd2; // fp result to be written back output [4:0] wn1, wn2; // fp dest register number output ww1, ww2; // fp register file write enable output stall_lw1, stall_lw2; // stall by lw output stall_fp1, stall_fp2; // stall by fp data hazard output stall_lwc11, stall_lwc12; // stall by lwc1 output stall_swc11, stall_swc12; // stall by swc1 output stall1, stall2; // pipeline stall output [31:0] m_a; // memory address output [31:0] m_d_r; // memory data read output [31:0] m_d_w; // memory data write output m_access; // memory access output m_write; // memory write enable output m_ready; // memory ready wire io1,io2; // i/o, not used wire [31:0] m_a1,m_a2; wire [31:0] m_d_w1,m_d_w2; wire m_access1,m_access2; wire m_write1,m_write2; reg cnt; // counter // core1 cpu_cache_tlb core1 (clk,memclk,clrn,v_pc1,pc1,inst1,ealu1,malu1,wdi1,wn1,wd1,ww1, stall_lw1,stall_fp1,stall_lwc11,stall_swc11,stall1, m_a1,m_d_r,m_d_w1,m_access1,m_write1,m_ready1,io1); // core2 cpu_cache_tlb core2 (clk,memclk,clrn,v_pc2,pc2,inst2,ealu2,malu2,wdi2,wn2,wd2,ww2, stall_lw2,stall_fp2,stall_lwc12,stall_swc12,stall2, m_a2,m_d_r,m_d_w2,m_access2,m_write2,m_ready2,io2); // counter for arbitration on memory access collision always @(negedge clrn or posedge clk) begin if (!clrn) begin cnt <= 0; end else if (m_ready) begin cnt <= ~cnt; end end wire select1 = ~cnt & m_access1 | cnt & ~m_access2; // mux assign m_a = select1 ? m_a1 : m_a2; assign m_d_w = select1 ? m_d_w1 : m_d_w2; assign m_access = select1 ? m_access1 : m_access2; assign m_write = select1 ? m_write1 : m_write2; // demux assign m_ready1 = select1 & m_ready; assign m_ready2 = ~select1 & m_ready; // main memory physical_memory mem (m_a,m_d_r,m_d_w,m_access,m_write,m_ready,clk, memclk,clrn); endmodule
source_codes/v/core2_cache_tlb_memory_tb.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ `timescale 1ns/1ns module core2_cache_tlb_memory_tb; reg clk,memclk,clrn; wire [31:0] v_pc1,v_pc2; wire [31:0] pc1,pc2; wire [31:0] inst1,inst2; wire [31:0] ealu1,ealu2; wire [31:0] malu1,malu2; wire [31:0] wdi1,wdi2; wire [31:0] wd1,wd2; wire [4:0] wn1,wn2; wire ww1,ww2; wire stall_lw1,stall_lw2; wire stall_fp1,stall_fp2; wire stall_lwc11,stall_lwc12; wire stall_swc11,stall_swc12; wire stall1,stall2; wire [31:0] m_a; wire [31:0] m_d_r; wire [31:0] m_d_w; wire m_access; wire m_write; wire m_ready; core2_cache_tlb_memory dualcore (v_pc1,pc1,inst1,ealu1,malu1,wdi1,wn1, wd1,ww1,stall_lw1,stall_fp1, stall_lwc11,stall_swc11,stall1, v_pc2,pc2,inst2,ealu2,malu2,wdi2,wn2, wd2,ww2,stall_lw2,stall_fp2, stall_lwc12,stall_swc12,stall2, clk,memclk,clrn,m_a,m_d_r,m_d_w, m_access,m_write,m_ready); initial begin clk = 1; memclk = 0; clrn = 0; #1 clrn = 1; #8999 $finish; end always #1 memclk = !memclk; always #2 clk = !clk; endmodule /* 168 1 004 - 172.001 2 172 - 340.001 3 340 - 508.001 4 508 - 676.001 5 676 - 844.001 6 844 - 1012.001 7 1012 - 1180.001 8 1180 - 1348.001 9 2332 - 2500.001 10 7096 - 7264.001 */
source_codes/v/counter_6.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module counter_6 (u,clk,clrn,q,a,b,c,d,e,f,g); // a counter with 7-seg LED input clk, clrn; // clk, clear (active low) input u; // u==1: count up; u==0: count down output [2:0] q; // 3-bit counter output output a, b, c, d, e, f, g; // seven-segment LED control reg [2:0] q; // register type always @ (posedge clk or negedge clrn) begin if (!clrn) q <= 0; // if clrn is asserted, counter=0 else if (u) q <= (q + 1) % 6; // if counter up, q++ else if (q != 0) q <= q - 1; // else q-- else q <= 3'd5; end assign {g,f,e,d,c,b,a} = seg7(q); // call function to get LED control function [6:0] seg7; // the function, 7-bit return value input [2:0] q; // input argument case (q) // cases: 3'd0 : seg7 = 7'b1000000; // 0's LED control, 0: light on 3'd1 : seg7 = 7'b1111001; // 1's LED control, 1: light off 3'd2 : seg7 = 7'b0100100; // 2's LED control 3'd3 : seg7 = 7'b0110000; // 3's LED control 3'd4 : seg7 = 7'b0011001; // 4's LED control 3'd5 : seg7 = 7'b0010010; // 5's LED control default: seg7 = 7'b1111111; // default: all segments light off endcase endfunction endmodule
source_codes/v/counter_6_tb.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ `timescale 1ns/1ns module counter_6_tb; reg u,clk,clrn; wire [2:0] q; wire a,b,c,d,e,f,g; counter_6 cnt (u,clk,clrn,q,a,b,c,d,e,f,g); initial begin clk = 1; forever #5 clk = !clk; end initial begin $display("time\tu\tq\ta\tb\tc\td\te\tf\tg"); clrn = 0; u = 1; #5 clrn = 1; #80 u = 0; #90 u = 1; #1 $finish; end initial begin $monitor("%1d\t%b\t%d\t%b\t%b\t%b\t%b\t%b\t%b\t%b", $time,u,q,a,b,c,d,e,f,g); end endmodule
source_codes/v/cpu_cache_tlb.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module cpu_cache_tlb (clk,memclk,clrn,v_pc,pc,inst,ealu,malu,wdi,wn,wd, ww,stall_lw,stall_fp,stall_lwc1,stall_swc1,stall, mem_a,mem_data,mem_st_data,mem_access,mem_write, mem_ready,io); // cpu + cache + tlb input clk, memclk, clrn; // clocks and reset input [31:0] mem_data; // main memory data read input mem_ready; // main memory ready output [31:0] v_pc; // virtual pc output [31:0] pc; // real pc output [31:0] inst; // instruction output [31:0] ealu; // alu output in exe stage output [31:0] malu; // alu output in mem stage output [31:0] wdi; // data to iu reg file output [31:0] wd; // data to fpu reg file output [31:0] mem_a; // main memory address output [31:0] mem_st_data; // main memory data write output [4:0] wn; // fpu reg file's write number output ww; // fpu reg file's write enable output stall_lw; // stall by lw output stall_fp; // stall by fp data dependency output stall_lwc1; // stall by lwc1 output stall_swc1; // stall by swc1 output stall; // stall by div and sqrt output mem_access; // main memory access output mem_write; // main memory write enable output io; // inst rom or data i/o wire [31:0] e3d; // fpu data in e3 stage wire [31:0] qfa,qfb,fa,fb,dfa,dfb; // for iu wire [31:0] mmo,wmo; wire [4:0] count_div,count_sqrt; wire [4:0] e1n,e2n,e3n,wrn,fs,ft,fd; wire [2:0] fc; wire [1:0] e1c,e2c,e3c; // for fpu wire fwdla,fwdlb,fwdfa,fwdfb; wire wf,fasmds,e1w,e2w,e3w,wwfpr; wire no_cache_stall,dtlb; wire e; // for multithreading CPU iu_cache_tlb i_u (e1n,e2n,e3n, e1w,e2w,e3w, stall,1'b0,dfb,e3d,clk, memclk,clrn,no_cache_stall,dtlb,fs,ft,wmo,wrn,wwfpr,mmo, fwdla,fwdlb,fwdfa,fwdfb,fd,fc,wf,fasmds,v_pc,pc,inst,ealu, malu,wdi,stall_lw,stall_fp,stall_lwc1,stall_swc1,mem_a, mem_data,mem_st_data,mem_access,mem_write,mem_ready,io); regfile2w fpr (fs,ft,wd,wn,ww,wmo,wrn,wwfpr,~clk,clrn,qfa,qfb); mux2x32 fwd_f_load_a (qfa,mmo,fwdla,fa); // forward lwc1 to fp a mux2x32 fwd_f_load_b (qfb,mmo,fwdlb,fb); // forward lwc1 to fp b mux2x32 fwd_f_res_a (fa,e3d,fwdfa,dfa); // forward fp res to fp a mux2x32 fwd_f_res_b (fb,e3d,fwdfb,dfb); // forward fp res to fp b fpu fp_unit (dfa,dfb,fc,wf,fd,no_cache_stall,clk,clrn,e3d,wd,wn,ww, stall,e1n,e1w,e2n,e2w,e3n,e3w,e1c,e2c,e3c,count_div, count_sqrt,e,dtlb); endmodule
source_codes/v/cpu_cache_tlb_memory.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module cpu_cache_tlb_memory (clk,memclk,clrn,v_pc,pc,inst,ealu,malu,wdi,wn, wd,ww,stall_lw,stall_fp,stall_lwc1,stall_swc1,stall,m_a,m_d_r,m_d_w, m_access,m_write,m_ready); // cpu + cache + tlb + memory input clk, memclk, clrn; // clocks and reset output [31:0] v_pc; // virtual pc output [31:0] pc; // real pc output [31:0] inst; // instruction output [31:0] ealu; // alu output in exe stage output [31:0] malu; // alu output in mem stage output [31:0] wdi; // data to iu reg file output [31:0] wd; // data to fpu reg file output [4:0] wn; // fpu reg file's write number output ww; // fpu reg file's write enable output stall_lw; // stall by lw output stall_fp; // stall by fp data dependency output stall_lwc1; // stall by lwc1 output stall_swc1; // stall by swc1 output stall; // stall by div and sqrt output [31:0] m_a; // main memory address output [31:0] m_d_r; // main memory data read output [31:0] m_d_w; // main memory data write output m_access; // main memory access output m_write; // main memory write enable output m_ready; // main memory ready wire io; // inst rom or data i/o // cpu cpu_cache_tlb cpucachetlb ( clk,memclk,clrn,v_pc,pc,inst,ealu,malu,wdi,wn,wd, ww,stall_lw,stall_fp,stall_lwc1,stall_swc1,stall, m_a,m_d_r,m_d_w,m_access,m_write,m_ready,io); // i/o, ignored wire [31:0] io_d_r = 0; // ignored io here wire io_ready = 1; // ignored io here wire [31:0] mem_d_r; wire mem_ready; wire mem_access = m_access & ~io; wire io_access = m_access & io; wire mem_write = m_write & ~io; wire io_write = m_write & io; assign m_d_r = (io) ? io_d_r : mem_d_r; assign m_ready = (io) ? io_ready : mem_ready; // main memory physical_memory mem (m_a,mem_d_r,m_d_w,mem_access,m_write,mem_ready, clk,memclk,clrn); endmodule
source_codes/v/cpu_cache_tlb_memory_tb.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ `timescale 1ns/1ns module cpu_cache_tlb_memory_tb; reg clk,memclk,clrn; wire [31:0] v_pc,pc,inst,ealu,malu,wdi; wire [31:0] wd; wire [4:0] wn; wire ww,stall_lw,stall_fp,stall_lwc1,stall_swc1,stall; wire [31:0] m_a; wire [31:0] m_d_r; wire [31:0] m_d_w; wire m_access; wire m_write; wire m_ready; cpu_cache_tlb_memory compsys (clk,memclk,clrn, v_pc,pc,inst,ealu,malu,wdi,wn,wd,ww, stall_lw,stall_fp,stall_lwc1,stall_swc1, stall,m_a,m_d_r,m_d_w,m_access,m_write, m_ready); initial begin clk = 1; memclk = 0; clrn = 0; #1 clrn = 1; #4999 $finish; end always #1 memclk = !memclk; always #2 clk = !clk; endmodule /* 144 1 004- 148 reset 2 148- 292 reset 3 292- 436 goto user prog 4 436- 580 goto user prog 5 1156-1300 eret 6 4340-4500 cache hit */
source_codes/v/crc3.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module crc3 (clk,clrn,m,crc); // G = x^3 + x + 1 (D = 1011) input clk, clrn; // clock and reset input m; // message or dividend output reg [2:0] crc; // 3-bit crc code wire m_xor_crc2 = m ^ crc[2]; always @ (posedge clk or negedge clrn) begin if (!clrn) begin crc <= 0; end else begin crc[0] <= m_xor_crc2; // 1 crc[1] <= crc[0]^ m_xor_crc2; // x crc[2] <= crc[1]; end end endmodule
source_codes/v/crc3_tb.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ `timescale 1ns/1ns module crc3_tb; reg clk,clrn; reg m; wire [2:0] crc; crc3 crc_3 (clk,clrn,m,crc); initial begin clk = 1; clrn = 0; #1 clrn = 1; m = 1; #10 m = 1; #10 m = 0; #10 m = 0; #10 m = 0; #10 m = 1; #10 m = 0; #10 m = 1; #10 m = 1; #10 m = 1; #10 m = 1; #10 m = 1; #10 m = 0; end always #5 clk = !clk; endmodule
source_codes/v/crc32.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module crc32 (clk,clrn,m,crc); // G = x^{32} + x^{26} + x^{23} + x^{22} + // x^{16} + x^{12} + x^{11} + x^{10} + x^{8} + x^{7} + x^{5} + x^{4} + // x^{2} + x + 1 // D = 1_0000_0100_1100_0001_0001_1101_1011_0111 = 0x104c11db7 input clk, clrn; // clock and reset input m; // message or dividend output reg [31:0] crc; // 32-bit crc code wire m_xor_crc31 = m ^ crc[31]; always @ (posedge clk or negedge clrn) begin if (!clrn) begin crc <= 0; end else begin crc[00] <= m_xor_crc31; // x^{00} crc[01] <= crc[00] ^ m_xor_crc31; // x^{01} crc[02] <= crc[01] ^ m_xor_crc31; // x^{02} crc[03] <= crc[02]; crc[04] <= crc[03] ^ m_xor_crc31; // x^{04} crc[05] <= crc[04] ^ m_xor_crc31; // x^{05} crc[06] <= crc[05]; crc[07] <= crc[06] ^ m_xor_crc31; // x^{07} crc[08] <= crc[07] ^ m_xor_crc31; // x^{08} crc[09] <= crc[08]; crc[10] <= crc[09] ^ m_xor_crc31; // x^{10} crc[11] <= crc[10] ^ m_xor_crc31; // x^{11} crc[12] <= crc[11] ^ m_xor_crc31; // x^{12} crc[13] <= crc[12]; crc[14] <= crc[13]; crc[15] <= crc[14]; crc[16] <= crc[15] ^ m_xor_crc31; // x^{16} crc[17] <= crc[16]; crc[18] <= crc[17]; crc[19] <= crc[18]; crc[20] <= crc[19]; crc[21] <= crc[20]; crc[22] <= crc[21] ^ m_xor_crc31; // x^{22} crc[23] <= crc[22] ^ m_xor_crc31; // x^{23} crc[24] <= crc[23]; crc[25] <= crc[24]; crc[26] <= crc[25] ^ m_xor_crc31; // x^{26} crc[27] <= crc[26]; crc[28] <= crc[27]; crc[29] <= crc[28]; crc[30] <= crc[29]; crc[31] <= crc[30]; end end endmodule
source_codes/v/crc32_tb.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ `timescale 1ns/1ns module crc32_tb; reg clk,clrn; reg m; wire [31:0] crc; crc32 crc_32 (clk,clrn,m,crc); initial begin clk = 1; clrn = 0; #1 clrn = 1; m = 1; #10 m = 0; #10 m = 0; #10 m = 0; #10 m = 0; #10 m = 0; #10 m = 1; #10 m = 0; #10 m = 0; #10 m = 1; #10 m = 1; #10 m = 0; #10 m = 0; #10 m = 0; #10 m = 0; #10 m = 0; #10 m = 1; #10 m = 0; #10 m = 0; #10 m = 0; #10 m = 1; #10 m = 1; #10 m = 1; #10 m = 0; #10 m = 1; #10 m = 1; #10 m = 0; #10 m = 1; #10 m = 1; #10 m = 0; #10 m = 1; #10 m = 1; #10 m = 1; #10 m = 0; end always #5 clk = !clk; endmodule
source_codes/v/csa.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module csa (a, b, ci, s, co); // carry save adder (csa) input a, b, ci; // inputs: a, b, carry_in output s, co; // outputs: sum, carry_out assign s = a ^ b ^ ci; // sum of inputs assign co = a & b | b & ci | ci & a; // carry_out endmodule
source_codes/v/cu_exc_int.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module cu_exc_int (mwreg,mrn,ern,ewreg,em2reg,mm2reg,rsrtequ,func,op,rs,rt, rd,op1,wreg,m2reg,wmem,aluc,regrt,aluimm,fwda,fwdb,wpcir, sext,pcsrc,shift,jal,irq,sta,ecancel,eis_branch, mis_branch,inta,selpc,exc,sepc,cause,mtc0,wepc,wcau,wsta, mfc0,is_branch,ove,cancel,exc_ovr,mexc_ovr); // ctrl unit input [31:0] sta; // status: IM[3:0]: ov,unimpl,sys,int input [5:0] op,func; input [4:0] mrn,ern,rs,rt,rd; input [4:0] op1; // for decode mfc0, mtc0, and eret input mwreg,ewreg,em2reg,mm2reg,rsrtequ; input irq; // interrupt request input ecancel; // cancel in EXE stage input eis_branch; // is_branch in EXE stage input mis_branch; // is_branch in MEM stage input exc_ovr; // overflow exception occurs input mexc_ovr; // exc_ovr in MEM stage output [31:0] cause; // cause content output [3:0] aluc; output [1:0] pcsrc,fwda,fwdb; output [1:0] selpc; // 00: npc; 01: epc; 10: exc_base output [1:0] mfc0; // 00: epc8; 01: sta; 10: cau; 11: epc output [1:0] sepc; // 00: pc; 01: pcd; 10: pce; 11: pcm output wpcir,wreg,m2reg,wmem,regrt,aluimm,sext,shift,jal; output inta; // interrupt acknowledgement output exc; // any int or exc happened output mtc0; // is mtc0 instruction output wsta; // status register write enable output wcau; // cause register write enable output wepc; // epc register write enable output is_branch; // is a branch or a jump output ove; // ov enable = arith & sta[3] output cancel; // exception cancels next instruction reg [1:0] fwda,fwdb; wire [1:0] exccode; // exccode wire rtype,i_add,i_sub,i_and,i_or,i_xor,i_sll,i_srl,i_sra; wire i_jr,i_addi,i_andi,i_ori,i_xori,i_lw,i_sw,i_beq,i_bne; wire i_lui,i_j,i_jal,i_rs,i_rt; wire exc_int; // exception of interrupt wire exc_sys; // exception of system call wire exc_uni; // exception of unimplemented inst wire c0_type; // cp0 instructions wire i_syscall; // is syscall instruction wire i_mfc0; // is mfc0 instruction wire i_mtc0; // is mtc0 instruction wire i_eret; // is eret instruction wire unimplemented_inst; // is an unimplemented inst wire rd_is_status; // rd is status wire rd_is_cause; // rd is cause wire rd_is_epc; // rd is epc wire arith = i_add | i_sub | i_addi; // for overflow assign is_branch = i_beq | i_bne | i_jr | i_j | i_jal; // has delay slot assign exc_int = sta[0] & irq; // 0. exc_int assign exc_sys = sta[1] & i_syscall; // 1. exc_sys assign exc_uni = sta[2] & unimplemented_inst; // 2. exc_uni assign ove = sta[3] & arith; // 3. exc_ovr enable assign inta = exc_int; // ack immediately assign exc = exc_int | exc_sys | exc_uni | exc_ovr; // all int_exc assign cancel = exc | i_eret; // always cancel next inst, eret also // sel epc: id is_branch eis_branch mis_branch others // exc_int PCD (01) PC (00) PC (00) PC (00) // exc_sys x x PCD (01) PCD (01) // exc_uni x x PCD (01) PCD (01) // exc_ovr x x PCM (11) PCE (10) assign sepc[0] = exc_int & is_branch | exc_sys | exc_uni | exc_ovr & mis_branch; assign sepc[1] = exc_ovr; // exccode: 0 0 : irq // 0 1 : i_syscall // 1 0 : unimplemented_inst // 1 1 : exc_ovr assign exccode[0] = i_syscall | exc_ovr; assign exccode[1] = unimplemented_inst | exc_ovr; assign cause = {eis_branch,27'h0,exccode,2'b00}; // BD assign mtc0 = i_mtc0; assign wsta = exc | mtc0 & rd_is_status | i_eret; assign wcau = exc | mtc0 & rd_is_cause; assign wepc = exc | mtc0 & rd_is_epc; assign rd_is_status = (rd == 5'd12); // cp0 status register assign rd_is_cause = (rd == 5'd13); // cp0 cause register assign rd_is_epc = (rd == 5'd14); // cp0 epc register // mfc0: 0 0 : epc8 // 0 1 : sta // 1 0 : cau // 1 1 : epc assign mfc0[0] = i_mfc0 & rd_is_status | i_mfc0 & rd_is_epc; assign mfc0[1] = i_mfc0 & rd_is_cause | i_mfc0 & rd_is_epc; // selpc: 0 0 : npc // 0 1 : epc // 1 0 : exc_base // 1 1 : x assign selpc[0] = i_eret; assign selpc[1] = exc; assign c0_type = ~op[5] & op[4] & ~op[3] & ~op[2] & ~op[1] & ~op[0]; assign i_mfc0 = c0_type &~op1[4] &~op1[3] &~op1[2] &~op1[1] &~op1[0]; assign i_mtc0 = c0_type &~op1[4] &~op1[3] & op1[2] &~op1[1] &~op1[0]; assign i_eret = c0_type & op1[4] &~op1[3] &~op1[2] &~op1[1] &~op1[0] & ~func[5] & func[4] & func[3] &~func[2] &~func[1] &~func[0]; assign i_syscall = rtype & ~func[5] & ~func[4] & func[3] & func[2] & ~func[1] & ~func[0]; assign unimplemented_inst = ~(i_mfc0 | i_mtc0 | i_eret | i_syscall | i_add | i_sub | i_and | i_or | i_xor | i_sll | i_srl | i_sra | i_jr | i_addi | i_andi | i_ori | i_xori | i_lw | i_sw | i_beq | i_bne | i_lui | i_j | i_jal); // except for implemented insts and (rtype,~op[5],~op[4],~op[3],~op[2],~op[1],~op[0]); // r format and (i_add,rtype, func[5],~func[4],~func[3],~func[2],~func[1],~func[0]); and (i_sub,rtype, func[5],~func[4],~func[3],~func[2], func[1],~func[0]); and (i_and,rtype, func[5],~func[4],~func[3], func[2],~func[1],~func[0]); and (i_or, rtype, func[5],~func[4],~func[3], func[2],~func[1], func[0]); and (i_xor,rtype, func[5],~func[4],~func[3], func[2], func[1],~func[0]); and (i_sll,rtype,~func[5],~func[4],~func[3],~func[2],~func[1],~func[0]); and (i_srl,rtype,~func[5],~func[4],~func[3],~func[2], func[1],~func[0]); and (i_sra,rtype,~func[5],~func[4],~func[3],~func[2], func[1], func[0]); and (i_jr, rtype,~func[5],~func[4], func[3],~func[2],~func[1],~func[0]); and (i_addi,~op[5],~op[4], op[3],~op[2],~op[1],~op[0]); // i format and (i_andi,~op[5],~op[4], op[3], op[2],~op[1],~op[0]); and (i_ori, ~op[5],~op[4], op[3], op[2],~op[1], op[0]); and (i_xori,~op[5],~op[4], op[3], op[2], op[1],~op[0]); and (i_lw, op[5],~op[4],~op[3],~op[2], op[1], op[0]); and (i_sw, op[5],~op[4], op[3],~op[2], op[1], op[0]); and (i_beq, ~op[5],~op[4],~op[3], op[2],~op[1],~op[0]); and (i_bne, ~op[5],~op[4],~op[3], op[2],~op[1], op[0]); and (i_lui, ~op[5],~op[4], op[3], op[2], op[1], op[0]); and (i_j, ~op[5],~op[4],~op[3],~op[2], op[1],~op[0]); // i format and (i_jal, ~op[5],~op[4],~op[3],~op[2], op[1], op[0]); assign i_rs = i_add | i_sub | i_and | i_or | i_xor | i_jr | i_addi | i_andi | i_ori | i_xori | i_lw | i_sw | i_beq | i_bne; assign i_rt = i_add | i_sub | i_and | i_or | i_xor | i_sll | i_srl | i_sra | i_sw | i_beq | i_bne | i_mtc0; // mtc0 added assign wpcir = ~(ewreg & em2reg & (ern != 0) & (i_rs & (ern == rs) | i_rt & (ern == rt))); always @ (ewreg or mwreg or ern or mrn or em2reg or mm2reg or rs or rt) begin fwda = 2'b00; // default: no hazards if (ewreg & (ern != 0) & (ern == rs) & ~em2reg) begin fwda = 2'b01; // select exe_alu end else begin if (mwreg & (mrn != 0) & (mrn == rs) & ~mm2reg) begin fwda = 2'b10; // select mem_alu end else begin if (mwreg & (mrn != 0) & (mrn == rs) & mm2reg) begin fwda = 2'b11; // select mem_lw end end end fwdb = 2'b00; // default: no hazards if (ewreg & (ern != 0) & (ern == rt) & ~em2reg) begin fwdb = 2'b01; // select exe_alu end else begin if (mwreg & (mrn != 0) & (mrn == rt) & ~mm2reg) begin fwdb = 2'b10; // select mem_alu end else begin if (mwreg & (mrn != 0) & (mrn == rt) & mm2reg) begin fwdb = 2'b11; // select mem_lw end end end end assign wmem = i_sw & wpcir & ~ecancel & ~exc_ovr & ~mexc_ovr; assign regrt = i_addi|i_andi|i_ori |i_xori|i_lw |i_lui |i_mfc0; assign jal = i_jal; assign m2reg = i_lw; assign shift = i_sll |i_srl |i_sra; assign aluimm = i_addi|i_andi|i_ori |i_xori|i_lw |i_lui |i_sw; assign sext = i_addi|i_lw |i_sw |i_beq |i_bne; assign aluc[3] = i_sra; assign aluc[2] = i_sub |i_or |i_srl |i_sra |i_ori |i_lui; assign aluc[1] = i_xor |i_sll |i_srl |i_sra |i_xori|i_beq |i_bne|i_lui; assign aluc[0] = i_and |i_or |i_sll |i_srl |i_sra |i_andi|i_ori; assign pcsrc[1] = i_jr |i_j |i_jal; assign pcsrc[0] = i_beq & rsrtequ |i_bne & ~rsrtequ | i_j | i_jal; assign wreg =(i_add |i_sub |i_and |i_or |i_xor|i_sll | i_srl |i_sra |i_addi|i_andi|i_ori|i_xori | i_lw |i_lui |i_jal |i_mfc0) & // mfc0 added wpcir & ~ecancel & ~exc_ovr & ~mexc_ovr; endmodule
source_codes/v/d_cache.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module d_cache ( // direct mapping, 2^6 blocks, 1 word/block, write-through input [31:0] p_a, // cpu address input [31:0] p_dout, // cpu data out to mem output [31:0] p_din, // cpu data in from mem input p_strobe, // cpu strobe input p_rw, // cpu read/write command input uncached, // uncached output p_ready, // ready (to cpu) input clk, clrn, // clock and reset output [31:0] m_a, // mem address input [31:0] m_dout, // mem data out to cpu output [31:0] m_din, // mem data in from cpu output m_strobe, // mem strobe output m_rw, // mem read/write input m_ready // mem ready ); reg d_valid [0:63]; // 1-bit valid reg [23:0] d_tags [0:63]; // 24-bit tag reg [31:0] d_data [0:63]; // 32-bit data wire [23:0] tag = p_a[31:8]; // address tag wire [31:0] c_din; // data to cache wire [5:0] index = p_a[7:2]; // block index wire c_write; // cache write integer i; always @ (posedge clk or negedge clrn) if (!clrn) begin for (i=0; i<64; i=i+1) d_valid[i] <= 0; // clear valid end else if (c_write) d_valid[index] <= 1; // write valid always @ (posedge clk) if (c_write) begin d_tags[index] <= tag; // write address tag d_data[index] <= c_din; // write data end wire valid = d_valid[index]; // read cache valid wire [23:0] tagout = d_tags[index]; // read cache tag wire [31:0] c_dout = d_data[index]; // read cache data wire cache_hit = p_strobe & valid & (tagout == tag); // cache hit wire cache_miss = p_strobe & (!valid | (tagout != tag)); // cache miss assign m_din = p_dout; // mem <-- cpu data assign m_a = p_a; // mem <-- cpu address assign m_rw = p_rw; // write through assign m_strobe = p_rw | cache_miss; // also read on miss assign p_ready = ~p_rw & cache_hit | // read and hit or (cache_miss | p_rw) & m_ready; // write and mem ready assign c_write = ~uncached & (p_rw | cache_miss & m_ready); // write assign c_din = p_rw? p_dout : m_dout; // data from cpu or mem assign p_din = cache_hit? c_dout : m_dout; // data from cache or mem endmodule
source_codes/v/d_cache_tb.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ `timescale 1ns/1ns module d_cache_tb; reg [31:0] p_a; reg [31:0] p_dout; wire [31:0] p_din; reg p_strobe; reg p_rw; reg uncached; wire p_ready; reg clk,clrn; wire [31:0] m_a; reg [31:0] m_dout; wire [31:0] m_din; wire m_strobe; wire m_rw; reg m_ready; d_cache dcache (p_a,p_dout,p_din,p_strobe,p_rw,uncached,p_ready, clk,clrn,m_a,m_dout,m_din,m_strobe,m_rw,m_ready); initial begin clrn = 0; clk = 1; p_a = 32'h00000100; p_dout = 32'h00000000; p_strobe = 1; p_rw = 0; m_dout = 32'h00000000; uncached = 0; m_ready = 0; #10 clrn = 1; #80 m_dout = 32'hffffffff; m_ready = 1; #20 p_a = 32'h00000000; p_strobe = 0; m_dout = 32'h00000000; m_ready = 0; #60 p_a = 32'h00000100; p_strobe = 1; #20 p_a = 32'h00000000; p_strobe = 0; #80 p_a = 32'h00000104; p_dout = 32'h5555aaaa; p_rw = 1; p_strobe = 1; #100 m_ready = 1; #20 p_a = 32'h00000000; p_dout = 32'h00000000; p_strobe = 0; p_rw = 0; m_ready = 0; #20 p_a = 32'h00000104; p_strobe = 1; #20 p_a = 32'h00000000; p_strobe = 0; end always #10 clk = !clk; endmodule
source_codes/v/d_ff.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module d_ff (prn, clk, d, clrn, q, qn); // dff generated from schematic input prn, clk, d, clrn; // prn: preset; clrn: clear (active low) output q, qn; // outputs q, qn wire wire_0, wire_1; // internal wire, see figure ch02_fig21 wire wire_2, wire_3; // internal wire, see figure ch02_fig21 assign wire_0 = ~(wire_1 & prn & wire_2); // 3-input nand assign wire_1 = ~(clk & clrn & wire_0); // 3-input nand assign wire_2 = ~(wire_3 & clrn & d); // 3-input nand assign wire_3 = ~(wire_1 & clk & wire_2); // 3-input nand assign q = ~(prn & wire_1 & qn); // 3-input nand assign qn = ~(q & wire_3 & clrn); // 3-input nand endmodule
source_codes/v/d_ff_sync.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module d_ff_sync (d,clk,clrn,q); // dff with synchronous reset (to clk) input d, clk, clrn; // inputs d, clk, clrn (active low) output reg q; // output q, register type always @ (posedge clk) begin // always block, posedge: rising edge if (!clrn) q <= 0; // if clrn is asserted, reset dff else q <= d; // else store d to dff end endmodule
source_codes/v/d_ff_tb.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ `timescale 1ns/1ns module d_ff_tb; reg prn,clk,d,clrn; wire q,qn; d_ff dff (prn,clk,d,clrn,q,qn); initial begin clk = 0; prn = 1; clrn = 0; d = 0; #1 clrn = 1; #1 prn = 0; d = 1; #1 prn = 1; #1 d = 0; #2 d = 1; #2 d = 0; #1 d = 1; #2 d = 0; #3 d = 1; #2 d = 0; #2 d = 1; #1 d = 0; #2 d = 1; #3 d = 0; #6 $finish; end always #5 clk = !clk; endmodule
source_codes/v/d_flip_flop.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module d_flip_flop (clk,d,q,qn); // dff using 2 d latches input clk, d; // inputs: clk, d output q, qn; // outputs: q, qn wire q0, qn0; // internal wires wire clkn, clknn; // internal wires not inv1 (clkn, clk); // inverse of clk not inv2 (clknn, clkn); // inverse of clkn d_latch dlatch1 (clkn, d, q0, qn0); // master d latch d_latch dlatch2 (clknn, q0, q, qn); // slave d latch endmodule
source_codes/v/d_flip_flop_tb.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ `timescale 1ns/1ns module d_flip_flop_tb; reg clk,d; wire q,qn; d_flip_flop dff (clk,d,q,qn); initial begin clk = 0; d = 0; #2 d = 1; #2 d = 0; #2 d = 1; #2 d = 0; #1 d = 1; #2 d = 0; #3 d = 1; #2 d = 0; #2 d = 1; #1 d = 0; #2 d = 1; #3 d = 0; #6 $finish; end always #5 clk = !clk; endmodule
source_codes/v/d_latch.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module d_latch (c,d,q,qn); // d latch input c, d; // inputs: c, d output q, qn; // outputs: q, qn wire r, s; // internal wires nand nand1 (s, d, c); // nand (out, in1, in2); nand nand2 (r, ~d, c); // nand (out, in1, in2); rs_latch rs (s, r, q, qn); // use rs_latch module endmodule
source_codes/v/d_latch_tb.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ `timescale 1ns/1ns module d_latch_tb; reg c,d; wire q,qn; d_latch dl (c,d,q,qn); initial begin c = 0; d = 0; #2 d = 1; #2 d = 0; #1 c = 1; #1 d = 1; #2 d = 0; #1 d = 1; #1 c = 0; #1 d = 0; #3 d = 1; #1 c = 1; #1 d = 0; #2 d = 1; #1 d = 0; #1 c = 0; #1 d = 1; #3 d = 0; #1 c = 1; #5 $finish; end endmodule
source_codes/v/data_mem.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module data_mem (we,addr,datain,memclk,dataout); input [31:0] addr,datain; input we,memclk; output [31:0] dataout; lpm_ram_dq ram (.data(datain),.address(addr[6:2]),.we(we), .inclock(memclk),.outclock(memclk),.q(dataout)); defparam ram.lpm_width = 32; defparam ram.lpm_widthad = 5; defparam ram.lpm_file = "data_mem.hex"; defparam ram.lpm_indata = "REGISTERED"; defparam ram.lpm_outdata = "REGISTERED"; defparam ram.lpm_address_control = "REGISTERED"; endmodule
source_codes/v/dec5e.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module dec5e (n,ena,e); // 5-32 decoder with an enable input [4:0] n; // 5-bit number input ena; // master enable output [31:0] e; // 32-bit enables assign e = ena? decoder(n) : 32'h00000000; function [31:0] decoder; input [4:0] n; case (n) 5'd00: decoder=32'h00000001; // 00000000000000000000000000000001 5'd01: decoder=32'h00000002; // 00000000000000000000000000000010 5'd02: decoder=32'h00000004; // 00000000000000000000000000000100 5'd03: decoder=32'h00000008; // 00000000000000000000000000001000 5'd04: decoder=32'h00000010; // 00000000000000000000000000010000 5'd05: decoder=32'h00000020; // 00000000000000000000000000100000 5'd06: decoder=32'h00000040; // 00000000000000000000000001000000 5'd07: decoder=32'h00000080; // 00000000000000000000000010000000 5'd08: decoder=32'h00000100; // 00000000000000000000000100000000 5'd09: decoder=32'h00000200; // 00000000000000000000001000000000 5'd10: decoder=32'h00000400; // 00000000000000000000010000000000 5'd11: decoder=32'h00000800; // 00000000000000000000100000000000 5'd12: decoder=32'h00001000; // 00000000000000000001000000000000 5'd13: decoder=32'h00002000; // 00000000000000000010000000000000 5'd14: decoder=32'h00004000; // 00000000000000000100000000000000 5'd15: decoder=32'h00008000; // 00000000000000001000000000000000 5'd16: decoder=32'h00010000; // 00000000000000010000000000000000 5'd17: decoder=32'h00020000; // 00000000000000100000000000000000 5'd18: decoder=32'h00040000; // 00000000000001000000000000000000 5'd19: decoder=32'h00080000; // 00000000000010000000000000000000 5'd20: decoder=32'h00100000; // 00000000000100000000000000000000 5'd21: decoder=32'h00200000; // 00000000001000000000000000000000 5'd22: decoder=32'h00400000; // 00000000010000000000000000000000 5'd23: decoder=32'h00800000; // 00000000100000000000000000000000 5'd24: decoder=32'h01000000; // 00000001000000000000000000000000 5'd25: decoder=32'h02000000; // 00000010000000000000000000000000 5'd26: decoder=32'h04000000; // 00000100000000000000000000000000 5'd27: decoder=32'h08000000; // 00001000000000000000000000000000 5'd28: decoder=32'h10000000; // 00010000000000000000000000000000 5'd29: decoder=32'h20000000; // 00100000000000000000000000000000 5'd30: decoder=32'h40000000; // 01000000000000000000000000000000 5'd31: decoder=32'h80000000; // 10000000000000000000000000000000 endcase endfunction endmodule
source_codes/v/decoder3e.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module decoder3e (n,ena,d); // 3-8 decoder with enable input [2:0] n; // inputs: n, 3 bits input ena; // input: enable output [7:0] d; // outputs: d, 2^3 = 8 bits reg [7:0] d; // d cannot be a wire always @ (ena or n) begin // always block d = 8'b0; // let d = 00000000 first d[n] = ena; // then let n-th bit of d = ena (0 or 1) end endmodule
source_codes/v/decoder3e_tb.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ `timescale 1ns/1ns module decoder3e_tb; reg [2:0] n; reg ena; wire [7:0] d; integer i; decoder3e dec3e (n,ena,d); initial begin #0 $display("time\tena\tn\td"); #0 ena = 1; #0 n = 0; for (i = 1; i < 8; i = i + 1) begin #1 n = i; end #1 ena = 0; n = 3'bxxx; #1 $finish; end initial begin $monitor("%1d\t%b\t%b\t%b",$time,ena,n,d); end endmodule
source_codes/v/demux1to8.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module demux1to8 (s,y,a); // 1-to-8 demultiplexer input [2:0] s; // inputs: s, dispatch control input y; // input: y, to be dispatched output [7:0] a; // outputs: only 1 bit's value = y assign a = (1 << s) & {8{y}}; // the value of (2^s)th bit = y endmodule
source_codes/v/demux1to8_tb.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ `timescale 1ns/1ns module demux1to8_tb; reg [2:0] s; reg y; wire [7:0] a; integer i; demux1to8 dm (s,y,a); initial begin #0 $display("time\ts\ty\ta"); #0 s = 0; #0 y = 1; for (i = 1; i < 8; i = i + 1) begin #1 s = i; end #1 s = 0; y = 0; for (i = 1; i < 8; i = i + 1) begin #1 s = i; end #1 $finish; end initial begin $monitor("%1d\t%b\t%b\t%b",$time,s,y,a); end endmodule
source_codes/v/dff.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module dff (d,clk,clrn,q); // dff with asynchronous reset input d, clk, clrn; // inputs d, clk, clrn (active low) output reg q; // output q, register type always @ (posedge clk or negedge clrn) begin // always block, "or" if (!clrn) q <= 0; // if clrn is asserted, reset dff else q <= d; // else store d to dff end endmodule
source_codes/v/dff32.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module dff32 (d,clk,clrn,q); // a 32-bit register input [31:0] d; // input d input clk, clrn; // clock and reset output reg [31:0] q; // output q always @(negedge clrn or posedge clk) if (!clrn) q <= 0; // q = 0 if reset else q <= d; // save d endmodule
source_codes/v/dffe.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module dffe (d,clk,clrn,e,q); // dff (async) with write enable input d, clk, clrn; // inputs d, clk, clrn (active low) input e; // enable output reg q; // output q, register type always @ (posedge clk or negedge clrn) begin // always block, "or" if (!clrn) q <= 0; // if clrn is asserted, reset dff else if (e) q <= d; // else if enabled store d to dff end endmodule
source_codes/v/dffe32.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module dffe32 (d,clk,clrn,e,q); // a 32-bit register input [31:0] d; // input d input e; // e: enable input clk, clrn; // clock and reset output reg [31:0] q; // output q always @(negedge clrn or posedge clk) if (!clrn) q <= 0; // q = 0 if reset else if (e) q <= d; // save d if enabled endmodule
source_codes/v/display_i2c_eeprom.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module display_i2c_eeprom (sys_clk,clrn,i2c_scl,i2c_sda,r,g,b,hs,vs,vga_clk, blankn,syncn); // write & display chars in eeprom input sys_clk, clrn; // sys_clk: 50MHz inout i2c_scl, i2c_sda; // i2c clk and data output [7:0] r, g, b; // vga r,g,b colors output hs, vs; // vga h and v synch output vga_clk; // for ADV7123 VGA DAC output blankn; // for ADV7123 VGA DAC output syncn; // for ADV7123 VGA DAC wire font_dot; // font dot wire [31:0] inst,pc,d_t_mem,cpu_mem_a,d_f_mem; wire write,read,io_rdn,io_wrn,wvram,rvram; wire ready,overflow; reg vga_clk = 1; // vga_clk: 25MHz always @(posedge sys_clk) vga_clk <= ~vga_clk; // vga_clk: 25MHz // vga interface controller assign blankn = 1; assign syncn = 0; wire [8:0] row_addr; // pixel ram row addr wire [9:0] col_addr; // pixel ram col addr wire vga_rdn; wire [23:0] vga_pixel = font_dot? 24'hffffff : 24'h0000ff; //white/blue vgac vga (vga_clk,clrn,vga_pixel,row_addr,col_addr,vga_rdn,r,g,b,hs,vs); wire [5:0] char_row = row_addr[8:3]; // char row wire [2:0] font_row = row_addr[2:0]; // font row wire [6:0] char_col = col_addr[9:3]; // char col wire [2:0] font_col = col_addr[2:0]; // font col // character ram, 640/8 = 80 = 64 + 16; 480/8 = 60; wire [12:0] vga_cram_addr = {1'b0,char_row,6'h0} + {3'b0,char_row,4'h0} + {6'h0,char_col}; wire [12:0] char_ram_addr = wvram ? cpu_mem_a[14:2] : vga_cram_addr; reg [6:0] char_ram [0:4799]; // 80 * 60 = 4800 wire [6:0] ascii = char_ram[char_ram_addr]; always @(posedge sys_clk) begin if (wvram) char_ram[char_ram_addr] <= d_t_mem[6:0]; end // font_table 128 x 8 x 8 x 1 wire [12:0] ft_a = {ascii,font_row,font_col}; // ascii,row,col font_table ft (ft_a,font_dot); // i2c master controller wire csn = io_rdn & io_wrn; // chip select wire [1:0] addr = cpu_mem_a[3:2]; // i2c address wire [7:0] d_in = d_t_mem[7:0]; // data to be sent wire [7:0] d_out; // data out i2c eeprom (sys_clk,clrn,csn,addr,io_wrn,d_in,io_rdn,d_out,i2c_sda, i2c_scl); // cpu single_cycle_cpu_io cpu (sys_clk,clrn,pc,inst,cpu_mem_a,d_f_mem, d_t_mem,write,io_rdn,io_wrn,rvram,wvram); // instruction memory scinstmem_i2c_eeprom imem (pc,inst); // data memory wire [31:0] dm_out; // data mem data out scdatamem_i2c_eeprom dmem (sys_clk,cpu_mem_a,d_t_mem,write,dm_out); assign d_f_mem = io_rdn ? dm_out : {24'h0,d_out}; endmodule
source_codes/v/display_i2c_eeprom_tb.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ `timescale 1ns/1ns module display_i2c_eeprom_tb; reg sys_clk,clrn; reg scl_in,sda_in; // for assigning values to inout signals wire i2c_scl,i2c_sda; wire [7:0] r,g,b; wire hs,vs; wire vga_clk; wire blankn; wire syncn; display_i2c_eeprom ie (sys_clk,clrn,i2c_scl,i2c_sda, r,g,b,hs,vs,vga_clk,blankn,syncn); assign i2c_scl = scl_in; // assign to inout signal assign i2c_sda = sda_in; // assign to inout signal initial begin sda_in = 1'hz; scl_in = 1'hz; sys_clk = 1; clrn = 0; #5 clrn = 1; // ack for writing eeprom[0x0a55] = 0x43 #27515 sda_in = 0; // a0 ack #2500 sda_in = 1'hz; #22500 sda_in = 0; // 0a ack #2500 sda_in = 1'hz; #22500 sda_in = 0; // 55 ack #2500 sda_in = 1'hz; #22500 sda_in = 0; // 43 ack #2500 sda_in = 1'hz; // ack for reading eeprom[0x0a55] #32500 sda_in = 1; // a0 nack #2500 sda_in = 1'hz; #27500 sda_in = 1; // a0 nack #2500 sda_in = 1'hz; #27500 sda_in = 0; // a0 ack #2500 sda_in = 1'hz; #22500 sda_in = 0; // 0a ack #2500 sda_in = 1'hz; #22500 sda_in = 0; // 55 ack #2500 sda_in = 1'hz; #27500 sda_in = 0; // a1 ack #2500 sda_in = 1'hz; // 0x43 'C': output of eeprom[0x0a55] #2500 sda_in = 0; // bit 7 #2500 sda_in = 1; // bit 6 #2500 sda_in = 0; // bit 5 #2500 sda_in = 0; // bit 4 #2500 sda_in = 0; // bit 3 #2500 sda_in = 0; // bit 2 #2500 sda_in = 1; // bit 1 #2500 sda_in = 1; // bit 0 #2500 sda_in = 1'hz; // nack // 315 us end always #10 sys_clk = !sys_clk; // 50 MHz endmodule /* 1. 0 - 56 us 2. 56 - 112 us 3. 112 - 162 us 4. 162 - 212 us 5. 212 - 262 us 6. 262 - 312 us */
source_codes/v/display_scan_codes.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module display_scan_codes (sys_clk,clrn,ps2_clk,ps2_data,r,g,b,hs,vs, vga_clk,blankn,syncn); // display key scan codes input sys_clk, clrn; // sys_clk: 50MHz input ps2_clk, ps2_data; // kbd clk and data output [7:0] r, g, b; // vga red,green,blue colors output hs, vs; // vga h and v synchronization output vga_clk; // for ADV7123 VGA DAC output blankn; // for ADV7123 VGA DAC output syncn; // for ADV7123 VGA DAC wire font_dot; // font dot wire [31:0] inst,pc,d_t_mem,cpu_mem_a,d_f_mem; wire write,read,io_rdn,io_wrn,wvram,rvram,ready,overflow; wire [7:0] key_data; // kbd code byte // vga_clk reg vga_clk = 1; always @(posedge sys_clk) begin vga_clk <= ~vga_clk; // vga_clk: 25MHz end // vgac assign blankn = 1; assign syncn = 0; wire [8:0] row_addr; // pixel ram row addr, 480 (512) lines wire [9:0] col_addr; // pixel ram col addr, 640 (1024) pixels wire vga_rdn; // in vgac, rd_a = {row[8:0],col[9:0]} wire [23:0] vga_pixel = font_dot? 24'hffffff : 24'h0000ff; //white/blue vgac vga_24 (vga_clk,clrn,vga_pixel,row_addr,col_addr,vga_rdn, r,g,b,hs,vs); wire [5:0] char_row = row_addr[8:3]; // char row wire [2:0] font_row = row_addr[2:0]; // font row wire [6:0] char_col = col_addr[9:3]; // char col wire [2:0] font_col = col_addr[2:0]; // font col // char ram, 640/8 = 80 = 64 + 16; 480/8 = 60; wire [12:0] vga_cram_addr = (char_row<<6) + (char_row<<4) + char_col; wire [12:0] char_ram_addr = wvram? cpu_mem_a[14:2] : vga_cram_addr; reg [6:0] char_ram [0:4799]; // 80 * 60 = 4800 wire [6:0] ascii = char_ram[char_ram_addr]; always @(posedge sys_clk) begin if (wvram) begin char_ram[char_ram_addr] <= d_t_mem[6:0]; end end // font_table 128 x 8 x 8 x 1 wire [12:0] ft_a = {ascii,font_row,font_col}; // ascii,row,col font_table ft (ft_a,font_dot); // ps2_keyboard ps2_keyboard kbd (sys_clk,clrn,ps2_clk,ps2_data,io_rdn,key_data,ready, overflow); // cpu single_cycle_cpu_io cpu (sys_clk,clrn,pc,inst,cpu_mem_a,d_f_mem, d_t_mem,write,io_rdn,io_wrn,rvram,wvram); assign d_f_mem = io_rdn? {25'h0,ascii} : {23'h0,ready,key_data}; // instruction memory scinstmem_make_code_break_code imem (pc,inst); endmodule
source_codes/v/div_nonrestoring.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module div_nonrestoring (a,b,start,clk,clrn,q,r,busy,ready,count); input [31:0] a; // dividend input [15:0] b; // divisor input start; // start input clk, clrn; // clk,reset output [31:0] q; // quotient output [15:0] r; // remainder output reg busy; // busy output reg ready; // ready output [4:0] count; // count reg [31:0] reg_q; reg [15:0] reg_r; reg [15:0] reg_b; reg [4:0] count; wire [16:0] sub_add = reg_r[15]? {reg_r,reg_q[31]} + {1'b0,reg_b} : // + b {reg_r,reg_q[31]} - {1'b0,reg_b}; // - b assign q = reg_q; assign r = reg_r[15]? reg_r + reg_b : reg_r; // adjust r always @ (posedge clk or negedge clrn) begin if (!clrn) begin busy <= 0; ready <= 0; end else begin if (start) begin reg_q <= a; // load a reg_b <= b; // load b reg_r <= 0; busy <= 1; ready <= 0; count <= 0; end else if (busy) begin reg_q <= {reg_q[30:0],~sub_add[16]}; // << 1 reg_r <= sub_add[15:0]; count <= count + 5'b1; // count++ if (count == 5'h1f) begin // finish busy <= 0; ready <= 1; // q,r ready end end end end endmodule
source_codes/v/div_nonrestoring_tb.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ `timescale 1ns/1ns module div_nonrestoring_tb; reg [31:0] a; reg [15:0] b; reg start; reg clk,clrn; wire [31:0] q; wire [15:0] r; wire busy; wire ready; wire [4:0] count; div_nonrestoring div (a,b,start,clk,clrn,q,r,busy,ready,count); initial begin clrn = 0; start = 0; clk = 1; a = 32'h4c7f228a; b = 16'h6a0e; #5 clrn = 1; start = 1; #10 start = 0; #320 start = 1; #5 a = 32'h00ffff00; b = 16'h0004; #5 start = 0; end always #5 clk = !clk; endmodule
source_codes/v/div_restoring.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module div_restoring (a,b,start,clk,clrn,q,r,busy,ready,count); input [31:0] a; // dividend input [15:0] b; // divisor input start; // start input clk, clrn; // clk,reset output [31:0] q; // quotient output [15:0] r; // remainder output reg busy; // busy output reg ready; // ready output [4:0] count; // counter reg [31:0] reg_q; reg [15:0] reg_r; reg [15:0] reg_b; reg [4:0] count; wire [16:0] sub_out = {reg_r,reg_q[31]} - {1'b0,reg_b}; // sub wire [15:0] mux_out = sub_out[16]? // restoring {reg_r[14:0],reg_q[31]} : sub_out[15:0]; // or not assign q = reg_q; assign r = reg_r; always @ (posedge clk or negedge clrn) begin if (!clrn) begin busy <= 0; ready <= 0; end else begin if (start) begin reg_q <= a; // load a reg_b <= b; // load b reg_r <= 0; busy <= 1; ready <= 0; count <= 0; end else if (busy) begin reg_q <= {reg_q[30:0],~sub_out[16]}; // << 1 reg_r <= mux_out; count <= count + 5'b1; // counter++ if (count == 5'h1f) begin // finished busy <= 0; ready <= 1; // q,r ready end end end end endmodule
source_codes/v/div_restoring_tb.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ `timescale 1ns/1ns module div_restoring_tb; reg [31:0] a; reg [15:0] b; reg start; reg clk,clrn; wire [31:0] q; wire [15:0] r; wire busy; wire ready; wire [4:0] count; div_restoring div (a,b,start,clk,clrn,q,r,busy,ready,count); initial begin clrn = 0; start = 0; clk = 1; a = 32'h4c7f228a; b = 16'h6a0e; #5 clrn = 1; start = 1; #10 start = 0; #320 start = 1; #5 a = 32'h00ffff00; b = 16'h0004; #5 start = 0; end always #5 clk = !clk; endmodule
source_codes/v/encoder8ep.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module encoder8ep (d,ena,n,g); // 8-3 priority encoder with enable input [7:0] d; // input: d, 8 bits input ena; // input: enable output [2:0] n; // outputs: n, log_2 8 = 3 bits output g; // output: g = 1 if d is not 0 assign g = ena & |d; // if there is at least a 1 in d assign n = enc(ena, d); // call a function enc function [2:0] enc; // the function enc input e; // input of the function input [7:0] d; // input of the function casex ({e,d}) // cases, x: don't care 9'b1_1xxxxxxx: enc = 3'd7; // d[7] has the highest priority 9'b1_01xxxxxx: enc = 3'd6; // d[6] is active, ignore d[5:0] 9'b1_001xxxxx: enc = 3'd5; // d[5] is active, ignore d[4:0] 9'b1_0001xxxx: enc = 3'd4; // d[4] is active, ignore d[3:0] 9'b1_00001xxx: enc = 3'd3; // d[3] is active, ignore d[2:0] 9'b1_000001xx: enc = 3'd2; // d[2] is active, ignore d[1:0] 9'b1_0000001x: enc = 3'd1; // d[1] is active, ignore d[0] default: enc = 3'd0; // d[0] has the lowest priority endcase endfunction endmodule
source_codes/v/encoder8ep_tb.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ `timescale 1ns/1ns module encoder8ep_tb; reg [7:0] d; reg ena; wire [2:0] n; wire g; integer i; encoder8ep enc (d,ena,n,g); initial begin #0 $display("time\tena\td\t\tn\tg"); #0 ena = 1; #0 d = 8'b1xxxxxxx; for (i = 0; i < 8; i = i + 1) #1 d = d >> 1; #1 ena = 0; d = 8'bxxxxxxxx; #1 $finish; end initial begin $monitor("%1d\t%b\t%b\t%b\t%b",$time,ena,d,n,g); end endmodule
source_codes/v/f2i.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module f2i (a,d,p_lost,denorm,invalid); // convert float to integer input [31:0] a; // float output [31:0] d; // integer output p_lost; // precision lost output denorm; // denormalized output invalid; // inf,nan,out_of_range reg [31:0] d; // will be combinational reg p_lost; // will be combinational reg invalid; // will be combinational wire hidden_bit = |a[30:23]; // hidden bit wire frac_is_not_0 = |a[22:0]; assign denorm = ~hidden_bit & frac_is_not_0; wire is_zero = ~hidden_bit & ~frac_is_not_0; wire sign = a[31]; // sign wire [8:0] shift_right_bits = 9'd158 - {1'b0,a[30:23]}; // 127 + 31 wire [55:0] frac0 = {hidden_bit,a[22:0],32'h0}; // 32 + 24 = 56 bits wire [55:0] f_abs = ($signed(shift_right_bits) > 9'd32)? // shift frac0 >> 6'd32 : frac0 >> shift_right_bits; wire lost_bits = |f_abs[23:0]; // if != 0, p_lost = 1 wire [31:0] int32 = sign? ~f_abs[55:24] + 32'd1 : f_abs[55:24]; always @ * begin if (denorm) begin //denormalized p_lost = 1; invalid = 0; d = 32'h00000000; end else begin // not denormalized if (shift_right_bits[8]) begin // too big p_lost = 0; invalid = 1; d = 32'h80000000; end else begin // shift right if (shift_right_bits[7:0] > 8'h1f) begin // too small if (is_zero) p_lost = 0; else p_lost = 1; invalid = 0; d = 32'h00000000; end else begin if (sign != int32[31]) begin // out of range p_lost = 0; invalid = 1; d = 32'h80000000; end else begin // normal case if (lost_bits) p_lost = 1; else p_lost = 0; invalid = 0; d = int32; end end end end end endmodule
source_codes/v/f2i_tb.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ `timescale 1ns/1ns module f2i_tb; reg [31:0] a; wire [31:0] d; wire p_lost; wire denorm; wire invalid; f2i f_i (a,d,p_lost,denorm,invalid); initial begin #00 a = 32'h4effffff; #10 a = 32'h4f000000; #10 a = 32'h3f800000; #10 a = 32'h3f000000; #10 a = 32'h00000001; #10 a = 32'h7f800000; #10 a = 32'h3fc00000; #10 a = 32'hcf000000; #10 a = 32'hcf000001; #10 a = 32'hbf800000; #10 a = 32'hbf7fffff; #10 a = 32'h80000001; #10 a = 32'hff800000; #10 a = 32'h00000000; end endmodule
source_codes/v/fa_behavioral.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module fa_behavioral (a,b,ci,s,co); // full adder, behavioral style input a, b, ci; // inputs: a, b, carry_in output s, co; // outputs: sum, carry_out assign {co,s} = a + b + ci; // two-bit {co,s} output endmodule
source_codes/v/fa_structural.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module fa_structural (a,b,ci,s,co); // full adder, structural style input a, b, ci; // inputs: a, b, carry_in output s, co; // outputs: sum, carry_out wire ab, bc, ca; // wires, outputs of and gates xor i1 (s, a, b, ci); // xor (out, in1, in2, in3); and i2 (ab, a, b); // and (out, in1, in2); and i3 (bc, b, ci); // and (out, in1, in2); and i4 (ca, ci, a); // and (out, in1, in2); or i5 (co, ab, bc, ca); // or (out, in1, in2, in3); endmodule
source_codes/v/fadd_align.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module fadd_align (a,b,sub,s_is_nan,s_is_inf,inf_nan_frac,sign,temp_exp, op_sub,large_frac24,small_frac27); //alignment stage input [31:0] a,b; input sub; output [26:0] small_frac27; output [23:0] large_frac24; output [22:0] inf_nan_frac; output [7:0] temp_exp; output s_is_nan; output s_is_inf; output sign; output op_sub; wire exchange = (b[30:0] > a[30:0]); wire [31:0] fp_large = exchange? b : a; wire [31:0] fp_small = exchange? a : b; wire fp_large_hidden_bit = |fp_large[30:23]; wire fp_small_hidden_bit = |fp_small[30:23]; wire [23:0] large_frac24 = {fp_large_hidden_bit,fp_large[22:0]}; wire [23:0] small_frac24 = {fp_small_hidden_bit,fp_small[22:0]}; assign temp_exp = fp_large[30:23]; assign sign = exchange? sub ^ b[31] : a[31]; assign op_sub = sub ^ fp_large[31] ^ fp_small[31]; wire fp_large_expo_is_ff = &fp_large[30:23]; // exp == 0xff wire fp_small_expo_is_ff = &fp_small[30:23]; wire fp_large_frac_is_00 = ~|fp_large[22:0]; // frac == 0x0 wire fp_small_frac_is_00 = ~|fp_small[22:0]; wire fp_large_is_inf=fp_large_expo_is_ff & fp_large_frac_is_00; wire fp_small_is_inf=fp_small_expo_is_ff & fp_small_frac_is_00; wire fp_large_is_nan=fp_large_expo_is_ff &~fp_large_frac_is_00; wire fp_small_is_nan=fp_small_expo_is_ff &~fp_small_frac_is_00; assign s_is_inf = fp_large_is_inf | fp_small_is_inf; wire s_is_nan = fp_large_is_nan | fp_small_is_nan | ((sub ^ fp_small[31] ^ fp_large[31]) & fp_large_is_inf & fp_small_is_inf); wire [22:0] nan_frac = (a[21:0] > b[21:0])? {1'b1,a[21:0]} : {1'b1,b[21:0]}; assign inf_nan_frac = s_is_nan? nan_frac : 23'h0; wire [7:0] exp_diff = fp_large[30:23] - fp_small[30:23]; wire small_den_only = (fp_large[30:23] != 0) & (fp_small[30:23] == 0); wire [7:0] shift_amount = small_den_only? exp_diff - 8'h1 : exp_diff; wire [49:0] small_frac50 = (shift_amount >= 26)? {26'h0,small_frac24} : {small_frac24,26'h0} >> shift_amount; assign small_frac27 = {small_frac50[49:24],|small_frac50[23:0]}; endmodule
source_codes/v/fadd_cal.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module fadd_cal (op_sub,large_frac24,small_frac27, cal_frac); // calculation input [23:0] large_frac24; input op_sub; input [26:0] small_frac27; output [27:0] cal_frac; wire [27:0] aligned_large_frac = {1'b0,large_frac24,3'b000}; wire [27:0] aligned_small_frac = {1'b0,small_frac27}; assign cal_frac = op_sub? aligned_large_frac - aligned_small_frac : aligned_large_frac + aligned_small_frac; endmodule
source_codes/v/fadd_norm.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module fadd_norm (rm,is_nan,is_inf,inf_nan_frac,sign,temp_exp,cal_frac,s); input [27:0] cal_frac; input [22:0] inf_nan_frac; input [7:0] temp_exp; input [1:0] rm; input is_nan,is_inf; input sign; output [31:0] s; wire [26:0] f4,f3,f2,f1,f0; wire [4:0] zeros; assign zeros[4] = ~|cal_frac[26:11]; // 16-bit 0 assign f4 = zeros[4]? {cal_frac[10:0],16'b0} : cal_frac[26:0]; assign zeros[3] = ~|f4[26:19]; // 8-bit 0 assign f3 = zeros[3]? {f4[18:0], 8'b0} : f4; assign zeros[2] = ~|f3[26:23]; // 4-bit 0 assign f2 = zeros[2]? {f3[22:0], 4'b0} : f3; assign zeros[1] = ~|f2[26:25]; // 2-bit 0 assign f1 = zeros[1]? {f2[24:0], 2'b0} : f2; assign zeros[0] = ~f1[26]; // 1-bit 0 assign f0 = zeros[0]? {f1[25:0], 1'b0} : f1; reg [26:0] frac0; reg [7:0] exp0; always @ * begin if (cal_frac[27]) begin frac0 = cal_frac[27:1]; // 1x.xxxxxxxxxxxxxxxxxxxxxxx xxx exp0 = temp_exp + 8'h1; // 1.xxxxxxxxxxxxxxxxxxxxxxx xxx end else begin if ((temp_exp > zeros) && (f0[26])) begin // a normalized number exp0 = temp_exp - zeros; frac0 = f0; // 01.xxxxxxxxxxxxxxxxxxxxxxx xxx end else begin // is a denormalized number or 0 exp0 = 0; if (temp_exp != 0) // (e - 127) = ((e - 1) - 126) frac0 = cal_frac[26:0] << (temp_exp - 8'h1); else frac0 = cal_frac[26:0]; end end end wire frac_plus_1 = // for rounding ~rm[1] & ~rm[0] & frac0[2] & (frac0[1] | frac0[0]) | ~rm[1] & ~rm[0] & frac0[2] & ~frac0[1] & ~frac0[0] & frac0[3] | ~rm[1] & rm[0] & (frac0[2] | frac0[1] | frac0[0]) & sign | rm[1] & ~rm[0] & (frac0[2] | frac0[1] | frac0[0]) & ~sign; wire [24:0] frac_round = {1'b0,frac0[26:3]} + frac_plus_1; wire [7:0] exponent = frac_round[24]? exp0 + 8'h1 : exp0; wire overflow = &exp0 | &exponent; assign s = final_result(overflow, rm, sign, is_nan, is_inf, exponent, frac_round[22:0], inf_nan_frac); function [31:0] final_result; input overflow; input [1:0] rm; input sign, is_nan, is_inf; input [7:0] exponent; input [22:0] fraction, inf_nan_frac; casex ({overflow, rm, sign, is_nan, is_inf}) 6'b1_00_x_0_x : final_result = {sign,8'hff,23'h000000}; // inf 6'b1_01_0_0_x : final_result = {sign,8'hfe,23'h7fffff}; // max 6'b1_01_1_0_x : final_result = {sign,8'hff,23'h000000}; // inf 6'b1_10_0_0_x : final_result = {sign,8'hff,23'h000000}; // inf 6'b1_10_1_0_x : final_result = {sign,8'hfe,23'h7fffff}; // max 6'b1_11_x_0_x : final_result = {sign,8'hfe,23'h7fffff}; // max 6'b0_xx_x_0_0 : final_result = {sign,exponent,fraction}; // nor 6'bx_xx_x_1_x : final_result = {1'b1,8'hff,inf_nan_frac}; // nan 6'bx_xx_x_0_1 : final_result = {sign,8'hff,inf_nan_frac}; // inf default : final_result = {sign,8'h00,23'h000000}; // 0 endcase endfunction endmodule
source_codes/v/fadder.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module fadder (a,b,sub,rm,s); // fadder input [31:0] a,b; // fp a and b input [1:0] rm; // round mode input sub; // 1: sub; 0: add output [31:0] s; // fp output wire exchange = ({1'b0,b[30:0]} > {1'b0,a[30:0]}); wire [31:0] fp_large = exchange? b : a; wire [31:0] fp_small = exchange? a : b; wire fp_large_hidden_bit = |fp_large[30:23]; wire fp_small_hidden_bit = |fp_small[30:23]; wire [23:0] large_frac24 = {fp_large_hidden_bit,fp_large[22:0]}; wire [23:0] small_frac24 = {fp_small_hidden_bit,fp_small[22:0]}; wire [7:0] temp_exp = fp_large[30:23]; wire sign = exchange? sub ^ b[31] : a[31]; wire op_sub = sub ^ fp_large[31] ^ fp_small[31]; wire fp_large_expo_is_ff = &fp_large[30:23]; // exp == 0xff wire fp_small_expo_is_ff = &fp_small[30:23]; wire fp_large_frac_is_00 = ~|fp_large[22:0]; // frac == 0x0 wire fp_small_frac_is_00 = ~|fp_small[22:0]; wire fp_large_is_inf=fp_large_expo_is_ff & fp_large_frac_is_00; wire fp_small_is_inf=fp_small_expo_is_ff & fp_small_frac_is_00; wire fp_large_is_nan=fp_large_expo_is_ff &~fp_large_frac_is_00; wire fp_small_is_nan=fp_small_expo_is_ff &~fp_small_frac_is_00; wire s_is_inf = fp_large_is_inf | fp_small_is_inf; wire s_is_nan = fp_large_is_nan | fp_small_is_nan | ((sub ^ fp_small[31] ^ fp_large[31]) & fp_large_is_inf & fp_small_is_inf); wire [22:0] nan_frac = ({1'b0,a[22:0]} > {1'b0,b[22:0]}) ? {1'b1,a[21:0]} : {1'b1,b[21:0]}; wire [22:0] inf_nan_frac = s_is_nan? nan_frac : 23'h0; wire [7:0] exp_diff = fp_large[30:23] - fp_small[30:23]; wire small_den_only = (fp_large[30:23] != 0) & (fp_small[30:23] == 0); wire [7:0] shift_amount = small_den_only? exp_diff - 8'h1 : exp_diff; wire [49:0] small_frac50 = (shift_amount >= 26)? {26'h0,small_frac24} : {small_frac24,26'h0} >> shift_amount; wire [26:0] small_frac27 = {small_frac50[49:24],|small_frac50[23:0]}; wire [27:0] aligned_large_frac = {1'b0,large_frac24,3'b000}; wire [27:0] aligned_small_frac = {1'b0,small_frac27}; wire [27:0] cal_frac = op_sub? aligned_large_frac - aligned_small_frac : aligned_large_frac + aligned_small_frac; wire [26:0] f4,f3,f2,f1,f0; wire [4:0] zeros; assign zeros[4] = ~|cal_frac[26:11]; // 16-bit 0 assign f4 = zeros[4]? {cal_frac[10:0],16'b0} : cal_frac[26:0]; assign zeros[3] = ~|f4[26:19]; // 8-bit 0 assign f3 = zeros[3]? {f4[18:0], 8'b0} : f4; assign zeros[2] = ~|f3[26:23]; // 4-bit 0 assign f2 = zeros[2]? {f3[22:0], 4'b0} : f3; assign zeros[1] = ~|f2[26:25]; // 2-bit 0 assign f1 = zeros[1]? {f2[24:0], 2'b0} : f2; assign zeros[0] = ~f1[26]; // 1-bit 0 assign f0 = zeros[0]? {f1[25:0], 1'b0} : f1; reg [7:0] exp0; reg [26:0] frac0; always @ * begin if (cal_frac[27]) begin // 1x.xxxxxxxxxxxxxxxxxxxxxxx xxx frac0 = cal_frac[27:1]; // 1.xxxxxxxxxxxxxxxxxxxxxxx xxx exp0 = temp_exp + 8'h1; end else begin if ((temp_exp > zeros) && (f0[26])) begin // a normalized number exp0 = temp_exp - zeros; frac0 = f0; // 1.xxxxxxxxxxxxxxxxxxxxxxx xxx end else begin // is a denormalized number or 0 exp0 = 0; if (temp_exp != 0) // (e - 127) = ((e - 1) - 126) frac0 = cal_frac[26:0] << (temp_exp - 8'h1); else frac0 = cal_frac[26:0]; end end end wire frac_plus_1 = // for rounding ~rm[1] & ~rm[0] & frac0[2] & (frac0[1] | frac0[0]) | ~rm[1] & ~rm[0] & frac0[2] & ~frac0[1] & ~frac0[0] & frac0[3] | ~rm[1] & rm[0] & (frac0[2] | frac0[1] | frac0[0]) & sign | rm[1] & ~rm[0] & (frac0[2] | frac0[1] | frac0[0]) & ~sign; wire [24:0] frac_round = {1'b0,frac0[26:3]} + frac_plus_1; wire [7:0] exponent = frac_round[24]? exp0 + 8'h1 : exp0; wire overflow = &exp0 | &exponent; assign s = final_result(overflow,rm,sign,s_is_nan,s_is_inf,exponent, frac_round[22:0],inf_nan_frac); function [31:0] final_result; input overflow; input [1:0] rm; input sign; input is_nan; input is_inf; input [7:0] exponent; input [22:0] fraction, inf_nan_frac; casex ({overflow,rm,sign,s_is_nan,s_is_inf}) 6'b1_00_x_0_x : final_result = {sign,8'hff,23'h000000}; // inf 6'b1_01_0_0_x : final_result = {sign,8'hfe,23'h7fffff}; // max 6'b1_01_1_0_x : final_result = {sign,8'hff,23'h000000}; // inf 6'b1_10_0_0_x : final_result = {sign,8'hff,23'h000000}; // inf 6'b1_10_1_0_x : final_result = {sign,8'hfe,23'h7fffff}; // max 6'b1_11_x_0_x : final_result = {sign,8'hfe,23'h7fffff}; // max 6'b0_xx_x_0_0 : final_result = {sign,exponent,fraction}; // nor 6'bx_xx_x_1_x : final_result = {1'b1,8'hff,inf_nan_frac}; // nan 6'bx_xx_x_0_1 : final_result = {sign,8'hff,inf_nan_frac}; // inf default : final_result = {sign,8'h00,23'h000000}; // 0 endcase endfunction endmodule
source_codes/v/fadder_tb.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ `timescale 1ns/1ns module fadder_tb; reg [31:0] a, b; reg sub; reg [1:0] rm; wire [31:0] s; fadder fa (a,b,sub,rm,s); initial begin rm = 0; sub = 1; a = 32'h3c600011; b = 32'hbe820000; #10 rm = 2'h1; #10 rm = 2'h2; #10 rm = 2'h3; #10 rm = 2'h0; sub = 0; #10 rm = 2'h1; #10 rm = 2'h2; #10 rm = 2'h3; #10 rm = 2'h0; sub = 1; a = 32'h3fffffff; b = 32'hb3800000; #10 rm = 2'h1; #10 rm = 2'h2; #10 rm = 2'h3; #10 rm = 2'h0; sub = 0; #10 rm = 2'h1; #10 rm = 2'h2; #10 rm = 2'h3; #10 rm = 2'h0; a = 32'h7f800000; b = 32'h7f800000; #10 sub = 1; #10 sub = 0; a = 32'h7f00ffff; b = 32'h7fe0000f; #10 sub = 0; a = 32'h7f7fffff; b = 32'h7f7fffff; #10 sub = 0; a = 32'h7f00ffff; b = 32'h00000000; #10 sub = 0; a = 32'h00800000; b = 32'h007fffff; #10 sub = 0; a = 32'h00000007; b = 32'h00000008; #10 sub = 1; end endmodule
source_codes/v/fdiv_newton.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module fdiv_newton (a,b,rm,fdiv,ena,clk,clrn, s,busy,stall,count,reg_x); input [31:0] a,b; // fp s = a / b input [1:0] rm; // round mode input fdiv; // ID stage: fdiv = i_fdiv input ena; // enable input clk, clrn; // clock and reset output [31:0] s; // fp output output [25:0] reg_x; // x_i output [4:0] count; // for iteration control output busy; // for generating stall output stall; // for pipeline stall parameter ZERO = 31'h00000000; parameter INF = 31'h7f800000; parameter NaN = 31'h7fc00000; parameter MAX = 31'h7f7fffff; wire a_expo_is_00 = ~|a[30:23]; // a_expo = 00 wire b_expo_is_00 = ~|b[30:23]; // b_expo = 00 wire a_expo_is_ff = &a[30:23]; // a_expo = ff wire b_expo_is_ff = &b[30:23]; // b_expo = ff wire a_frac_is_00 = ~|a[22:0]; // a_frac = 00 wire b_frac_is_00 = ~|b[22:0]; // b_frac = 00 wire sign = a[31] ^ b[31]; wire [9:0] exp_10 = {2'h0,a[30:23]} - {2'h0,b[30:23]} + 10'h7f; wire [23:0] a_temp24 = a_expo_is_00? {a[22:0],1'b0} : {1'b1,a[22:0]}; wire [23:0] b_temp24 = b_expo_is_00? {b[22:0],1'b0} : {1'b1,b[22:0]}; wire [23:0] a_frac24,b_frac24; // to 1xx...x for denormalized number wire [4:0] shamt_a,shamt_b; // how many bits shifted shift_to_msb_equ_1 shift_a (a_temp24,a_frac24,shamt_a); // to 1xx...xx shift_to_msb_equ_1 shift_b (b_temp24,b_frac24,shamt_b); // to 1xx...xx wire [9:0] exp10 = exp_10 - shamt_a + shamt_b; reg e1_sign,e1_ae00,e1_aeff,e1_af00,e1_be00,e1_beff,e1_bf00; reg e2_sign,e2_ae00,e2_aeff,e2_af00,e2_be00,e2_beff,e2_bf00; reg e3_sign,e3_ae00,e3_aeff,e3_af00,e3_be00,e3_beff,e3_bf00; reg [1:0] e1_rm,e2_rm,e3_rm; reg [9:0] e1_exp10,e2_exp10,e3_exp10; always @ (negedge clrn or posedge clk) if (!clrn) begin // 3 pipeline registers: reg_e1, reg_e2, and reg_e3 // reg_e1 // reg_e2 // reg_e3 e1_sign <= 0; e2_sign <= 0; e3_sign <= 0; e1_rm <= 0; e2_rm <= 0; e3_rm <= 0; e1_exp10<= 0; e2_exp10<= 0; e3_exp10<= 0; e1_ae00 <= 0; e2_ae00 <= 0; e3_ae00 <= 0; e1_aeff <= 0; e2_aeff <= 0; e3_aeff <= 0; e1_af00 <= 0; e2_af00 <= 0; e3_af00 <= 0; e1_be00 <= 0; e2_be00 <= 0; e3_be00 <= 0; e1_beff <= 0; e2_beff <= 0; e3_beff <= 0; e1_bf00 <= 0; e2_bf00 <= 0; e3_bf00 <= 0; end else if (ena) begin e1_sign <= sign; e2_sign <= e1_sign; e3_sign <= e2_sign; e1_rm <= rm; e2_rm <= e1_rm; e3_rm <= e2_rm; e1_exp10<= exp10; e2_exp10<= e1_exp10; e3_exp10<= e2_exp10; e1_ae00 <= a_expo_is_00; e2_ae00 <= e1_ae00; e3_ae00 <= e2_ae00; e1_aeff <= a_expo_is_ff; e2_aeff <= e1_aeff; e3_aeff <= e2_aeff; e1_af00 <= a_frac_is_00; e2_af00 <= e1_af00; e3_af00 <= e2_af00; e1_be00 <= b_expo_is_00; e2_be00 <= e1_be00; e3_be00 <= e2_be00; e1_beff <= b_expo_is_ff; e2_beff <= e1_beff; e3_beff <= e2_beff; e1_bf00 <= b_frac_is_00; e2_bf00 <= e1_bf00; e3_bf00 <= e2_bf00; end wire [31:0] q; // af24 / bf24 = 1.xxxxx...x or 0.1xxxx...x newton24 frac_newton (a_frac24,b_frac24,fdiv,ena,clk,clrn, q,busy,count,reg_x,stall); wire [31:0] z0 = q[31] ? q : {q[30:0],1'b0}; // 1.xxxxx...x wire [9:0] exp_adj = q[31] ? e3_exp10 : e3_exp10 - 10'b1; reg [9:0] exp0; reg [31:0] frac0; always @ * begin if (exp_adj[9]) begin // exp is negative exp0 = 0; if (z0[31]) // 1.xx...x frac0 = z0 >> (10'b1 - exp_adj); // denormalized (-126) else frac0 = 0; end else if (exp_adj == 0) begin // exp is 0 exp0 = 0; frac0 = {1'b0,z0[31:2],|z0[1:0]}; // denormalized (-126) end else begin // exp > 0 if (exp_adj > 254) begin // inf exp0 = 10'hff; frac0 = 0; end else begin // normalized exp0 = exp_adj; frac0 = z0; end end end wire [26:0] frac = {frac0[31:6],|frac0[5:0]}; // sticky wire frac_plus_1 = ~e3_rm[1] & ~e3_rm[0] & frac[3] & frac[2] & ~frac[1] & ~frac[0] | ~e3_rm[1] & ~e3_rm[0] & frac[2] & (frac[1] | frac[0]) | ~e3_rm[1] & e3_rm[0] & (frac[2] | frac[1] | frac[0]) & e3_sign | e3_rm[1] & ~e3_rm[0] & (frac[2] | frac[1] | frac[0]) & ~e3_sign; wire [24:0] frac_round = {1'b0,frac[26:3]} + frac_plus_1; wire [9:0] exp1 = frac_round[24]? exp0 + 10'h1 : exp0; wire overflow = (exp1 >= 10'h0ff); // overflow wire [7:0] exponent; wire [22:0] fraction; assign {exponent,fraction} = final_result(overflow,e3_rm,e3_sign, e3_ae00,e3_aeff,e3_af00,e3_be00,e3_beff, e3_bf00,{exp1[7:0],frac_round[22:0]}); assign s = {e3_sign,exponent,fraction}; function [30:0] final_result; input overflow; input [1:0] e3_rm; input e3_sign; input a_e00,a_eff,a_f00, b_e00,b_eff,b_f00; input [30:0] calc; casex ({overflow,e3_rm,e3_sign,a_e00,a_eff,a_f00,b_e00,b_eff,b_f00}) 10'b100x_xxx_xxx : final_result = INF; // overflow 10'b1010_xxx_xxx : final_result = MAX; // overflow 10'b1011_xxx_xxx : final_result = INF; // overflow 10'b1100_xxx_xxx : final_result = INF; // overflow 10'b1101_xxx_xxx : final_result = MAX; // overflow 10'b111x_xxx_xxx : final_result = MAX; // overflow 10'b0xxx_010_xxx : final_result = NaN; // NaN / any 10'b0xxx_011_010 : final_result = NaN; // inf / NaN 10'b0xxx_100_010 : final_result = NaN; // den / NaN 10'b0xxx_101_010 : final_result = NaN; // 0 / NaN 10'b0xxx_00x_010 : final_result = NaN; // nor / NaN 10'b0xxx_011_011 : final_result = NaN; // inf / inf 10'b0xxx_100_011 : final_result = ZERO; // den / inf 10'b0xxx_101_011 : final_result = ZERO; // 0 / inf 10'b0xxx_00x_011 : final_result = ZERO; // nor / inf 10'b0xxx_011_101 : final_result = INF; // inf / 0 10'b0xxx_100_101 : final_result = INF; // den / 0 10'b0xxx_101_101 : final_result = NaN; // 0 / 0 10'b0xxx_00x_101 : final_result = INF; // nor / 0 10'b0xxx_011_100 : final_result = INF; // inf / den 10'b0xxx_100_100 : final_result = calc; // den / den 10'b0xxx_101_100 : final_result = ZERO; // 0 / den 10'b0xxx_00x_100 : final_result = calc; // nor / den 10'b0xxx_011_00x : final_result = INF; // inf / nor 10'b0xxx_100_00x : final_result = calc; // den / nor 10'b0xxx_101_00x : final_result = ZERO; // 0 / nor 10'b0xxx_00x_00x : final_result = calc; // nor / nor default : final_result = ZERO; endcase endfunction endmodule
source_codes/v/fdiv_newton_tb.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ `timescale 1ns/1ns module fdiv_newton_tb; reg [31:0] a, b; reg [1:0] rm; reg fdiv; reg ena; reg clk, clrn; wire [31:0] s; wire busy; wire stall; wire [4:0] count; wire [25:0] reg_x; fdiv_newton fdn (a,b,rm,fdiv,ena,clk,clrn,s,busy,stall,count,reg_x); initial begin clk = 1; clrn = 0; rm = 0; ena = 1; fdiv = 0; a = 32'h41000000; b = 32'h40800000; #2 clrn = 1; #13 fdiv = 1; #154 fdiv = 0; #71 a = 32'h0000fe01; b = 32'h000000ff; #15 fdiv = 1; #154 fdiv = 0; end always #5 clk = !clk; endmodule
source_codes/v/fifo.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module fifo (clk,clrn,read,write,data_in,data_out,ready,overflow); // fifo input clk, clrn; // clock and reset input read; // fifo read, active high input write; // fifo write, active high input [7:0] data_in; // fifo data input output [7:0] data_out; // fifo data output output ready; // fifo has data output reg overflow; // fifo overflow flag reg [7:0] fifo_buff [7:0]; // fifo buffer of depth 8 reg [2:0] write_pointer; // fifo write pointer reg [2:0] read_pointer; // fifo read pointer always @ (posedge clk or negedge clrn) begin if (!clrn) begin write_pointer <= 0; // clear write pointer read_pointer <= 0; // clear read pointer overflow <= 0; // clear overflow flag end else begin if (write) begin if ((write_pointer + 3'b1) != read_pointer) begin fifo_buff[write_pointer] <= data_in; // push data write_pointer <= write_pointer + 3'd1; // pointer++ end else begin overflow <= 1; // overflow end end if (read && ready) begin read_pointer <= read_pointer + 3'd1; // pointer++, pop overflow <= 0; // clear overflow end end end assign ready = (write_pointer != read_pointer); // has data assign data_out = fifo_buff[read_pointer]; // data output endmodule
source_codes/v/fifo_tb.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ `timescale 1ns/1ns module fifo_tb; reg clk,clrn; reg read; reg write; reg [7:0] data_in; wire [7:0] data_out; wire ready; wire overflow; fifo queue (clk,clrn,read,write,data_in,data_out,ready,overflow); initial begin clk = 0; clrn = 0; read = 0; write = 0; #20 clrn = 1; data_in = 8'he0; write = 1; #20 data_in = 8'he1; #20 data_in = 8'he2; #20 data_in = 8'he3; #20 data_in = 8'he4; #20 data_in = 8'he5; read = 1; #20 data_in = 8'he6; #20 data_in = 8'he7; #20 data_in = 8'he8; read = 0; #20 data_in = 8'he9; #20 data_in = 8'hea; #20 data_in = 8'heb; #20 data_in = 8'hec; #20 data_in = 8'hed; #20 data_in = 8'hee; #20 data_in = 8'hef; #20 data_in = 8'hf0; read = 1; #20 data_in = 8'hf1; #20 data_in = 8'hf2; read = 0; #20 data_in = 8'hf3; read = 1; #20 data_in = 8'hf4; write = 0; end always #10 clk = !clk; endmodule
source_codes/v/fifo4.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module fifo4 (clr, write, din, read, dout, full, empty); input clr; input write; input [7:0] din; input read; output [7:0] dout; output full; output empty; wire clk1, clk2, clk3, clk4; wire [7:0] d12, d23, d34; wire q1, q2, q3; wire qn1, qn2, qn3, qn4; wire write_n; wire pulse; ff8 r1 (clk1, din, d12); ff8 r2 (clk2, d12, d23); ff8 r3 (clk3, d23, d34); ff8 r4 (clk4, d34, dout); latch f1 (clr, clk1, clk2, q1, qn1); latch f2 (clr, clk2, clk3, q2, qn2); latch f3 (clr, clk3, clk4, q3, qn3); latch f4 (clr, clk4, read, q4, qn4); ffc fc (write, clk1 | clr, ~clr, pulse); and #1 a1 (clk1, pulse, qn1); and #1 a2 (clk2, q1, qn2); and #1 a3 (clk3, q2, qn3); and #1 a4 (clk4, q3, qn4, ~read); assign full = q1; assign empty = qn4; endmodule module latch (clr, s, r, q, qn); input clr; input s; input r; output q; output qn; nor nor1 (q, r, clr, qn); nor nor2 (qn, s, q); endmodule module ff8 (clk, d, q); input clk; input [7:0] d; output [7:0] q; reg [7:0] q; always @ (posedge clk) q <= d; endmodule module ffc (clk, clr, d, q); input clk, clr; input d; output q; reg q; always @ (posedge clk or posedge clr) if (clr) q <= 0; else q <= d; endmodule
source_codes/v/fifo4_tb.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ `timescale 1ns/1ns module fifo4_tb; reg clr; reg write; reg [7:0] din; reg read; wire [7:0] dout; wire full; wire empty; fifo4 queue4 (clr,write,din,read,dout,full,empty); initial begin clr = 1; write = 0; read = 0; #20 clr = 0; din = 8'he1; #5 write = 1; #10 write = 0; #5 din = 8'he2; #5 write = 1; #10 write = 0; #5 din = 8'he3; #5 write = 1; #10 write = 0; #5 din = 8'he4; #5 write = 1; #10 write = 0; #10 read = 1; #10 read = 0; #10 read = 1; #10 read = 0; #10 read = 1; #10 read = 0; #10 read = 1; #10 read = 0; end endmodule
source_codes/v/fmul.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module fmul (a,b,rm,s); // fmul input [31:0] a,b; // fp a and b input [1:0] rm; // round mode output [31:0] s; // fp output wire a_expo_is_00 = ~|a[30:23]; // exp = 00 wire b_expo_is_00 = ~|b[30:23]; wire a_expo_is_ff = &a[30:23]; // exp = ff wire b_expo_is_ff = &b[30:23]; wire a_frac_is_00 = ~|a[22:0]; // frac = 0 wire b_frac_is_00 = ~|b[22:0]; wire a_is_inf = a_expo_is_ff & a_frac_is_00; wire b_is_inf = b_expo_is_ff & b_frac_is_00; wire a_is_nan = a_expo_is_ff & ~a_frac_is_00; wire b_is_nan = b_expo_is_ff & ~b_frac_is_00; wire a_is_0 = a_expo_is_00 & a_frac_is_00; wire b_is_0 = b_expo_is_00 & b_frac_is_00; wire s_is_inf = a_is_inf | b_is_inf; wire s_is_nan = a_is_nan | (a_is_inf & b_is_0) | b_is_nan | (b_is_inf & a_is_0); wire [22:0] nan_frac = (a[21:0] > b[21:0])? {1'b1,a[21:0]} : {1'b1,b[21:0]}; wire [22:0] inf_nan_frac = s_is_nan? nan_frac : 23'h0; wire sign = a[31] ^ b[31]; wire [9:0] exp10 = {2'h0,a[30:23]} + {2'h0,b[30:23]} - 10'h7f + a_expo_is_00 + b_expo_is_00; // -126 wire [23:0] a_frac24 = {~a_expo_is_00,a[22:0]}; wire [23:0] b_frac24 = {~b_expo_is_00,b[22:0]}; wire [47:0] z; wire [47:8] z_sum; wire [47:8] z_carry; // multiplication 1 (carry and sum generated by wallace tree) wallace_24x24 wt24 (a_frac24,b_frac24,z_sum,z_carry,z[7:0]); // multiplication 2 (product by adding carry and sum) assign z[47:8] = {1'b0,z_sum} + z_carry; // xx.xxxxxxxxxxxx... // normalization wire [46:0] z5,z4,z3,z2,z1,z0; // x.xxxxxxxxxxxxxxxxxxxxxxxxxx... wire [5:0] zeros; assign zeros[5] = ~|z[46:15]; // 32-bit 0 assign z5 = zeros[5]? {z[14:0],32'b0} : z[46:0]; assign zeros[4] = ~|z5[46:31]; // 16-bit 0 assign z4 = zeros[4]? {z5[30:0],16'b0} : z5; assign zeros[3] = ~|z4[46:39]; // 8-bit 0 assign z3 = zeros[3]? {z4[38:0], 8'b0} : z4; assign zeros[2] = ~|z3[46:43]; // 4-bit 0 assign z2 = zeros[2]? {z3[42:0], 4'b0} : z3; assign zeros[1] = ~|z2[46:45]; // 2-bit 0 assign z1 = zeros[1]? {z2[44:0], 2'b0} : z2; assign zeros[0] = ~z1[46]; // 1-bit 0 assign z0 = zeros[0]? {z1[45:0], 1'b0} : z1; reg [46:0] frac0; // temporary fraction reg [9:0] exp0; // temporary exponent always @ * begin if (z[47]) begin // 1x.xxxxxxxxxxxxxxxxxxxxxxxx... exp0 = exp10 + 10'h1; frac0 = z[47:1]; // 1.xxxxxxxxxxxxxxxxxxxxxxxx... end else begin if (!exp10[9] && (exp10[8:0] > zeros) && z0[46]) begin exp0 = exp10 - zeros; frac0 = z0; // 1.xxxxxxxxxxxxxxxxxxxxxxxx... end else begin // is a denormalized number or 0 exp0 = 0; if (!exp10[9] && (exp10 != 0)) // e > 0 frac0 = z[46:0] << (exp10 - 10'h1); // e-127 -> -126 else frac0 = z[46:0] >> (10'h1 - exp10); // e = 0 or neg end end end wire [26:0] frac = {frac0[46:21],|frac0[20:0]}; // x.xx...xx grs wire frac_plus_1 = // for rounding ~rm[1] & ~rm[0] & frac0[2] & (frac0[1] | frac0[0]) | ~rm[1] & ~rm[0] & frac0[2] & ~frac0[1] & ~frac0[0] & frac0[3] | ~rm[1] & rm[0] & (frac0[2] | frac0[1] | frac0[0]) & sign | rm[1] & ~rm[0] & (frac0[2] | frac0[1] | frac0[0]) & ~sign; wire [24:0] frac_round = {1'b0,frac[26:3]} + frac_plus_1; wire [9:0] exp1 = frac_round[24]? exp0 + 10'h1 : exp0; wire overflow = (exp0 >= 10'h0ff) | (exp1 >= 10'h0ff); assign s = final_result(overflow, rm, sign, s_is_inf, s_is_nan, exp1[7:0], frac_round[22:0], inf_nan_frac); function [31:0] final_result; input overflow; input [1:0] rm; input sign, s_is_inf, s_is_nan; input [7:0] exponent; input [22:0] fraction, inf_nan_frac; casex ({overflow, rm, sign, s_is_nan, s_is_inf}) 6'b1_00_x_0_x : final_result = {sign,8'hff,23'h000000}; // inf 6'b1_01_0_0_x : final_result = {sign,8'hfe,23'h7fffff}; // max 6'b1_01_1_0_x : final_result = {sign,8'hff,23'h000000}; // inf 6'b1_10_0_0_x : final_result = {sign,8'hff,23'h000000}; // inf 6'b1_10_1_0_x : final_result = {sign,8'hfe,23'h7fffff}; // max 6'b1_11_x_0_x : final_result = {sign,8'hfe,23'h7fffff}; // max 6'b0_xx_x_0_0 : final_result = {sign,exponent,fraction}; // nor 6'bx_xx_x_1_x : final_result = {1'b1,8'hff,inf_nan_frac}; // nan 6'bx_xx_x_0_1 : final_result = {sign,8'hff,inf_nan_frac}; // inf default : final_result = {sign,8'h00,23'h000000}; // 0 endcase endfunction endmodule
source_codes/v/fmul_add.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module fmul_add (z_sum,z_carry,z); // fmul add input [39:0] z_sum; input [39:0] z_carry; output [47:8] z; assign z = z_sum + z_carry; endmodule
source_codes/v/fmul_mul.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module fmul_mul (a,b,sign,exp10,s_is_nan,s_is_inf,inf_nan_frac,z_sum, z_carry,z8); // mul stage input [31:0] a, b; output [39:0] z_sum; output [39:0] z_carry; output [22:0] inf_nan_frac; output [9:0] exp10; output [7:0] z8; output sign; output s_is_nan; output s_is_inf; wire a_expo_is_00 = ~|a[30:23]; // exp = 00 wire b_expo_is_00 = ~|b[30:23]; wire a_expo_is_ff = &a[30:23]; // exp = ff wire b_expo_is_ff = &b[30:23]; wire a_frac_is_00 = ~|a[22:0]; // frac = 0 wire b_frac_is_00 = ~|b[22:0]; wire a_is_inf = a_expo_is_ff & a_frac_is_00; wire b_is_inf = b_expo_is_ff & b_frac_is_00; wire a_is_nan = a_expo_is_ff & ~a_frac_is_00; wire b_is_nan = b_expo_is_ff & ~b_frac_is_00; wire a_is_0 = a_expo_is_00 & a_frac_is_00; wire b_is_0 = b_expo_is_00 & b_frac_is_00; assign s_is_inf = a_is_inf | b_is_inf; assign s_is_nan = a_is_nan | (a_is_inf & b_is_0) | b_is_nan | (b_is_inf & a_is_0); wire [22:0] nan_frac = (a[21:0] > b[21:0])? {1'b1,a[21:0]} : {1'b1,b[21:0]}; assign inf_nan_frac = s_is_nan? nan_frac : 23'h0; assign sign = a[31] ^ b[31]; assign exp10 = {2'h0,a[30:23]} + {2'h0,b[30:23]} - 10'h7f + a_expo_is_00 + b_expo_is_00; // -126 wire [23:0] a_frac24 = {~a_expo_is_00,a[22:0]}; wire [23:0] b_frac24 = {~b_expo_is_00,b[22:0]}; wallace_24x24 wt24 (a_frac24,b_frac24,z_sum,z_carry,z8); endmodule
source_codes/v/fmul_norm.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module fmul_norm (rm,sign,exp10,is_nan,is_inf,inf_nan_frac,z,s);// fmul norm input [47:0] z; // xx.xxxxxxxxxxxxxxxxxxxxxxxxxx... input [22:0] inf_nan_frac; input [9:0] exp10; input [1:0] rm; input sign; input is_nan; input is_inf; output [31:0] s; wire [46:0] z5,z4,z3,z2,z1,z0; // x.xxxxxxxxxxxxxxxxxxxxxxxxxx... wire [5:0] zeros; assign zeros[5] = ~|z[46:15]; // 32-bit 0 assign z5 = zeros[5]? {z[14:0],32'b0} : z[46:0]; assign zeros[4] = ~|z5[46:31]; // 16-bit 0 assign z4 = zeros[4]? {z5[30:0],16'b0} : z5; assign zeros[3] = ~|z4[46:39]; // 8-bit 0 assign z3 = zeros[3]? {z4[38:0], 8'b0} : z4; assign zeros[2] = ~|z3[46:43]; // 4-bit 0 assign z2 = zeros[2]? {z3[42:0], 4'b0} : z3; assign zeros[1] = ~|z2[46:45]; // 2-bit 0 assign z1 = zeros[1]? {z2[44:0], 2'b0} : z2; assign zeros[0] = ~z1[46]; // 1-bit 0 assign z0 = zeros[0]? {z1[45:0], 1'b0} : z1; reg [46:0] frac0; // temporary fraction reg [9:0] exp0; // temporary exponent always @ * begin if (z[47]) begin // 1x.xxxxxxxxxxxxxxxxxxxxxxxx... exp0 = exp10 + 10'h1; frac0 = z[47:1]; // 1.xxxxxxxxxxxxxxxxxxxxxxxx... end else begin if (!exp10[9] && (exp10[8:0] > zeros) && z0[46]) begin exp0 = exp10 - zeros; frac0 = z0; // 1.xxxxxxxxxxxxxxxxxxxxxxxx... end else begin // is a denormalized number or 0 exp0 = 0; if (!exp10[9] && (exp10 != 0)) // e > 0 frac0 = z[46:0] << (exp10 - 10'h1); // e-127 -> -126 else frac0 = z[46:0] >> (10'h1 - exp10); // e = 0 or neg end end end wire [26:0] frac = {frac0[46:21],|frac0[20:0]}; // x.xx...xx grs wire frac_plus_1 = // for rounding ~rm[1] & ~rm[0] & frac0[2] & (frac0[1] | frac0[0]) | ~rm[1] & ~rm[0] & frac0[2] & ~frac0[1] & ~frac0[0] & frac0[3] | ~rm[1] & rm[0] & (frac0[2] | frac0[1] | frac0[0]) & sign | rm[1] & ~rm[0] & (frac0[2] | frac0[1] | frac0[0]) & ~sign; wire [24:0] frac_round = {1'b0,frac[26:3]} + frac_plus_1; wire [9:0] exp1 = frac_round[24]? exp0 + 10'h1 : exp0; wire overflow = (exp0 >= 10'h0ff) | (exp1 >= 10'h0ff); assign s = final_result(overflow, rm, sign, is_nan, is_inf, exp1[7:0], frac_round[22:0], inf_nan_frac); function [31:0] final_result; input overflow; input [1:0] rm; input sign, is_nan, is_inf; input [7:0] exponent; input [22:0] fraction,inf_nan_frac; casex ({overflow,rm,sign,is_nan,is_inf}) 6'b1_00_x_0_x : final_result = {sign,8'hff,23'h000000}; // inf 6'b1_01_0_0_x : final_result = {sign,8'hfe,23'h7fffff}; // max 6'b1_01_1_0_x : final_result = {sign,8'hff,23'h000000}; // inf 6'b1_10_0_0_x : final_result = {sign,8'hff,23'h000000}; // inf 6'b1_10_1_0_x : final_result = {sign,8'hfe,23'h7fffff}; // max 6'b1_11_x_0_x : final_result = {sign,8'hfe,23'h7fffff}; // max 6'b0_xx_x_0_0 : final_result = {sign,exponent,fraction}; // nor 6'bx_xx_x_1_x : final_result = {1'b1,8'hff,inf_nan_frac}; // nan 6'bx_xx_x_0_1 : final_result = {sign,8'hff,inf_nan_frac}; // inf default : final_result = {sign,8'h00,23'h000000}; // 0 endcase endfunction endmodule
source_codes/v/fmul_tb.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ `timescale 1ns/1ns module fmul_tb; reg [31:0] a, b; reg [1:0] rm; wire [31:0] s; fmul fm (a,b,rm,s); initial begin rm = 0; a = 32'h3fc00000; b = 32'h3fc00000; #10 a = 32'h00800000; b = 32'h00800000; #10 a = 32'h7f7fffff; b = 32'h7f7fffff; #10 a = 32'h00800000; b = 32'h3f000000; #10 a = 32'h003fffff; b = 32'h40000000; #10 a = 32'h7f800000; b = 32'h00ffffff; #10 a = 32'h7f800000; b = 32'h00000000; #10 a = 32'h7ff000ff; b = 32'h3f80ff00; end endmodule
source_codes/v/font_table.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module font_table (a,d); input [12:0] a; // 8*8*128=2^3*2^3*2^7 output d; // font dot wire rom [0:8191]; assign d = rom[a]; assign rom[13'h0000] = 0; assign rom[13'h0001] = 0; assign rom[13'h0002] = 0; assign rom[13'h0003] = 0; assign rom[13'h0004] = 0; assign rom[13'h0005] = 0; assign rom[13'h0006] = 0; assign rom[13'h0007] = 0; assign rom[13'h0008] = 0; assign rom[13'h0009] = 0; assign rom[13'h000a] = 0; assign rom[13'h000b] = 0; assign rom[13'h000c] = 0; assign rom[13'h000d] = 0; assign rom[13'h000e] = 0; assign rom[13'h000f] = 0; assign rom[13'h0010] = 0; assign rom[13'h0011] = 0; assign rom[13'h0012] = 0; assign rom[13'h0013] = 0; assign rom[13'h0014] = 0; assign rom[13'h0015] = 0; assign rom[13'h0016] = 0; assign rom[13'h0017] = 0; assign rom[13'h0018] = 0; assign rom[13'h0019] = 0; assign rom[13'h001a] = 0; assign rom[13'h001b] = 0; assign rom[13'h001c] = 0; assign rom[13'h001d] = 0; assign rom[13'h001e] = 0; assign rom[13'h001f] = 0; assign rom[13'h0020] = 0; assign rom[13'h0021] = 0; assign rom[13'h0022] = 0; assign rom[13'h0023] = 0; assign rom[13'h0024] = 0; assign rom[13'h0025] = 0; assign rom[13'h0026] = 0; assign rom[13'h0027] = 0; assign rom[13'h0028] = 0; assign rom[13'h0029] = 0; assign rom[13'h002a] = 0; assign rom[13'h002b] = 0; assign rom[13'h002c] = 0; assign rom[13'h002d] = 0; assign rom[13'h002e] = 0; assign rom[13'h002f] = 0; assign rom[13'h0030] = 0; assign rom[13'h0031] = 0; assign rom[13'h0032] = 0; assign rom[13'h0033] = 0; assign rom[13'h0034] = 0; assign rom[13'h0035] = 0; assign rom[13'h0036] = 0; assign rom[13'h0037] = 0; assign rom[13'h0038] = 0; assign rom[13'h0039] = 0; assign rom[13'h003a] = 0; assign rom[13'h003b] = 0; assign rom[13'h003c] = 0; assign rom[13'h003d] = 0; assign rom[13'h003e] = 0; assign rom[13'h003f] = 0; assign rom[13'h0040] = 0; assign rom[13'h0041] = 0; assign rom[13'h0042] = 0; assign rom[13'h0043] = 0; assign rom[13'h0044] = 0; assign rom[13'h0045] = 0; assign rom[13'h0046] = 0; assign rom[13'h0047] = 0; assign rom[13'h0048] = 0; assign rom[13'h0049] = 0; assign rom[13'h004a] = 0; assign rom[13'h004b] = 0; assign rom[13'h004c] = 0; assign rom[13'h004d] = 0; assign rom[13'h004e] = 0; assign rom[13'h004f] = 0; assign rom[13'h0050] = 0; assign rom[13'h0051] = 0; assign rom[13'h0052] = 0; assign rom[13'h0053] = 0; assign rom[13'h0054] = 0; assign rom[13'h0055] = 0; assign rom[13'h0056] = 0; assign rom[13'h0057] = 0; assign rom[13'h0058] = 0; assign rom[13'h0059] = 0; assign rom[13'h005a] = 0; assign rom[13'h005b] = 0; assign rom[13'h005c] = 0; assign rom[13'h005d] = 0; assign rom[13'h005e] = 0; assign rom[13'h005f] = 0; assign rom[13'h0060] = 0; assign rom[13'h0061] = 0; assign rom[13'h0062] = 0; assign rom[13'h0063] = 0; assign rom[13'h0064] = 0; assign rom[13'h0065] = 0; assign rom[13'h0066] = 0; assign rom[13'h0067] = 0; assign rom[13'h0068] = 0; assign rom[13'h0069] = 0; assign rom[13'h006a] = 0; assign rom[13'h006b] = 0; assign rom[13'h006c] = 0; assign rom[13'h006d] = 0; assign rom[13'h006e] = 0; assign rom[13'h006f] = 0; assign rom[13'h0070] = 0; assign rom[13'h0071] = 0; assign rom[13'h0072] = 0; assign rom[13'h0073] = 0; assign rom[13'h0074] = 0; assign rom[13'h0075] = 0; assign rom[13'h0076] = 0; assign rom[13'h0077] = 0; assign rom[13'h0078] = 0; assign rom[13'h0079] = 0; assign rom[13'h007a] = 0; assign rom[13'h007b] = 0; assign rom[13'h007c] = 0; assign rom[13'h007d] = 0; assign rom[13'h007e] = 0; assign rom[13'h007f] = 0; assign rom[13'h0080] = 0; assign rom[13'h0081] = 0; assign rom[13'h0082] = 0; assign rom[13'h0083] = 0; assign rom[13'h0084] = 0; assign rom[13'h0085] = 0; assign rom[13'h0086] = 0; assign rom[13'h0087] = 0; assign rom[13'h0088] = 0; assign rom[13'h0089] = 0; assign rom[13'h008a] = 0; assign rom[13'h008b] = 0; assign rom[13'h008c] = 0; assign rom[13'h008d] = 0; assign rom[13'h008e] = 0; assign rom[13'h008f] = 0; assign rom[13'h0090] = 0; assign rom[13'h0091] = 0; assign rom[13'h0092] = 0; assign rom[13'h0093] = 0; assign rom[13'h0094] = 0; assign rom[13'h0095] = 0; assign rom[13'h0096] = 0; assign rom[13'h0097] = 0; assign rom[13'h0098] = 0; assign rom[13'h0099] = 0; assign rom[13'h009a] = 0; assign rom[13'h009b] = 0; assign rom[13'h009c] = 0; assign rom[13'h009d] = 0; assign rom[13'h009e] = 0; assign rom[13'h009f] = 0; assign rom[13'h00a0] = 0; assign rom[13'h00a1] = 0; assign rom[13'h00a2] = 0; assign rom[13'h00a3] = 0; assign rom[13'h00a4] = 0; assign rom[13'h00a5] = 0; assign rom[13'h00a6] = 0; assign rom[13'h00a7] = 0; assign rom[13'h00a8] = 0; assign rom[13'h00a9] = 0; assign rom[13'h00aa] = 0; assign rom[13'h00ab] = 0; assign rom[13'h00ac] = 0; assign rom[13'h00ad] = 0; assign rom[13'h00ae] = 0; assign rom[13'h00af] = 0; assign rom[13'h00b0] = 0; assign rom[13'h00b1] = 0; assign rom[13'h00b2] = 0; assign rom[13'h00b3] = 0; assign rom[13'h00b4] = 0; assign rom[13'h00b5] = 0; assign rom[13'h00b6] = 0; assign rom[13'h00b7] = 0; assign rom[13'h00b8] = 0; assign rom[13'h00b9] = 0; assign rom[13'h00ba] = 0; assign rom[13'h00bb] = 0; assign rom[13'h00bc] = 0; assign rom[13'h00bd] = 0; assign rom[13'h00be] = 0; assign rom[13'h00bf] = 0; assign rom[13'h00c0] = 0; assign rom[13'h00c1] = 0; assign rom[13'h00c2] = 0; assign rom[13'h00c3] = 0; assign rom[13'h00c4] = 0; assign rom[13'h00c5] = 0; assign rom[13'h00c6] = 0; assign rom[13'h00c7] = 0; assign rom[13'h00c8] = 0; assign rom[13'h00c9] = 0; assign rom[13'h00ca] = 0; assign rom[13'h00cb] = 0; assign rom[13'h00cc] = 0; assign rom[13'h00cd] = 0; assign rom[13'h00ce] = 0; assign rom[13'h00cf] = 0; assign rom[13'h00d0] = 0; assign rom[13'h00d1] = 0; assign rom[13'h00d2] = 0; assign rom[13'h00d3] = 0; assign rom[13'h00d4] = 0; assign rom[13'h00d5] = 0; assign rom[13'h00d6] = 0; assign rom[13'h00d7] = 0; assign rom[13'h00d8] = 0; assign rom[13'h00d9] = 0; assign rom[13'h00da] = 0; assign rom[13'h00db] = 0; assign rom[13'h00dc] = 0; assign rom[13'h00dd] = 0; assign rom[13'h00de] = 0; assign rom[13'h00df] = 0; assign rom[13'h00e0] = 0; assign rom[13'h00e1] = 0; assign rom[13'h00e2] = 0; assign rom[13'h00e3] = 0; assign rom[13'h00e4] = 0; assign rom[13'h00e5] = 0; assign rom[13'h00e6] = 0; assign rom[13'h00e7] = 0; assign rom[13'h00e8] = 0; assign rom[13'h00e9] = 0; assign rom[13'h00ea] = 0; assign rom[13'h00eb] = 0; assign rom[13'h00ec] = 0; assign rom[13'h00ed] = 0; assign rom[13'h00ee] = 0; assign rom[13'h00ef] = 0; assign rom[13'h00f0] = 0; assign rom[13'h00f1] = 0; assign rom[13'h00f2] = 0; assign rom[13'h00f3] = 0; assign rom[13'h00f4] = 0; assign rom[13'h00f5] = 0; assign rom[13'h00f6] = 0; assign rom[13'h00f7] = 0; assign rom[13'h00f8] = 0; assign rom[13'h00f9] = 0; assign rom[13'h00fa] = 0; assign rom[13'h00fb] = 0; assign rom[13'h00fc] = 0; assign rom[13'h00fd] = 0; assign rom[13'h00fe] = 0; assign rom[13'h00ff] = 0; assign rom[13'h0100] = 0; assign rom[13'h0101] = 0; assign rom[13'h0102] = 0; assign rom[13'h0103] = 0; assign rom[13'h0104] = 0; assign rom[13'h0105] = 0; assign rom[13'h0106] = 0; assign rom[13'h0107] = 0; assign rom[13'h0108] = 0; assign rom[13'h0109] = 0; assign rom[13'h010a] = 0; assign rom[13'h010b] = 0; assign rom[13'h010c] = 0; assign rom[13'h010d] = 0; assign rom[13'h010e] = 0; assign rom[13'h010f] = 0; assign rom[13'h0110] = 0; assign rom[13'h0111] = 0; assign rom[13'h0112] = 0; assign rom[13'h0113] = 0; assign rom[13'h0114] = 0; assign rom[13'h0115] = 0; assign rom[13'h0116] = 0; assign rom[13'h0117] = 0; assign rom[13'h0118] = 0; assign rom[13'h0119] = 0; assign rom[13'h011a] = 0; assign rom[13'h011b] = 0; assign rom[13'h011c] = 0; assign rom[13'h011d] = 0; assign rom[13'h011e] = 0; assign rom[13'h011f] = 0; assign rom[13'h0120] = 0; assign rom[13'h0121] = 0; assign rom[13'h0122] = 0; assign rom[13'h0123] = 0; assign rom[13'h0124] = 0; assign rom[13'h0125] = 0; assign rom[13'h0126] = 0; assign rom[13'h0127] = 0; assign rom[13'h0128] = 0; assign rom[13'h0129] = 0; assign rom[13'h012a] = 0; assign rom[13'h012b] = 0; assign rom[13'h012c] = 0; assign rom[13'h012d] = 0; assign rom[13'h012e] = 0; assign rom[13'h012f] = 0; assign rom[13'h0130] = 0; assign rom[13'h0131] = 0; assign rom[13'h0132] = 0; assign rom[13'h0133] = 0; assign rom[13'h0134] = 0; assign rom[13'h0135] = 0; assign rom[13'h0136] = 0; assign rom[13'h0137] = 0; assign rom[13'h0138] = 0; assign rom[13'h0139] = 0; assign rom[13'h013a] = 0; assign rom[13'h013b] = 0; assign rom[13'h013c] = 0; assign rom[13'h013d] = 0; assign rom[13'h013e] = 0; assign rom[13'h013f] = 0; assign rom[13'h0140] = 0; assign rom[13'h0141] = 0; assign rom[13'h0142] = 0; assign rom[13'h0143] = 0; assign rom[13'h0144] = 0; assign rom[13'h0145] = 0; assign rom[13'h0146] = 0; assign rom[13'h0147] = 0; assign rom[13'h0148] = 0; assign rom[13'h0149] = 0; assign rom[13'h014a] = 0; assign rom[13'h014b] = 0; assign rom[13'h014c] = 0; assign rom[13'h014d] = 0; assign rom[13'h014e] = 0; assign rom[13'h014f] = 0; assign rom[13'h0150] = 0; assign rom[13'h0151] = 0; assign rom[13'h0152] = 0; assign rom[13'h0153] = 0; assign rom[13'h0154] = 0; assign rom[13'h0155] = 0; assign rom[13'h0156] = 0; assign rom[13'h0157] = 0; assign rom[13'h0158] = 0; assign rom[13'h0159] = 0; assign rom[13'h015a] = 0; assign rom[13'h015b] = 0; assign rom[13'h015c] = 0; assign rom[13'h015d] = 0; assign rom[13'h015e] = 0; assign rom[13'h015f] = 0; assign rom[13'h0160] = 0; assign rom[13'h0161] = 0; assign rom[13'h0162] = 0; assign rom[13'h0163] = 0; assign rom[13'h0164] = 0; assign rom[13'h0165] = 0; assign rom[13'h0166] = 0; assign rom[13'h0167] = 0; assign rom[13'h0168] = 0; assign rom[13'h0169] = 0; assign rom[13'h016a] = 0; assign rom[13'h016b] = 0; assign rom[13'h016c] = 0; assign rom[13'h016d] = 0; assign rom[13'h016e] = 0; assign rom[13'h016f] = 0; assign rom[13'h0170] = 0; assign rom[13'h0171] = 0; assign rom[13'h0172] = 0; assign rom[13'h0173] = 0; assign rom[13'h0174] = 0; assign rom[13'h0175] = 0; assign rom[13'h0176] = 0; assign rom[13'h0177] = 0; assign rom[13'h0178] = 0; assign rom[13'h0179] = 0; assign rom[13'h017a] = 0; assign rom[13'h017b] = 0; assign rom[13'h017c] = 0; assign rom[13'h017d] = 0; assign rom[13'h017e] = 0; assign rom[13'h017f] = 0; assign rom[13'h0180] = 0; assign rom[13'h0181] = 0; assign rom[13'h0182] = 0; assign rom[13'h0183] = 0; assign rom[13'h0184] = 0; assign rom[13'h0185] = 0; assign rom[13'h0186] = 0; assign rom[13'h0187] = 0; assign rom[13'h0188] = 0; assign rom[13'h0189] = 0; assign rom[13'h018a] = 0; assign rom[13'h018b] = 0; assign rom[13'h018c] = 0; assign rom[13'h018d] = 0; assign rom[13'h018e] = 0; assign rom[13'h018f] = 0; assign rom[13'h0190] = 0; assign rom[13'h0191] = 0; assign rom[13'h0192] = 0; assign rom[13'h0193] = 0; assign rom[13'h0194] = 0; assign rom[13'h0195] = 0; assign rom[13'h0196] = 0; assign rom[13'h0197] = 0; assign rom[13'h0198] = 0; assign rom[13'h0199] = 0; assign rom[13'h019a] = 0; assign rom[13'h019b] = 0; assign rom[13'h019c] = 0; assign rom[13'h019d] = 0; assign rom[13'h019e] = 0; assign rom[13'h019f] = 0; assign rom[13'h01a0] = 0; assign rom[13'h01a1] = 0; assign rom[13'h01a2] = 0; assign rom[13'h01a3] = 0; assign rom[13'h01a4] = 0; assign rom[13'h01a5] = 0; assign rom[13'h01a6] = 0; assign rom[13'h01a7] = 0; assign rom[13'h01a8] = 0; assign rom[13'h01a9] = 0; assign rom[13'h01aa] = 0; assign rom[13'h01ab] = 0; assign rom[13'h01ac] = 0; assign rom[13'h01ad] = 0; assign rom[13'h01ae] = 0; assign rom[13'h01af] = 0; assign rom[13'h01b0] = 0; assign rom[13'h01b1] = 0; assign rom[13'h01b2] = 0; assign rom[13'h01b3] = 0; assign rom[13'h01b4] = 0; assign rom[13'h01b5] = 0; assign rom[13'h01b6] = 0; assign rom[13'h01b7] = 0; assign rom[13'h01b8] = 0; assign rom[13'h01b9] = 0; assign rom[13'h01ba] = 0; assign rom[13'h01bb] = 0; assign rom[13'h01bc] = 0; assign rom[13'h01bd] = 0; assign rom[13'h01be] = 0; assign rom[13'h01bf] = 0; assign rom[13'h01c0] = 0; assign rom[13'h01c1] = 0; assign rom[13'h01c2] = 0; assign rom[13'h01c3] = 0; assign rom[13'h01c4] = 0; assign rom[13'h01c5] = 0; assign rom[13'h01c6] = 0; assign rom[13'h01c7] = 0; assign rom[13'h01c8] = 0; assign rom[13'h01c9] = 0; assign rom[13'h01ca] = 0; assign rom[13'h01cb] = 0; assign rom[13'h01cc] = 0; assign rom[13'h01cd] = 0; assign rom[13'h01ce] = 0; assign rom[13'h01cf] = 0; assign rom[13'h01d0] = 0; assign rom[13'h01d1] = 0; assign rom[13'h01d2] = 0; assign rom[13'h01d3] = 0; assign rom[13'h01d4] = 0; assign rom[13'h01d5] = 0; assign rom[13'h01d6] = 0; assign rom[13'h01d7] = 0; assign rom[13'h01d8] = 0; assign rom[13'h01d9] = 0; assign rom[13'h01da] = 0; assign rom[13'h01db] = 0; assign rom[13'h01dc] = 0; assign rom[13'h01dd] = 0; assign rom[13'h01de] = 0; assign rom[13'h01df] = 0; assign rom[13'h01e0] = 0; assign rom[13'h01e1] = 0; assign rom[13'h01e2] = 0; assign rom[13'h01e3] = 0; assign rom[13'h01e4] = 0; assign rom[13'h01e5] = 0; assign rom[13'h01e6] = 0; assign rom[13'h01e7] = 0; assign rom[13'h01e8] = 0; assign rom[13'h01e9] = 0; assign rom[13'h01ea] = 0; assign rom[13'h01eb] = 0; assign rom[13'h01ec] = 0; assign rom[13'h01ed] = 0; assign rom[13'h01ee] = 0; assign rom[13'h01ef] = 0; assign rom[13'h01f0] = 0; assign rom[13'h01f1] = 0; assign rom[13'h01f2] = 0; assign rom[13'h01f3] = 0; assign rom[13'h01f4] = 0; assign rom[13'h01f5] = 0; assign rom[13'h01f6] = 0; assign rom[13'h01f7] = 0; assign rom[13'h01f8] = 0; assign rom[13'h01f9] = 0; assign rom[13'h01fa] = 0; assign rom[13'h01fb] = 0; assign rom[13'h01fc] = 0; assign rom[13'h01fd] = 0; assign rom[13'h01fe] = 0; assign rom[13'h01ff] = 0; assign rom[13'h0200] = 0; assign rom[13'h0201] = 0; assign rom[13'h0202] = 0; assign rom[13'h0203] = 0; assign rom[13'h0204] = 0; assign rom[13'h0205] = 0; assign rom[13'h0206] = 0; assign rom[13'h0207] = 0; assign rom[13'h0208] = 0; assign rom[13'h0209] = 0; assign rom[13'h020a] = 0; assign rom[13'h020b] = 0; assign rom[13'h020c] = 0; assign rom[13'h020d] = 0; assign rom[13'h020e] = 0; assign rom[13'h020f] = 0; assign rom[13'h0210] = 0; assign rom[13'h0211] = 0; assign rom[13'h0212] = 0; assign rom[13'h0213] = 0; assign rom[13'h0214] = 0; assign rom[13'h0215] = 0; assign rom[13'h0216] = 0; assign rom[13'h0217] = 0; assign rom[13'h0218] = 0; assign rom[13'h0219] = 0; assign rom[13'h021a] = 0; assign rom[13'h021b] = 0; assign rom[13'h021c] = 0; assign rom[13'h021d] = 0; assign rom[13'h021e] = 0; assign rom[13'h021f] = 0; assign rom[13'h0220] = 0; assign rom[13'h0221] = 0; assign rom[13'h0222] = 0; assign rom[13'h0223] = 0; assign rom[13'h0224] = 0; assign rom[13'h0225] = 0; assign rom[13'h0226] = 0; assign rom[13'h0227] = 0; assign rom[13'h0228] = 0; assign rom[13'h0229] = 0; assign rom[13'h022a] = 0; assign rom[13'h022b] = 0; assign rom[13'h022c] = 0; assign rom[13'h022d] = 0; assign rom[13'h022e] = 0; assign rom[13'h022f] = 0; assign rom[13'h0230] = 0; assign rom[13'h0231] = 0; assign rom[13'h0232] = 0; assign rom[13'h0233] = 0; assign rom[13'h0234] = 0; assign rom[13'h0235] = 0; assign rom[13'h0236] = 0; assign rom[13'h0237] = 0; assign rom[13'h0238] = 0; assign rom[13'h0239] = 0; assign rom[13'h023a] = 0; assign rom[13'h023b] = 0; assign rom[13'h023c] = 0; assign rom[13'h023d] = 0; assign rom[13'h023e] = 0; assign rom[13'h023f] = 0; assign rom[13'h0240] = 0; assign rom[13'h0241] = 0; assign rom[13'h0242] = 0; assign rom[13'h0243] = 0; assign rom[13'h0244] = 0; assign rom[13'h0245] = 0; assign rom[13'h0246] = 0; assign rom[13'h0247] = 0; assign rom[13'h0248] = 0; assign rom[13'h0249] = 0; assign rom[13'h024a] = 0; assign rom[13'h024b] = 0; assign rom[13'h024c] = 0; assign rom[13'h024d] = 0; assign rom[13'h024e] = 0; assign rom[13'h024f] = 0; assign rom[13'h0250] = 0; assign rom[13'h0251] = 0; assign rom[13'h0252] = 0; assign rom[13'h0253] = 0; assign rom[13'h0254] = 0; assign rom[13'h0255] = 0; assign rom[13'h0256] = 0; assign rom[13'h0257] = 0; assign rom[13'h0258] = 0; assign rom[13'h0259] = 0; assign rom[13'h025a] = 0; assign rom[13'h025b] = 0; assign rom[13'h025c] = 0; assign rom[13'h025d] = 0; assign rom[13'h025e] = 0; assign rom[13'h025f] = 0; assign rom[13'h0260] = 0; assign rom[13'h0261] = 0; assign rom[13'h0262] = 0; assign rom[13'h0263] = 0; assign rom[13'h0264] = 0; assign rom[13'h0265] = 0; assign rom[13'h0266] = 0; assign rom[13'h0267] = 0; assign rom[13'h0268] = 0; assign rom[13'h0269] = 0; assign rom[13'h026a] = 0; assign rom[13'h026b] = 0; assign rom[13'h026c] = 0; assign rom[13'h026d] = 0; assign rom[13'h026e] = 0; assign rom[13'h026f] = 0; assign rom[13'h0270] = 0; assign rom[13'h0271] = 0; assign rom[13'h0272] = 0; assign rom[13'h0273] = 0; assign rom[13'h0274] = 0; assign rom[13'h0275] = 0; assign rom[13'h0276] = 0; assign rom[13'h0277] = 0; assign rom[13'h0278] = 0; assign rom[13'h0279] = 0; assign rom[13'h027a] = 0; assign rom[13'h027b] = 0; assign rom[13'h027c] = 0; assign rom[13'h027d] = 0; assign rom[13'h027e] = 0; assign rom[13'h027f] = 0; assign rom[13'h0280] = 0; assign rom[13'h0281] = 0; assign rom[13'h0282] = 0; assign rom[13'h0283] = 0; assign rom[13'h0284] = 0; assign rom[13'h0285] = 0; assign rom[13'h0286] = 0; assign rom[13'h0287] = 0; assign rom[13'h0288] = 0; assign rom[13'h0289] = 0; assign rom[13'h028a] = 0; assign rom[13'h028b] = 0; assign rom[13'h028c] = 0; assign rom[13'h028d] = 0; assign rom[13'h028e] = 0; assign rom[13'h028f] = 0; assign rom[13'h0290] = 0; assign rom[13'h0291] = 0; assign rom[13'h0292] = 0; assign rom[13'h0293] = 0; assign rom[13'h0294] = 0; assign rom[13'h0295] = 0; assign rom[13'h0296] = 0; assign rom[13'h0297] = 0; assign rom[13'h0298] = 0; assign rom[13'h0299] = 0; assign rom[13'h029a] = 0; assign rom[13'h029b] = 0; assign rom[13'h029c] = 0; assign rom[13'h029d] = 0; assign rom[13'h029e] = 0; assign rom[13'h029f] = 0; assign rom[13'h02a0] = 0; assign rom[13'h02a1] = 0; assign rom[13'h02a2] = 0; assign rom[13'h02a3] = 0; assign rom[13'h02a4] = 0; assign rom[13'h02a5] = 0; assign rom[13'h02a6] = 0; assign rom[13'h02a7] = 0; assign rom[13'h02a8] = 0; assign rom[13'h02a9] = 0; assign rom[13'h02aa] = 0; assign rom[13'h02ab] = 0; assign rom[13'h02ac] = 0; assign rom[13'h02ad] = 0; assign rom[13'h02ae] = 0; assign rom[13'h02af] = 0; assign rom[13'h02b0] = 0; assign rom[13'h02b1] = 0; assign rom[13'h02b2] = 0; assign rom[13'h02b3] = 0; assign rom[13'h02b4] = 0; assign rom[13'h02b5] = 0; assign rom[13'h02b6] = 0; assign rom[13'h02b7] = 0; assign rom[13'h02b8] = 0; assign rom[13'h02b9] = 0; assign rom[13'h02ba] = 0; assign rom[13'h02bb] = 0; assign rom[13'h02bc] = 0; assign rom[13'h02bd] = 0; assign rom[13'h02be] = 0; assign rom[13'h02bf] = 0; assign rom[13'h02c0] = 0; assign rom[13'h02c1] = 0; assign rom[13'h02c2] = 0; assign rom[13'h02c3] = 0; assign rom[13'h02c4] = 0; assign rom[13'h02c5] = 0; assign rom[13'h02c6] = 0; assign rom[13'h02c7] = 0; assign rom[13'h02c8] = 0; assign rom[13'h02c9] = 0; assign rom[13'h02ca] = 0; assign rom[13'h02cb] = 0; assign rom[13'h02cc] = 0; assign rom[13'h02cd] = 0; assign rom[13'h02ce] = 0; assign rom[13'h02cf] = 0; assign rom[13'h02d0] = 0; assign rom[13'h02d1] = 0; assign rom[13'h02d2] = 0; assign rom[13'h02d3] = 0; assign rom[13'h02d4] = 0; assign rom[13'h02d5] = 0; assign rom[13'h02d6] = 0; assign rom[13'h02d7] = 0; assign rom[13'h02d8] = 0; assign rom[13'h02d9] = 0; assign rom[13'h02da] = 0; assign rom[13'h02db] = 0; assign rom[13'h02dc] = 0; assign rom[13'h02dd] = 0; assign rom[13'h02de] = 0; assign rom[13'h02df] = 0; assign rom[13'h02e0] = 0; assign rom[13'h02e1] = 0; assign rom[13'h02e2] = 0; assign rom[13'h02e3] = 0; assign rom[13'h02e4] = 0; assign rom[13'h02e5] = 0; assign rom[13'h02e6] = 0; assign rom[13'h02e7] = 0; assign rom[13'h02e8] = 0; assign rom[13'h02e9] = 0; assign rom[13'h02ea] = 0; assign rom[13'h02eb] = 0; assign rom[13'h02ec] = 0; assign rom[13'h02ed] = 0; assign rom[13'h02ee] = 0; assign rom[13'h02ef] = 0; assign rom[13'h02f0] = 0; assign rom[13'h02f1] = 0; assign rom[13'h02f2] = 0; assign rom[13'h02f3] = 0; assign rom[13'h02f4] = 0; assign rom[13'h02f5] = 0; assign rom[13'h02f6] = 0; assign rom[13'h02f7] = 0; assign rom[13'h02f8] = 0; assign rom[13'h02f9] = 0; assign rom[13'h02fa] = 0; assign rom[13'h02fb] = 0; assign rom[13'h02fc] = 0; assign rom[13'h02fd] = 0; assign rom[13'h02fe] = 0; assign rom[13'h02ff] = 0; assign rom[13'h0300] = 0; assign rom[13'h0301] = 0; assign rom[13'h0302] = 0; assign rom[13'h0303] = 0; assign rom[13'h0304] = 0; assign rom[13'h0305] = 0; assign rom[13'h0306] = 0; assign rom[13'h0307] = 0; assign rom[13'h0308] = 0; assign rom[13'h0309] = 0; assign rom[13'h030a] = 0; assign rom[13'h030b] = 0; assign rom[13'h030c] = 0; assign rom[13'h030d] = 0; assign rom[13'h030e] = 0; assign rom[13'h030f] = 0; assign rom[13'h0310] = 0; assign rom[13'h0311] = 0; assign rom[13'h0312] = 0; assign rom[13'h0313] = 0; assign rom[13'h0314] = 0; assign rom[13'h0315] = 0; assign rom[13'h0316] = 0; assign rom[13'h0317] = 0; assign rom[13'h0318] = 0; assign rom[13'h0319] = 0; assign rom[13'h031a] = 0; assign rom[13'h031b] = 0; assign rom[13'h031c] = 0; assign rom[13'h031d] = 0; assign rom[13'h031e] = 0; assign rom[13'h031f] = 0; assign rom[13'h0320] = 0; assign rom[13'h0321] = 0; assign rom[13'h0322] = 0; assign rom[13'h0323] = 0; assign rom[13'h0324] = 0; assign rom[13'h0325] = 0; assign rom[13'h0326] = 0; assign rom[13'h0327] = 0; assign rom[13'h0328] = 0; assign rom[13'h0329] = 0; assign rom[13'h032a] = 0; assign rom[13'h032b] = 0; assign rom[13'h032c] = 0; assign rom[13'h032d] = 0; assign rom[13'h032e] = 0; assign rom[13'h032f] = 0; assign rom[13'h0330] = 0; assign rom[13'h0331] = 0; assign rom[13'h0332] = 0; assign rom[13'h0333] = 0; assign rom[13'h0334] = 0; assign rom[13'h0335] = 0; assign rom[13'h0336] = 0; assign rom[13'h0337] = 0; assign rom[13'h0338] = 0; assign rom[13'h0339] = 0; assign rom[13'h033a] = 0; assign rom[13'h033b] = 0; assign rom[13'h033c] = 0; assign rom[13'h033d] = 0; assign rom[13'h033e] = 0; assign rom[13'h033f] = 0; assign rom[13'h0340] = 0; assign rom[13'h0341] = 0; assign rom[13'h0342] = 0; assign rom[13'h0343] = 0; assign rom[13'h0344] = 0; assign rom[13'h0345] = 0; assign rom[13'h0346] = 0; assign rom[13'h0347] = 0; assign rom[13'h0348] = 0; assign rom[13'h0349] = 0; assign rom[13'h034a] = 0; assign rom[13'h034b] = 0; assign rom[13'h034c] = 0; assign rom[13'h034d] = 0; assign rom[13'h034e] = 0; assign rom[13'h034f] = 0; assign rom[13'h0350] = 0; assign rom[13'h0351] = 0; assign rom[13'h0352] = 0; assign rom[13'h0353] = 0; assign rom[13'h0354] = 0; assign rom[13'h0355] = 0; assign rom[13'h0356] = 0; assign rom[13'h0357] = 0; assign rom[13'h0358] = 0; assign rom[13'h0359] = 0; assign rom[13'h035a] = 0; assign rom[13'h035b] = 0; assign rom[13'h035c] = 0; assign rom[13'h035d] = 0; assign rom[13'h035e] = 0; assign rom[13'h035f] = 0; assign rom[13'h0360] = 0; assign rom[13'h0361] = 0; assign rom[13'h0362] = 0; assign rom[13'h0363] = 0; assign rom[13'h0364] = 0; assign rom[13'h0365] = 0; assign rom[13'h0366] = 0; assign rom[13'h0367] = 0; assign rom[13'h0368] = 0; assign rom[13'h0369] = 0; assign rom[13'h036a] = 0; assign rom[13'h036b] = 0; assign rom[13'h036c] = 0; assign rom[13'h036d] = 0; assign rom[13'h036e] = 0; assign rom[13'h036f] = 0; assign rom[13'h0370] = 0; assign rom[13'h0371] = 0; assign rom[13'h0372] = 0; assign rom[13'h0373] = 0; assign rom[13'h0374] = 0; assign rom[13'h0375] = 0; assign rom[13'h0376] = 0; assign rom[13'h0377] = 0; assign rom[13'h0378] = 0; assign rom[13'h0379] = 0; assign rom[13'h037a] = 0; assign rom[13'h037b] = 0; assign rom[13'h037c] = 0; assign rom[13'h037d] = 0; assign rom[13'h037e] = 0; assign rom[13'h037f] = 0; assign rom[13'h0380] = 0; assign rom[13'h0381] = 0; assign rom[13'h0382] = 0; assign rom[13'h0383] = 0; assign rom[13'h0384] = 0; assign rom[13'h0385] = 0; assign rom[13'h0386] = 0; assign rom[13'h0387] = 0; assign rom[13'h0388] = 0; assign rom[13'h0389] = 0; assign rom[13'h038a] = 0; assign rom[13'h038b] = 0; assign rom[13'h038c] = 0; assign rom[13'h038d] = 0; assign rom[13'h038e] = 0; assign rom[13'h038f] = 0; assign rom[13'h0390] = 0; assign rom[13'h0391] = 0; assign rom[13'h0392] = 0; assign rom[13'h0393] = 0; assign rom[13'h0394] = 0; assign rom[13'h0395] = 0; assign rom[13'h0396] = 0; assign rom[13'h0397] = 0; assign rom[13'h0398] = 0; assign rom[13'h0399] = 0; assign rom[13'h039a] = 0; assign rom[13'h039b] = 0; assign rom[13'h039c] = 0; assign rom[13'h039d] = 0; assign rom[13'h039e] = 0; assign rom[13'h039f] = 0; assign rom[13'h03a0] = 0; assign rom[13'h03a1] = 0; assign rom[13'h03a2] = 0; assign rom[13'h03a3] = 0; assign rom[13'h03a4] = 0; assign rom[13'h03a5] = 0; assign rom[13'h03a6] = 0; assign rom[13'h03a7] = 0; assign rom[13'h03a8] = 0; assign rom[13'h03a9] = 0; assign rom[13'h03aa] = 0; assign rom[13'h03ab] = 0; assign rom[13'h03ac] = 0; assign rom[13'h03ad] = 0; assign rom[13'h03ae] = 0; assign rom[13'h03af] = 0; assign rom[13'h03b0] = 0; assign rom[13'h03b1] = 0; assign rom[13'h03b2] = 0; assign rom[13'h03b3] = 0; assign rom[13'h03b4] = 0; assign rom[13'h03b5] = 0; assign rom[13'h03b6] = 0; assign rom[13'h03b7] = 0; assign rom[13'h03b8] = 0; assign rom[13'h03b9] = 0; assign rom[13'h03ba] = 0; assign rom[13'h03bb] = 0; assign rom[13'h03bc] = 0; assign rom[13'h03bd] = 0; assign rom[13'h03be] = 0; assign rom[13'h03bf] = 0; assign rom[13'h03c0] = 0; assign rom[13'h03c1] = 0; assign rom[13'h03c2] = 0; assign rom[13'h03c3] = 0; assign rom[13'h03c4] = 0; assign rom[13'h03c5] = 0; assign rom[13'h03c6] = 0; assign rom[13'h03c7] = 0; assign rom[13'h03c8] = 0; assign rom[13'h03c9] = 0; assign rom[13'h03ca] = 0; assign rom[13'h03cb] = 0; assign rom[13'h03cc] = 0; assign rom[13'h03cd] = 0; assign rom[13'h03ce] = 0; assign rom[13'h03cf] = 0; assign rom[13'h03d0] = 0; assign rom[13'h03d1] = 0; assign rom[13'h03d2] = 0; assign rom[13'h03d3] = 0; assign rom[13'h03d4] = 0; assign rom[13'h03d5] = 0; assign rom[13'h03d6] = 0; assign rom[13'h03d7] = 0; assign rom[13'h03d8] = 0; assign rom[13'h03d9] = 0; assign rom[13'h03da] = 0; assign rom[13'h03db] = 0; assign rom[13'h03dc] = 0; assign rom[13'h03dd] = 0; assign rom[13'h03de] = 0; assign rom[13'h03df] = 0; assign rom[13'h03e0] = 0; assign rom[13'h03e1] = 0; assign rom[13'h03e2] = 0; assign rom[13'h03e3] = 0; assign rom[13'h03e4] = 0; assign rom[13'h03e5] = 0; assign rom[13'h03e6] = 0; assign rom[13'h03e7] = 0; assign rom[13'h03e8] = 0; assign rom[13'h03e9] = 0; assign rom[13'h03ea] = 0; assign rom[13'h03eb] = 0; assign rom[13'h03ec] = 0; assign rom[13'h03ed] = 0; assign rom[13'h03ee] = 0; assign rom[13'h03ef] = 0; assign rom[13'h03f0] = 0; assign rom[13'h03f1] = 0; assign rom[13'h03f2] = 0; assign rom[13'h03f3] = 0; assign rom[13'h03f4] = 0; assign rom[13'h03f5] = 0; assign rom[13'h03f6] = 0; assign rom[13'h03f7] = 0; assign rom[13'h03f8] = 0; assign rom[13'h03f9] = 0; assign rom[13'h03fa] = 0; assign rom[13'h03fb] = 0; assign rom[13'h03fc] = 0; assign rom[13'h03fd] = 0; assign rom[13'h03fe] = 0; assign rom[13'h03ff] = 0; assign rom[13'h0400] = 0; assign rom[13'h0401] = 0; assign rom[13'h0402] = 0; assign rom[13'h0403] = 0; assign rom[13'h0404] = 0; assign rom[13'h0405] = 0; assign rom[13'h0406] = 0; assign rom[13'h0407] = 0; assign rom[13'h0408] = 0; assign rom[13'h0409] = 0; assign rom[13'h040a] = 0; assign rom[13'h040b] = 0; assign rom[13'h040c] = 0; assign rom[13'h040d] = 0; assign rom[13'h040e] = 0; assign rom[13'h040f] = 0; assign rom[13'h0410] = 0; assign rom[13'h0411] = 0; assign rom[13'h0412] = 0; assign rom[13'h0413] = 0; assign rom[13'h0414] = 0; assign rom[13'h0415] = 0; assign rom[13'h0416] = 0; assign rom[13'h0417] = 0; assign rom[13'h0418] = 0; assign rom[13'h0419] = 0; assign rom[13'h041a] = 0; assign rom[13'h041b] = 0; assign rom[13'h041c] = 0; assign rom[13'h041d] = 0; assign rom[13'h041e] = 0; assign rom[13'h041f] = 0; assign rom[13'h0420] = 0; assign rom[13'h0421] = 0; assign rom[13'h0422] = 0; assign rom[13'h0423] = 0; assign rom[13'h0424] = 0; assign rom[13'h0425] = 0; assign rom[13'h0426] = 0; assign rom[13'h0427] = 0; assign rom[13'h0428] = 0; assign rom[13'h0429] = 0; assign rom[13'h042a] = 0; assign rom[13'h042b] = 0; assign rom[13'h042c] = 0; assign rom[13'h042d] = 0; assign rom[13'h042e] = 0; assign rom[13'h042f] = 0; assign rom[13'h0430] = 0; assign rom[13'h0431] = 0; assign rom[13'h0432] = 0; assign rom[13'h0433] = 0; assign rom[13'h0434] = 0; assign rom[13'h0435] = 0; assign rom[13'h0436] = 0; assign rom[13'h0437] = 0; assign rom[13'h0438] = 0; assign rom[13'h0439] = 0; assign rom[13'h043a] = 0; assign rom[13'h043b] = 0; assign rom[13'h043c] = 0; assign rom[13'h043d] = 0; assign rom[13'h043e] = 0; assign rom[13'h043f] = 0; assign rom[13'h0440] = 0; assign rom[13'h0441] = 0; assign rom[13'h0442] = 0; assign rom[13'h0443] = 0; assign rom[13'h0444] = 0; assign rom[13'h0445] = 0; assign rom[13'h0446] = 0; assign rom[13'h0447] = 0; assign rom[13'h0448] = 0; assign rom[13'h0449] = 0; assign rom[13'h044a] = 0; assign rom[13'h044b] = 0; assign rom[13'h044c] = 0; assign rom[13'h044d] = 0; assign rom[13'h044e] = 0; assign rom[13'h044f] = 0; assign rom[13'h0450] = 0; assign rom[13'h0451] = 0; assign rom[13'h0452] = 0; assign rom[13'h0453] = 0; assign rom[13'h0454] = 0; assign rom[13'h0455] = 0; assign rom[13'h0456] = 0; assign rom[13'h0457] = 0; assign rom[13'h0458] = 0; assign rom[13'h0459] = 0; assign rom[13'h045a] = 0; assign rom[13'h045b] = 0; assign rom[13'h045c] = 0; assign rom[13'h045d] = 0; assign rom[13'h045e] = 0; assign rom[13'h045f] = 0; assign rom[13'h0460] = 0; assign rom[13'h0461] = 0; assign rom[13'h0462] = 0; assign rom[13'h0463] = 0; assign rom[13'h0464] = 0; assign rom[13'h0465] = 0; assign rom[13'h0466] = 0; assign rom[13'h0467] = 0; assign rom[13'h0468] = 0; assign rom[13'h0469] = 0; assign rom[13'h046a] = 0; assign rom[13'h046b] = 0; assign rom[13'h046c] = 0; assign rom[13'h046d] = 0; assign rom[13'h046e] = 0; assign rom[13'h046f] = 0; assign rom[13'h0470] = 0; assign rom[13'h0471] = 0; assign rom[13'h0472] = 0; assign rom[13'h0473] = 0; assign rom[13'h0474] = 0; assign rom[13'h0475] = 0; assign rom[13'h0476] = 0; assign rom[13'h0477] = 0; assign rom[13'h0478] = 0; assign rom[13'h0479] = 0; assign rom[13'h047a] = 0; assign rom[13'h047b] = 0; assign rom[13'h047c] = 0; assign rom[13'h047d] = 0; assign rom[13'h047e] = 0; assign rom[13'h047f] = 0; assign rom[13'h0480] = 0; assign rom[13'h0481] = 0; assign rom[13'h0482] = 0; assign rom[13'h0483] = 0; assign rom[13'h0484] = 0; assign rom[13'h0485] = 0; assign rom[13'h0486] = 0; assign rom[13'h0487] = 0; assign rom[13'h0488] = 0; assign rom[13'h0489] = 0; assign rom[13'h048a] = 0; assign rom[13'h048b] = 0; assign rom[13'h048c] = 0; assign rom[13'h048d] = 0; assign rom[13'h048e] = 0; assign rom[13'h048f] = 0; assign rom[13'h0490] = 0; assign rom[13'h0491] = 0; assign rom[13'h0492] = 0; assign rom[13'h0493] = 0; assign rom[13'h0494] = 0; assign rom[13'h0495] = 0; assign rom[13'h0496] = 0; assign rom[13'h0497] = 0; assign rom[13'h0498] = 0; assign rom[13'h0499] = 0; assign rom[13'h049a] = 0; assign rom[13'h049b] = 0; assign rom[13'h049c] = 0; assign rom[13'h049d] = 0; assign rom[13'h049e] = 0; assign rom[13'h049f] = 0; assign rom[13'h04a0] = 0; assign rom[13'h04a1] = 0; assign rom[13'h04a2] = 0; assign rom[13'h04a3] = 0; assign rom[13'h04a4] = 0; assign rom[13'h04a5] = 0; assign rom[13'h04a6] = 0; assign rom[13'h04a7] = 0; assign rom[13'h04a8] = 0; assign rom[13'h04a9] = 0; assign rom[13'h04aa] = 0; assign rom[13'h04ab] = 0; assign rom[13'h04ac] = 0; assign rom[13'h04ad] = 0; assign rom[13'h04ae] = 0; assign rom[13'h04af] = 0; assign rom[13'h04b0] = 0; assign rom[13'h04b1] = 0; assign rom[13'h04b2] = 0; assign rom[13'h04b3] = 0; assign rom[13'h04b4] = 0; assign rom[13'h04b5] = 0; assign rom[13'h04b6] = 0; assign rom[13'h04b7] = 0; assign rom[13'h04b8] = 0; assign rom[13'h04b9] = 0; assign rom[13'h04ba] = 0; assign rom[13'h04bb] = 0; assign rom[13'h04bc] = 0; assign rom[13'h04bd] = 0; assign rom[13'h04be] = 0; assign rom[13'h04bf] = 0; assign rom[13'h04c0] = 0; assign rom[13'h04c1] = 0; assign rom[13'h04c2] = 0; assign rom[13'h04c3] = 0; assign rom[13'h04c4] = 0; assign rom[13'h04c5] = 0; assign rom[13'h04c6] = 0; assign rom[13'h04c7] = 0; assign rom[13'h04c8] = 0; assign rom[13'h04c9] = 0; assign rom[13'h04ca] = 0; assign rom[13'h04cb] = 0; assign rom[13'h04cc] = 0; assign rom[13'h04cd] = 0; assign rom[13'h04ce] = 0; assign rom[13'h04cf] = 0; assign rom[13'h04d0] = 0; assign rom[13'h04d1] = 0; assign rom[13'h04d2] = 0; assign rom[13'h04d3] = 0; assign rom[13'h04d4] = 0; assign rom[13'h04d5] = 0; assign rom[13'h04d6] = 0; assign rom[13'h04d7] = 0; assign rom[13'h04d8] = 0; assign rom[13'h04d9] = 0; assign rom[13'h04da] = 0; assign rom[13'h04db] = 0; assign rom[13'h04dc] = 0; assign rom[13'h04dd] = 0; assign rom[13'h04de] = 0; assign rom[13'h04df] = 0; assign rom[13'h04e0] = 0; assign rom[13'h04e1] = 0; assign rom[13'h04e2] = 0; assign rom[13'h04e3] = 0; assign rom[13'h04e4] = 0; assign rom[13'h04e5] = 0; assign rom[13'h04e6] = 0; assign rom[13'h04e7] = 0; assign rom[13'h04e8] = 0; assign rom[13'h04e9] = 0; assign rom[13'h04ea] = 0; assign rom[13'h04eb] = 0; assign rom[13'h04ec] = 0; assign rom[13'h04ed] = 0; assign rom[13'h04ee] = 0; assign rom[13'h04ef] = 0; assign rom[13'h04f0] = 0; assign rom[13'h04f1] = 0; assign rom[13'h04f2] = 0; assign rom[13'h04f3] = 0; assign rom[13'h04f4] = 0; assign rom[13'h04f5] = 0; assign rom[13'h04f6] = 0; assign rom[13'h04f7] = 0; assign rom[13'h04f8] = 0; assign rom[13'h04f9] = 0; assign rom[13'h04fa] = 0; assign rom[13'h04fb] = 0; assign rom[13'h04fc] = 0; assign rom[13'h04fd] = 0; assign rom[13'h04fe] = 0; assign rom[13'h04ff] = 0; assign rom[13'h0500] = 0; assign rom[13'h0501] = 0; assign rom[13'h0502] = 0; assign rom[13'h0503] = 0; assign rom[13'h0504] = 0; assign rom[13'h0505] = 0; assign rom[13'h0506] = 0; assign rom[13'h0507] = 0; assign rom[13'h0508] = 0; assign rom[13'h0509] = 0; assign rom[13'h050a] = 0; assign rom[13'h050b] = 0; assign rom[13'h050c] = 0; assign rom[13'h050d] = 0; assign rom[13'h050e] = 0; assign rom[13'h050f] = 0; assign rom[13'h0510] = 0; assign rom[13'h0511] = 0; assign rom[13'h0512] = 0; assign rom[13'h0513] = 0; assign rom[13'h0514] = 0; assign rom[13'h0515] = 0; assign rom[13'h0516] = 0; assign rom[13'h0517] = 0; assign rom[13'h0518] = 0; assign rom[13'h0519] = 0; assign rom[13'h051a] = 0; assign rom[13'h051b] = 0; assign rom[13'h051c] = 0; assign rom[13'h051d] = 0; assign rom[13'h051e] = 0; assign rom[13'h051f] = 0; assign rom[13'h0520] = 0; assign rom[13'h0521] = 0; assign rom[13'h0522] = 0; assign rom[13'h0523] = 0; assign rom[13'h0524] = 0; assign rom[13'h0525] = 0; assign rom[13'h0526] = 0; assign rom[13'h0527] = 0; assign rom[13'h0528] = 0; assign rom[13'h0529] = 0; assign rom[13'h052a] = 0; assign rom[13'h052b] = 0; assign rom[13'h052c] = 0; assign rom[13'h052d] = 0; assign rom[13'h052e] = 0; assign rom[13'h052f] = 0; assign rom[13'h0530] = 0; assign rom[13'h0531] = 0; assign rom[13'h0532] = 0; assign rom[13'h0533] = 0; assign rom[13'h0534] = 0; assign rom[13'h0535] = 0; assign rom[13'h0536] = 0; assign rom[13'h0537] = 0; assign rom[13'h0538] = 0; assign rom[13'h0539] = 0; assign rom[13'h053a] = 0; assign rom[13'h053b] = 0; assign rom[13'h053c] = 0; assign rom[13'h053d] = 0; assign rom[13'h053e] = 0; assign rom[13'h053f] = 0; assign rom[13'h0540] = 0; assign rom[13'h0541] = 0; assign rom[13'h0542] = 0; assign rom[13'h0543] = 0; assign rom[13'h0544] = 0; assign rom[13'h0545] = 0; assign rom[13'h0546] = 0; assign rom[13'h0547] = 0; assign rom[13'h0548] = 0; assign rom[13'h0549] = 0; assign rom[13'h054a] = 0; assign rom[13'h054b] = 0; assign rom[13'h054c] = 0; assign rom[13'h054d] = 0; assign rom[13'h054e] = 0; assign rom[13'h054f] = 0; assign rom[13'h0550] = 0; assign rom[13'h0551] = 0; assign rom[13'h0552] = 0; assign rom[13'h0553] = 0; assign rom[13'h0554] = 0; assign rom[13'h0555] = 0; assign rom[13'h0556] = 0; assign rom[13'h0557] = 0; assign rom[13'h0558] = 0; assign rom[13'h0559] = 0; assign rom[13'h055a] = 0; assign rom[13'h055b] = 0; assign rom[13'h055c] = 0; assign rom[13'h055d] = 0; assign rom[13'h055e] = 0; assign rom[13'h055f] = 0; assign rom[13'h0560] = 0; assign rom[13'h0561] = 0; assign rom[13'h0562] = 0; assign rom[13'h0563] = 0; assign rom[13'h0564] = 0; assign rom[13'h0565] = 0; assign rom[13'h0566] = 0; assign rom[13'h0567] = 0; assign rom[13'h0568] = 0; assign rom[13'h0569] = 0; assign rom[13'h056a] = 0; assign rom[13'h056b] = 0; assign rom[13'h056c] = 0; assign rom[13'h056d] = 0; assign rom[13'h056e] = 0; assign rom[13'h056f] = 0; assign rom[13'h0570] = 0; assign rom[13'h0571] = 0; assign rom[13'h0572] = 0; assign rom[13'h0573] = 0; assign rom[13'h0574] = 0; assign rom[13'h0575] = 0; assign rom[13'h0576] = 0; assign rom[13'h0577] = 0; assign rom[13'h0578] = 0; assign rom[13'h0579] = 0; assign rom[13'h057a] = 0; assign rom[13'h057b] = 0; assign rom[13'h057c] = 0; assign rom[13'h057d] = 0; assign rom[13'h057e] = 0; assign rom[13'h057f] = 0; assign rom[13'h0580] = 0; assign rom[13'h0581] = 0; assign rom[13'h0582] = 0; assign rom[13'h0583] = 0; assign rom[13'h0584] = 0; assign rom[13'h0585] = 0; assign rom[13'h0586] = 0; assign rom[13'h0587] = 0; assign rom[13'h0588] = 0; assign rom[13'h0589] = 0; assign rom[13'h058a] = 0; assign rom[13'h058b] = 0; assign rom[13'h058c] = 0; assign rom[13'h058d] = 0; assign rom[13'h058e] = 0; assign rom[13'h058f] = 0; assign rom[13'h0590] = 0; assign rom[13'h0591] = 0; assign rom[13'h0592] = 0; assign rom[13'h0593] = 0; assign rom[13'h0594] = 0; assign rom[13'h0595] = 0; assign rom[13'h0596] = 0; assign rom[13'h0597] = 0; assign rom[13'h0598] = 0; assign rom[13'h0599] = 0; assign rom[13'h059a] = 0; assign rom[13'h059b] = 0; assign rom[13'h059c] = 0; assign rom[13'h059d] = 0; assign rom[13'h059e] = 0; assign rom[13'h059f] = 0; assign rom[13'h05a0] = 0; assign rom[13'h05a1] = 0; assign rom[13'h05a2] = 0; assign rom[13'h05a3] = 0; assign rom[13'h05a4] = 0; assign rom[13'h05a5] = 0; assign rom[13'h05a6] = 0; assign rom[13'h05a7] = 0; assign rom[13'h05a8] = 0; assign rom[13'h05a9] = 0; assign rom[13'h05aa] = 0; assign rom[13'h05ab] = 0; assign rom[13'h05ac] = 0; assign rom[13'h05ad] = 0; assign rom[13'h05ae] = 0; assign rom[13'h05af] = 0; assign rom[13'h05b0] = 0; assign rom[13'h05b1] = 0; assign rom[13'h05b2] = 0; assign rom[13'h05b3] = 0; assign rom[13'h05b4] = 0; assign rom[13'h05b5] = 0; assign rom[13'h05b6] = 0; assign rom[13'h05b7] = 0; assign rom[13'h05b8] = 0; assign rom[13'h05b9] = 0; assign rom[13'h05ba] = 0; assign rom[13'h05bb] = 0; assign rom[13'h05bc] = 0; assign rom[13'h05bd] = 0; assign rom[13'h05be] = 0; assign rom[13'h05bf] = 0; assign rom[13'h05c0] = 0; assign rom[13'h05c1] = 0; assign rom[13'h05c2] = 0; assign rom[13'h05c3] = 0; assign rom[13'h05c4] = 0; assign rom[13'h05c5] = 0; assign rom[13'h05c6] = 0; assign rom[13'h05c7] = 0; assign rom[13'h05c8] = 0; assign rom[13'h05c9] = 0; assign rom[13'h05ca] = 0; assign rom[13'h05cb] = 0; assign rom[13'h05cc] = 0; assign rom[13'h05cd] = 0; assign rom[13'h05ce] = 0; assign rom[13'h05cf] = 0; assign rom[13'h05d0] = 0; assign rom[13'h05d1] = 0; assign rom[13'h05d2] = 0; assign rom[13'h05d3] = 0; assign rom[13'h05d4] = 0; assign rom[13'h05d5] = 0; assign rom[13'h05d6] = 0; assign rom[13'h05d7] = 0; assign rom[13'h05d8] = 0; assign rom[13'h05d9] = 0; assign rom[13'h05da] = 0; assign rom[13'h05db] = 0; assign rom[13'h05dc] = 0; assign rom[13'h05dd] = 0; assign rom[13'h05de] = 0; assign rom[13'h05df] = 0; assign rom[13'h05e0] = 0; assign rom[13'h05e1] = 0; assign rom[13'h05e2] = 0; assign rom[13'h05e3] = 0; assign rom[13'h05e4] = 0; assign rom[13'h05e5] = 0; assign rom[13'h05e6] = 0; assign rom[13'h05e7] = 0; assign rom[13'h05e8] = 0; assign rom[13'h05e9] = 0; assign rom[13'h05ea] = 0; assign rom[13'h05eb] = 0; assign rom[13'h05ec] = 0; assign rom[13'h05ed] = 0; assign rom[13'h05ee] = 0; assign rom[13'h05ef] = 0; assign rom[13'h05f0] = 0; assign rom[13'h05f1] = 0; assign rom[13'h05f2] = 0; assign rom[13'h05f3] = 0; assign rom[13'h05f4] = 0; assign rom[13'h05f5] = 0; assign rom[13'h05f6] = 0; assign rom[13'h05f7] = 0; assign rom[13'h05f8] = 0; assign rom[13'h05f9] = 0; assign rom[13'h05fa] = 0; assign rom[13'h05fb] = 0; assign rom[13'h05fc] = 0; assign rom[13'h05fd] = 0; assign rom[13'h05fe] = 0; assign rom[13'h05ff] = 0; assign rom[13'h0600] = 0; assign rom[13'h0601] = 0; assign rom[13'h0602] = 0; assign rom[13'h0603] = 0; assign rom[13'h0604] = 0; assign rom[13'h0605] = 0; assign rom[13'h0606] = 0; assign rom[13'h0607] = 0; assign rom[13'h0608] = 0; assign rom[13'h0609] = 0; assign rom[13'h060a] = 0; assign rom[13'h060b] = 0; assign rom[13'h060c] = 0; assign rom[13'h060d] = 0; assign rom[13'h060e] = 0; assign rom[13'h060f] = 0; assign rom[13'h0610] = 0; assign rom[13'h0611] = 0; assign rom[13'h0612] = 0; assign rom[13'h0613] = 0; assign rom[13'h0614] = 0; assign rom[13'h0615] = 0; assign rom[13'h0616] = 0; assign rom[13'h0617] = 0; assign rom[13'h0618] = 0; assign rom[13'h0619] = 0; assign rom[13'h061a] = 0; assign rom[13'h061b] = 0; assign rom[13'h061c] = 0; assign rom[13'h061d] = 0; assign rom[13'h061e] = 0; assign rom[13'h061f] = 0; assign rom[13'h0620] = 0; assign rom[13'h0621] = 0; assign rom[13'h0622] = 0; assign rom[13'h0623] = 0; assign rom[13'h0624] = 0; assign rom[13'h0625] = 0; assign rom[13'h0626] = 0; assign rom[13'h0627] = 0; assign rom[13'h0628] = 0; assign rom[13'h0629] = 0; assign rom[13'h062a] = 0; assign rom[13'h062b] = 0; assign rom[13'h062c] = 0; assign rom[13'h062d] = 0; assign rom[13'h062e] = 0; assign rom[13'h062f] = 0; assign rom[13'h0630] = 0; assign rom[13'h0631] = 0; assign rom[13'h0632] = 0; assign rom[13'h0633] = 0; assign rom[13'h0634] = 0; assign rom[13'h0635] = 0; assign rom[13'h0636] = 0; assign rom[13'h0637] = 0; assign rom[13'h0638] = 0; assign rom[13'h0639] = 0; assign rom[13'h063a] = 0; assign rom[13'h063b] = 0; assign rom[13'h063c] = 0; assign rom[13'h063d] = 0; assign rom[13'h063e] = 0; assign rom[13'h063f] = 0; assign rom[13'h0640] = 0; assign rom[13'h0641] = 0; assign rom[13'h0642] = 0; assign rom[13'h0643] = 0; assign rom[13'h0644] = 0; assign rom[13'h0645] = 0; assign rom[13'h0646] = 0; assign rom[13'h0647] = 0; assign rom[13'h0648] = 0; assign rom[13'h0649] = 0; assign rom[13'h064a] = 0; assign rom[13'h064b] = 0; assign rom[13'h064c] = 0; assign rom[13'h064d] = 0; assign rom[13'h064e] = 0; assign rom[13'h064f] = 0; assign rom[13'h0650] = 0; assign rom[13'h0651] = 0; assign rom[13'h0652] = 0; assign rom[13'h0653] = 0; assign rom[13'h0654] = 0; assign rom[13'h0655] = 0; assign rom[13'h0656] = 0; assign rom[13'h0657] = 0; assign rom[13'h0658] = 0; assign rom[13'h0659] = 0; assign rom[13'h065a] = 0; assign rom[13'h065b] = 0; assign rom[13'h065c] = 0; assign rom[13'h065d] = 0; assign rom[13'h065e] = 0; assign rom[13'h065f] = 0; assign rom[13'h0660] = 0; assign rom[13'h0661] = 0; assign rom[13'h0662] = 0; assign rom[13'h0663] = 0; assign rom[13'h0664] = 0; assign rom[13'h0665] = 0; assign rom[13'h0666] = 0; assign rom[13'h0667] = 0; assign rom[13'h0668] = 0; assign rom[13'h0669] = 0; assign rom[13'h066a] = 0; assign rom[13'h066b] = 0; assign rom[13'h066c] = 0; assign rom[13'h066d] = 0; assign rom[13'h066e] = 0; assign rom[13'h066f] = 0; assign rom[13'h0670] = 0; assign rom[13'h0671] = 0; assign rom[13'h0672] = 0; assign rom[13'h0673] = 0; assign rom[13'h0674] = 0; assign rom[13'h0675] = 0; assign rom[13'h0676] = 0; assign rom[13'h0677] = 0; assign rom[13'h0678] = 0; assign rom[13'h0679] = 0; assign rom[13'h067a] = 0; assign rom[13'h067b] = 0; assign rom[13'h067c] = 0; assign rom[13'h067d] = 0; assign rom[13'h067e] = 0; assign rom[13'h067f] = 0; assign rom[13'h0680] = 0; assign rom[13'h0681] = 0; assign rom[13'h0682] = 0; assign rom[13'h0683] = 0; assign rom[13'h0684] = 0; assign rom[13'h0685] = 0; assign rom[13'h0686] = 0; assign rom[13'h0687] = 0; assign rom[13'h0688] = 0; assign rom[13'h0689] = 0; assign rom[13'h068a] = 0; assign rom[13'h068b] = 0; assign rom[13'h068c] = 0; assign rom[13'h068d] = 0; assign rom[13'h068e] = 0; assign rom[13'h068f] = 0; assign rom[13'h0690] = 0; assign rom[13'h0691] = 0; assign rom[13'h0692] = 0; assign rom[13'h0693] = 0; assign rom[13'h0694] = 0; assign rom[13'h0695] = 0; assign rom[13'h0696] = 0; assign rom[13'h0697] = 0; assign rom[13'h0698] = 0; assign rom[13'h0699] = 0; assign rom[13'h069a] = 0; assign rom[13'h069b] = 0; assign rom[13'h069c] = 0; assign rom[13'h069d] = 0; assign rom[13'h069e] = 0; assign rom[13'h069f] = 0; assign rom[13'h06a0] = 0; assign rom[13'h06a1] = 0; assign rom[13'h06a2] = 0; assign rom[13'h06a3] = 0; assign rom[13'h06a4] = 0; assign rom[13'h06a5] = 0; assign rom[13'h06a6] = 0; assign rom[13'h06a7] = 0; assign rom[13'h06a8] = 0; assign rom[13'h06a9] = 0; assign rom[13'h06aa] = 0; assign rom[13'h06ab] = 0; assign rom[13'h06ac] = 0; assign rom[13'h06ad] = 0; assign rom[13'h06ae] = 0; assign rom[13'h06af] = 0; assign rom[13'h06b0] = 0; assign rom[13'h06b1] = 0; assign rom[13'h06b2] = 0; assign rom[13'h06b3] = 0; assign rom[13'h06b4] = 0; assign rom[13'h06b5] = 0; assign rom[13'h06b6] = 0; assign rom[13'h06b7] = 0; assign rom[13'h06b8] = 0; assign rom[13'h06b9] = 0; assign rom[13'h06ba] = 0; assign rom[13'h06bb] = 0; assign rom[13'h06bc] = 0; assign rom[13'h06bd] = 0; assign rom[13'h06be] = 0; assign rom[13'h06bf] = 0; assign rom[13'h06c0] = 0; assign rom[13'h06c1] = 0; assign rom[13'h06c2] = 0; assign rom[13'h06c3] = 0; assign rom[13'h06c4] = 0; assign rom[13'h06c5] = 0; assign rom[13'h06c6] = 0; assign rom[13'h06c7] = 0; assign rom[13'h06c8] = 0; assign rom[13'h06c9] = 0; assign rom[13'h06ca] = 0; assign rom[13'h06cb] = 0; assign rom[13'h06cc] = 0; assign rom[13'h06cd] = 0; assign rom[13'h06ce] = 0; assign rom[13'h06cf] = 0; assign rom[13'h06d0] = 0; assign rom[13'h06d1] = 0; assign rom[13'h06d2] = 0; assign rom[13'h06d3] = 0; assign rom[13'h06d4] = 0; assign rom[13'h06d5] = 0; assign rom[13'h06d6] = 0; assign rom[13'h06d7] = 0; assign rom[13'h06d8] = 0; assign rom[13'h06d9] = 0; assign rom[13'h06da] = 0; assign rom[13'h06db] = 0; assign rom[13'h06dc] = 0; assign rom[13'h06dd] = 0; assign rom[13'h06de] = 0; assign rom[13'h06df] = 0; assign rom[13'h06e0] = 0; assign rom[13'h06e1] = 0; assign rom[13'h06e2] = 0; assign rom[13'h06e3] = 0; assign rom[13'h06e4] = 0; assign rom[13'h06e5] = 0; assign rom[13'h06e6] = 0; assign rom[13'h06e7] = 0; assign rom[13'h06e8] = 0; assign rom[13'h06e9] = 0; assign rom[13'h06ea] = 0; assign rom[13'h06eb] = 0; assign rom[13'h06ec] = 0; assign rom[13'h06ed] = 0; assign rom[13'h06ee] = 0; assign rom[13'h06ef] = 0; assign rom[13'h06f0] = 0; assign rom[13'h06f1] = 0; assign rom[13'h06f2] = 0; assign rom[13'h06f3] = 0; assign rom[13'h06f4] = 0; assign rom[13'h06f5] = 0; assign rom[13'h06f6] = 0; assign rom[13'h06f7] = 0; assign rom[13'h06f8] = 0; assign rom[13'h06f9] = 0; assign rom[13'h06fa] = 0; assign rom[13'h06fb] = 0; assign rom[13'h06fc] = 0; assign rom[13'h06fd] = 0; assign rom[13'h06fe] = 0; assign rom[13'h06ff] = 0; assign rom[13'h0700] = 0; assign rom[13'h0701] = 0; assign rom[13'h0702] = 0; assign rom[13'h0703] = 0; assign rom[13'h0704] = 0; assign rom[13'h0705] = 0; assign rom[13'h0706] = 0; assign rom[13'h0707] = 0; assign rom[13'h0708] = 0; assign rom[13'h0709] = 0; assign rom[13'h070a] = 0; assign rom[13'h070b] = 0; assign rom[13'h070c] = 0; assign rom[13'h070d] = 0; assign rom[13'h070e] = 0; assign rom[13'h070f] = 0; assign rom[13'h0710] = 0; assign rom[13'h0711] = 0; assign rom[13'h0712] = 0; assign rom[13'h0713] = 0; assign rom[13'h0714] = 0; assign rom[13'h0715] = 0; assign rom[13'h0716] = 0; assign rom[13'h0717] = 0; assign rom[13'h0718] = 0; assign rom[13'h0719] = 0; assign rom[13'h071a] = 0; assign rom[13'h071b] = 0; assign rom[13'h071c] = 0; assign rom[13'h071d] = 0; assign rom[13'h071e] = 0; assign rom[13'h071f] = 0; assign rom[13'h0720] = 0; assign rom[13'h0721] = 0; assign rom[13'h0722] = 0; assign rom[13'h0723] = 0; assign rom[13'h0724] = 0; assign rom[13'h0725] = 0; assign rom[13'h0726] = 0; assign rom[13'h0727] = 0; assign rom[13'h0728] = 0; assign rom[13'h0729] = 0; assign rom[13'h072a] = 0; assign rom[13'h072b] = 0; assign rom[13'h072c] = 0; assign rom[13'h072d] = 0; assign rom[13'h072e] = 0; assign rom[13'h072f] = 0; assign rom[13'h0730] = 0; assign rom[13'h0731] = 0; assign rom[13'h0732] = 0; assign rom[13'h0733] = 0; assign rom[13'h0734] = 0; assign rom[13'h0735] = 0; assign rom[13'h0736] = 0; assign rom[13'h0737] = 0; assign rom[13'h0738] = 0; assign rom[13'h0739] = 0; assign rom[13'h073a] = 0; assign rom[13'h073b] = 0; assign rom[13'h073c] = 0; assign rom[13'h073d] = 0; assign rom[13'h073e] = 0; assign rom[13'h073f] = 0; assign rom[13'h0740] = 0; assign rom[13'h0741] = 0; assign rom[13'h0742] = 0; assign rom[13'h0743] = 0; assign rom[13'h0744] = 0; assign rom[13'h0745] = 0; assign rom[13'h0746] = 0; assign rom[13'h0747] = 0; assign rom[13'h0748] = 0; assign rom[13'h0749] = 0; assign rom[13'h074a] = 0; assign rom[13'h074b] = 0; assign rom[13'h074c] = 0; assign rom[13'h074d] = 0; assign rom[13'h074e] = 0; assign rom[13'h074f] = 0; assign rom[13'h0750] = 0; assign rom[13'h0751] = 0; assign rom[13'h0752] = 0; assign rom[13'h0753] = 0; assign rom[13'h0754] = 0; assign rom[13'h0755] = 0; assign rom[13'h0756] = 0; assign rom[13'h0757] = 0; assign rom[13'h0758] = 0; assign rom[13'h0759] = 0; assign rom[13'h075a] = 0; assign rom[13'h075b] = 0; assign rom[13'h075c] = 0; assign rom[13'h075d] = 0; assign rom[13'h075e] = 0; assign rom[13'h075f] = 0; assign rom[13'h0760] = 0; assign rom[13'h0761] = 0; assign rom[13'h0762] = 0; assign rom[13'h0763] = 0; assign rom[13'h0764] = 0; assign rom[13'h0765] = 0; assign rom[13'h0766] = 0; assign rom[13'h0767] = 0; assign rom[13'h0768] = 0; assign rom[13'h0769] = 0; assign rom[13'h076a] = 0; assign rom[13'h076b] = 0; assign rom[13'h076c] = 0; assign rom[13'h076d] = 0; assign rom[13'h076e] = 0; assign rom[13'h076f] = 0; assign rom[13'h0770] = 0; assign rom[13'h0771] = 0; assign rom[13'h0772] = 0; assign rom[13'h0773] = 0; assign rom[13'h0774] = 0; assign rom[13'h0775] = 0; assign rom[13'h0776] = 0; assign rom[13'h0777] = 0; assign rom[13'h0778] = 0; assign rom[13'h0779] = 0; assign rom[13'h077a] = 0; assign rom[13'h077b] = 0; assign rom[13'h077c] = 0; assign rom[13'h077d] = 0; assign rom[13'h077e] = 0; assign rom[13'h077f] = 0; assign rom[13'h0780] = 0; assign rom[13'h0781] = 0; assign rom[13'h0782] = 0; assign rom[13'h0783] = 0; assign rom[13'h0784] = 0; assign rom[13'h0785] = 0; assign rom[13'h0786] = 0; assign rom[13'h0787] = 0; assign rom[13'h0788] = 0; assign rom[13'h0789] = 0; assign rom[13'h078a] = 0; assign rom[13'h078b] = 0; assign rom[13'h078c] = 0; assign rom[13'h078d] = 0; assign rom[13'h078e] = 0; assign rom[13'h078f] = 0; assign rom[13'h0790] = 0; assign rom[13'h0791] = 0; assign rom[13'h0792] = 0; assign rom[13'h0793] = 0; assign rom[13'h0794] = 0; assign rom[13'h0795] = 0; assign rom[13'h0796] = 0; assign rom[13'h0797] = 0; assign rom[13'h0798] = 0; assign rom[13'h0799] = 0; assign rom[13'h079a] = 0; assign rom[13'h079b] = 0; assign rom[13'h079c] = 0; assign rom[13'h079d] = 0; assign rom[13'h079e] = 0; assign rom[13'h079f] = 0; assign rom[13'h07a0] = 0; assign rom[13'h07a1] = 0; assign rom[13'h07a2] = 0; assign rom[13'h07a3] = 0; assign rom[13'h07a4] = 0; assign rom[13'h07a5] = 0; assign rom[13'h07a6] = 0; assign rom[13'h07a7] = 0; assign rom[13'h07a8] = 0; assign rom[13'h07a9] = 0; assign rom[13'h07aa] = 0; assign rom[13'h07ab] = 0; assign rom[13'h07ac] = 0; assign rom[13'h07ad] = 0; assign rom[13'h07ae] = 0; assign rom[13'h07af] = 0; assign rom[13'h07b0] = 0; assign rom[13'h07b1] = 0; assign rom[13'h07b2] = 0; assign rom[13'h07b3] = 0; assign rom[13'h07b4] = 0; assign rom[13'h07b5] = 0; assign rom[13'h07b6] = 0; assign rom[13'h07b7] = 0; assign rom[13'h07b8] = 0; assign rom[13'h07b9] = 0; assign rom[13'h07ba] = 0; assign rom[13'h07bb] = 0; assign rom[13'h07bc] = 0; assign rom[13'h07bd] = 0; assign rom[13'h07be] = 0; assign rom[13'h07bf] = 0; assign rom[13'h07c0] = 0; assign rom[13'h07c1] = 0; assign rom[13'h07c2] = 0; assign rom[13'h07c3] = 0; assign rom[13'h07c4] = 0; assign rom[13'h07c5] = 0; assign rom[13'h07c6] = 0; assign rom[13'h07c7] = 0; assign rom[13'h07c8] = 0; assign rom[13'h07c9] = 0; assign rom[13'h07ca] = 0; assign rom[13'h07cb] = 0; assign rom[13'h07cc] = 0; assign rom[13'h07cd] = 0; assign rom[13'h07ce] = 0; assign rom[13'h07cf] = 0; assign rom[13'h07d0] = 0; assign rom[13'h07d1] = 0; assign rom[13'h07d2] = 0; assign rom[13'h07d3] = 0; assign rom[13'h07d4] = 0; assign rom[13'h07d5] = 0; assign rom[13'h07d6] = 0; assign rom[13'h07d7] = 0; assign rom[13'h07d8] = 0; assign rom[13'h07d9] = 0; assign rom[13'h07da] = 0; assign rom[13'h07db] = 0; assign rom[13'h07dc] = 0; assign rom[13'h07dd] = 0; assign rom[13'h07de] = 0; assign rom[13'h07df] = 0; assign rom[13'h07e0] = 0; assign rom[13'h07e1] = 0; assign rom[13'h07e2] = 0; assign rom[13'h07e3] = 0; assign rom[13'h07e4] = 0; assign rom[13'h07e5] = 0; assign rom[13'h07e6] = 0; assign rom[13'h07e7] = 0; assign rom[13'h07e8] = 0; assign rom[13'h07e9] = 0; assign rom[13'h07ea] = 0; assign rom[13'h07eb] = 0; assign rom[13'h07ec] = 0; assign rom[13'h07ed] = 0; assign rom[13'h07ee] = 0; assign rom[13'h07ef] = 0; assign rom[13'h07f0] = 0; assign rom[13'h07f1] = 0; assign rom[13'h07f2] = 0; assign rom[13'h07f3] = 0; assign rom[13'h07f4] = 0; assign rom[13'h07f5] = 0; assign rom[13'h07f6] = 0; assign rom[13'h07f7] = 0; assign rom[13'h07f8] = 0; assign rom[13'h07f9] = 0; assign rom[13'h07fa] = 0; assign rom[13'h07fb] = 0; assign rom[13'h07fc] = 0; assign rom[13'h07fd] = 0; assign rom[13'h07fe] = 0; assign rom[13'h07ff] = 0; assign rom[13'h0800] = 0; assign rom[13'h0801] = 0; assign rom[13'h0802] = 0; assign rom[13'h0803] = 0; assign rom[13'h0804] = 0; assign rom[13'h0805] = 0; assign rom[13'h0806] = 0; assign rom[13'h0807] = 0; assign rom[13'h0808] = 0; assign rom[13'h0809] = 0; assign rom[13'h080a] = 0; assign rom[13'h080b] = 0; assign rom[13'h080c] = 0; assign rom[13'h080d] = 0; assign rom[13'h080e] = 0; assign rom[13'h080f] = 0; assign rom[13'h0810] = 0; assign rom[13'h0811] = 0; assign rom[13'h0812] = 0; assign rom[13'h0813] = 0; assign rom[13'h0814] = 0; assign rom[13'h0815] = 0; assign rom[13'h0816] = 0; assign rom[13'h0817] = 0; assign rom[13'h0818] = 0; assign rom[13'h0819] = 0; assign rom[13'h081a] = 0; assign rom[13'h081b] = 0; assign rom[13'h081c] = 0; assign rom[13'h081d] = 0; assign rom[13'h081e] = 0; assign rom[13'h081f] = 0; assign rom[13'h0820] = 0; assign rom[13'h0821] = 0; assign rom[13'h0822] = 0; assign rom[13'h0823] = 0; assign rom[13'h0824] = 0; assign rom[13'h0825] = 0; assign rom[13'h0826] = 0; assign rom[13'h0827] = 0; assign rom[13'h0828] = 0; assign rom[13'h0829] = 0; assign rom[13'h082a] = 0; assign rom[13'h082b] = 0; assign rom[13'h082c] = 0; assign rom[13'h082d] = 0; assign rom[13'h082e] = 0; assign rom[13'h082f] = 0; assign rom[13'h0830] = 0; assign rom[13'h0831] = 0; assign rom[13'h0832] = 0; assign rom[13'h0833] = 0; assign rom[13'h0834] = 0; assign rom[13'h0835] = 0; assign rom[13'h0836] = 0; assign rom[13'h0837] = 0; assign rom[13'h0838] = 0; assign rom[13'h0839] = 0; assign rom[13'h083a] = 0; assign rom[13'h083b] = 0; assign rom[13'h083c] = 0; assign rom[13'h083d] = 0; assign rom[13'h083e] = 0; assign rom[13'h083f] = 0; assign rom[13'h0840] = 0; assign rom[13'h0841] = 0; assign rom[13'h0842] = 0; assign rom[13'h0843] = 1; assign rom[13'h0844] = 1; assign rom[13'h0845] = 0; assign rom[13'h0846] = 0; assign rom[13'h0847] = 0; assign rom[13'h0848] = 0; assign rom[13'h0849] = 0; assign rom[13'h084a] = 0; assign rom[13'h084b] = 1; assign rom[13'h084c] = 1; assign rom[13'h084d] = 0; assign rom[13'h084e] = 0; assign rom[13'h084f] = 0; assign rom[13'h0850] = 0; assign rom[13'h0851] = 0; assign rom[13'h0852] = 0; assign rom[13'h0853] = 1; assign rom[13'h0854] = 1; assign rom[13'h0855] = 0; assign rom[13'h0856] = 0; assign rom[13'h0857] = 0; assign rom[13'h0858] = 0; assign rom[13'h0859] = 0; assign rom[13'h085a] = 0; assign rom[13'h085b] = 1; assign rom[13'h085c] = 1; assign rom[13'h085d] = 0; assign rom[13'h085e] = 0; assign rom[13'h085f] = 0; assign rom[13'h0860] = 0; assign rom[13'h0861] = 0; assign rom[13'h0862] = 0; assign rom[13'h0863] = 0; assign rom[13'h0864] = 0; assign rom[13'h0865] = 0; assign rom[13'h0866] = 0; assign rom[13'h0867] = 0; assign rom[13'h0868] = 0; assign rom[13'h0869] = 0; assign rom[13'h086a] = 0; assign rom[13'h086b] = 1; assign rom[13'h086c] = 1; assign rom[13'h086d] = 0; assign rom[13'h086e] = 0; assign rom[13'h086f] = 0; assign rom[13'h0870] = 0; assign rom[13'h0871] = 0; assign rom[13'h0872] = 0; assign rom[13'h0873] = 1; assign rom[13'h0874] = 1; assign rom[13'h0875] = 0; assign rom[13'h0876] = 0; assign rom[13'h0877] = 0; assign rom[13'h0878] = 0; assign rom[13'h0879] = 0; assign rom[13'h087a] = 0; assign rom[13'h087b] = 0; assign rom[13'h087c] = 0; assign rom[13'h087d] = 0; assign rom[13'h087e] = 0; assign rom[13'h087f] = 0; assign rom[13'h0880] = 0; assign rom[13'h0881] = 1; assign rom[13'h0882] = 1; assign rom[13'h0883] = 0; assign rom[13'h0884] = 1; assign rom[13'h0885] = 1; assign rom[13'h0886] = 0; assign rom[13'h0887] = 0; assign rom[13'h0888] = 0; assign rom[13'h0889] = 1; assign rom[13'h088a] = 1; assign rom[13'h088b] = 0; assign rom[13'h088c] = 1; assign rom[13'h088d] = 1; assign rom[13'h088e] = 0; assign rom[13'h088f] = 0; assign rom[13'h0890] = 0; assign rom[13'h0891] = 1; assign rom[13'h0892] = 0; assign rom[13'h0893] = 0; assign rom[13'h0894] = 1; assign rom[13'h0895] = 0; assign rom[13'h0896] = 0; assign rom[13'h0897] = 0; assign rom[13'h0898] = 0; assign rom[13'h0899] = 0; assign rom[13'h089a] = 0; assign rom[13'h089b] = 0; assign rom[13'h089c] = 0; assign rom[13'h089d] = 0; assign rom[13'h089e] = 0; assign rom[13'h089f] = 0; assign rom[13'h08a0] = 0; assign rom[13'h08a1] = 0; assign rom[13'h08a2] = 0; assign rom[13'h08a3] = 0; assign rom[13'h08a4] = 0; assign rom[13'h08a5] = 0; assign rom[13'h08a6] = 0; assign rom[13'h08a7] = 0; assign rom[13'h08a8] = 0; assign rom[13'h08a9] = 0; assign rom[13'h08aa] = 0; assign rom[13'h08ab] = 0; assign rom[13'h08ac] = 0; assign rom[13'h08ad] = 0; assign rom[13'h08ae] = 0; assign rom[13'h08af] = 0; assign rom[13'h08b0] = 0; assign rom[13'h08b1] = 0; assign rom[13'h08b2] = 0; assign rom[13'h08b3] = 0; assign rom[13'h08b4] = 0; assign rom[13'h08b5] = 0; assign rom[13'h08b6] = 0; assign rom[13'h08b7] = 0; assign rom[13'h08b8] = 0; assign rom[13'h08b9] = 0; assign rom[13'h08ba] = 0; assign rom[13'h08bb] = 0; assign rom[13'h08bc] = 0; assign rom[13'h08bd] = 0; assign rom[13'h08be] = 0; assign rom[13'h08bf] = 0; assign rom[13'h08c0] = 0; assign rom[13'h08c1] = 1; assign rom[13'h08c2] = 1; assign rom[13'h08c3] = 0; assign rom[13'h08c4] = 1; assign rom[13'h08c5] = 1; assign rom[13'h08c6] = 0; assign rom[13'h08c7] = 0; assign rom[13'h08c8] = 0; assign rom[13'h08c9] = 1; assign rom[13'h08ca] = 1; assign rom[13'h08cb] = 0; assign rom[13'h08cc] = 1; assign rom[13'h08cd] = 1; assign rom[13'h08ce] = 0; assign rom[13'h08cf] = 0; assign rom[13'h08d0] = 1; assign rom[13'h08d1] = 1; assign rom[13'h08d2] = 1; assign rom[13'h08d3] = 1; assign rom[13'h08d4] = 1; assign rom[13'h08d5] = 1; assign rom[13'h08d6] = 1; assign rom[13'h08d7] = 0; assign rom[13'h08d8] = 0; assign rom[13'h08d9] = 1; assign rom[13'h08da] = 1; assign rom[13'h08db] = 0; assign rom[13'h08dc] = 1; assign rom[13'h08dd] = 1; assign rom[13'h08de] = 0; assign rom[13'h08df] = 0; assign rom[13'h08e0] = 1; assign rom[13'h08e1] = 1; assign rom[13'h08e2] = 1; assign rom[13'h08e3] = 1; assign rom[13'h08e4] = 1; assign rom[13'h08e5] = 1; assign rom[13'h08e6] = 1; assign rom[13'h08e7] = 0; assign rom[13'h08e8] = 0; assign rom[13'h08e9] = 1; assign rom[13'h08ea] = 1; assign rom[13'h08eb] = 0; assign rom[13'h08ec] = 1; assign rom[13'h08ed] = 1; assign rom[13'h08ee] = 0; assign rom[13'h08ef] = 0; assign rom[13'h08f0] = 0; assign rom[13'h08f1] = 1; assign rom[13'h08f2] = 1; assign rom[13'h08f3] = 0; assign rom[13'h08f4] = 1; assign rom[13'h08f5] = 1; assign rom[13'h08f6] = 0; assign rom[13'h08f7] = 0; assign rom[13'h08f8] = 0; assign rom[13'h08f9] = 0; assign rom[13'h08fa] = 0; assign rom[13'h08fb] = 0; assign rom[13'h08fc] = 0; assign rom[13'h08fd] = 0; assign rom[13'h08fe] = 0; assign rom[13'h08ff] = 0; assign rom[13'h0900] = 0; assign rom[13'h0901] = 0; assign rom[13'h0902] = 0; assign rom[13'h0903] = 1; assign rom[13'h0904] = 1; assign rom[13'h0905] = 0; assign rom[13'h0906] = 0; assign rom[13'h0907] = 0; assign rom[13'h0908] = 0; assign rom[13'h0909] = 1; assign rom[13'h090a] = 1; assign rom[13'h090b] = 1; assign rom[13'h090c] = 1; assign rom[13'h090d] = 1; assign rom[13'h090e] = 1; assign rom[13'h090f] = 0; assign rom[13'h0910] = 1; assign rom[13'h0911] = 1; assign rom[13'h0912] = 0; assign rom[13'h0913] = 1; assign rom[13'h0914] = 1; assign rom[13'h0915] = 0; assign rom[13'h0916] = 0; assign rom[13'h0917] = 0; assign rom[13'h0918] = 0; assign rom[13'h0919] = 1; assign rom[13'h091a] = 1; assign rom[13'h091b] = 1; assign rom[13'h091c] = 1; assign rom[13'h091d] = 1; assign rom[13'h091e] = 1; assign rom[13'h091f] = 0; assign rom[13'h0920] = 0; assign rom[13'h0921] = 0; assign rom[13'h0922] = 0; assign rom[13'h0923] = 1; assign rom[13'h0924] = 1; assign rom[13'h0925] = 0; assign rom[13'h0926] = 1; assign rom[13'h0927] = 1; assign rom[13'h0928] = 0; assign rom[13'h0929] = 1; assign rom[13'h092a] = 1; assign rom[13'h092b] = 1; assign rom[13'h092c] = 1; assign rom[13'h092d] = 1; assign rom[13'h092e] = 1; assign rom[13'h092f] = 0; assign rom[13'h0930] = 0; assign rom[13'h0931] = 0; assign rom[13'h0932] = 0; assign rom[13'h0933] = 1; assign rom[13'h0934] = 1; assign rom[13'h0935] = 0; assign rom[13'h0936] = 0; assign rom[13'h0937] = 0; assign rom[13'h0938] = 0; assign rom[13'h0939] = 0; assign rom[13'h093a] = 0; assign rom[13'h093b] = 0; assign rom[13'h093c] = 0; assign rom[13'h093d] = 0; assign rom[13'h093e] = 0; assign rom[13'h093f] = 0; assign rom[13'h0940] = 0; assign rom[13'h0941] = 1; assign rom[13'h0942] = 1; assign rom[13'h0943] = 0; assign rom[13'h0944] = 0; assign rom[13'h0945] = 0; assign rom[13'h0946] = 1; assign rom[13'h0947] = 0; assign rom[13'h0948] = 0; assign rom[13'h0949] = 1; assign rom[13'h094a] = 1; assign rom[13'h094b] = 0; assign rom[13'h094c] = 0; assign rom[13'h094d] = 1; assign rom[13'h094e] = 1; assign rom[13'h094f] = 0; assign rom[13'h0950] = 0; assign rom[13'h0951] = 0; assign rom[13'h0952] = 0; assign rom[13'h0953] = 0; assign rom[13'h0954] = 1; assign rom[13'h0955] = 1; assign rom[13'h0956] = 0; assign rom[13'h0957] = 0; assign rom[13'h0958] = 0; assign rom[13'h0959] = 0; assign rom[13'h095a] = 0; assign rom[13'h095b] = 1; assign rom[13'h095c] = 1; assign rom[13'h095d] = 0; assign rom[13'h095e] = 0; assign rom[13'h095f] = 0; assign rom[13'h0960] = 0; assign rom[13'h0961] = 0; assign rom[13'h0962] = 1; assign rom[13'h0963] = 1; assign rom[13'h0964] = 0; assign rom[13'h0965] = 0; assign rom[13'h0966] = 0; assign rom[13'h0967] = 0; assign rom[13'h0968] = 0; assign rom[13'h0969] = 1; assign rom[13'h096a] = 1; assign rom[13'h096b] = 0; assign rom[13'h096c] = 0; assign rom[13'h096d] = 1; assign rom[13'h096e] = 1; assign rom[13'h096f] = 0; assign rom[13'h0970] = 0; assign rom[13'h0971] = 1; assign rom[13'h0972] = 0; assign rom[13'h0973] = 0; assign rom[13'h0974] = 0; assign rom[13'h0975] = 1; assign rom[13'h0976] = 1; assign rom[13'h0977] = 0; assign rom[13'h0978] = 0; assign rom[13'h0979] = 0; assign rom[13'h097a] = 0; assign rom[13'h097b] = 0; assign rom[13'h097c] = 0; assign rom[13'h097d] = 0; assign rom[13'h097e] = 0; assign rom[13'h097f] = 0; assign rom[13'h0980] = 0; assign rom[13'h0981] = 0; assign rom[13'h0982] = 1; assign rom[13'h0983] = 1; assign rom[13'h0984] = 1; assign rom[13'h0985] = 0; assign rom[13'h0986] = 0; assign rom[13'h0987] = 0; assign rom[13'h0988] = 0; assign rom[13'h0989] = 1; assign rom[13'h098a] = 1; assign rom[13'h098b] = 0; assign rom[13'h098c] = 1; assign rom[13'h098d] = 1; assign rom[13'h098e] = 0; assign rom[13'h098f] = 0; assign rom[13'h0990] = 0; assign rom[13'h0991] = 1; assign rom[13'h0992] = 1; assign rom[13'h0993] = 0; assign rom[13'h0994] = 1; assign rom[13'h0995] = 0; assign rom[13'h0996] = 0; assign rom[13'h0997] = 0; assign rom[13'h0998] = 0; assign rom[13'h0999] = 1; assign rom[13'h099a] = 1; assign rom[13'h099b] = 1; assign rom[13'h099c] = 0; assign rom[13'h099d] = 1; assign rom[13'h099e] = 1; assign rom[13'h099f] = 0; assign rom[13'h09a0] = 1; assign rom[13'h09a1] = 1; assign rom[13'h09a2] = 0; assign rom[13'h09a3] = 1; assign rom[13'h09a4] = 1; assign rom[13'h09a5] = 1; assign rom[13'h09a6] = 0; assign rom[13'h09a7] = 0; assign rom[13'h09a8] = 1; assign rom[13'h09a9] = 1; assign rom[13'h09aa] = 0; assign rom[13'h09ab] = 0; assign rom[13'h09ac] = 1; assign rom[13'h09ad] = 1; assign rom[13'h09ae] = 0; assign rom[13'h09af] = 0; assign rom[13'h09b0] = 0; assign rom[13'h09b1] = 1; assign rom[13'h09b2] = 1; assign rom[13'h09b3] = 1; assign rom[13'h09b4] = 0; assign rom[13'h09b5] = 1; assign rom[13'h09b6] = 1; assign rom[13'h09b7] = 0; assign rom[13'h09b8] = 0; assign rom[13'h09b9] = 0; assign rom[13'h09ba] = 0; assign rom[13'h09bb] = 0; assign rom[13'h09bc] = 0; assign rom[13'h09bd] = 0; assign rom[13'h09be] = 0; assign rom[13'h09bf] = 0; assign rom[13'h09c0] = 0; assign rom[13'h09c1] = 0; assign rom[13'h09c2] = 0; assign rom[13'h09c3] = 1; assign rom[13'h09c4] = 1; assign rom[13'h09c5] = 0; assign rom[13'h09c6] = 0; assign rom[13'h09c7] = 0; assign rom[13'h09c8] = 0; assign rom[13'h09c9] = 0; assign rom[13'h09ca] = 0; assign rom[13'h09cb] = 1; assign rom[13'h09cc] = 1; assign rom[13'h09cd] = 0; assign rom[13'h09ce] = 0; assign rom[13'h09cf] = 0; assign rom[13'h09d0] = 0; assign rom[13'h09d1] = 0; assign rom[13'h09d2] = 1; assign rom[13'h09d3] = 1; assign rom[13'h09d4] = 0; assign rom[13'h09d5] = 0; assign rom[13'h09d6] = 0; assign rom[13'h09d7] = 0; assign rom[13'h09d8] = 0; assign rom[13'h09d9] = 0; assign rom[13'h09da] = 0; assign rom[13'h09db] = 0; assign rom[13'h09dc] = 0; assign rom[13'h09dd] = 0; assign rom[13'h09de] = 0; assign rom[13'h09df] = 0; assign rom[13'h09e0] = 0; assign rom[13'h09e1] = 0; assign rom[13'h09e2] = 0; assign rom[13'h09e3] = 0; assign rom[13'h09e4] = 0; assign rom[13'h09e5] = 0; assign rom[13'h09e6] = 0; assign rom[13'h09e7] = 0; assign rom[13'h09e8] = 0; assign rom[13'h09e9] = 0; assign rom[13'h09ea] = 0; assign rom[13'h09eb] = 0; assign rom[13'h09ec] = 0; assign rom[13'h09ed] = 0; assign rom[13'h09ee] = 0; assign rom[13'h09ef] = 0; assign rom[13'h09f0] = 0; assign rom[13'h09f1] = 0; assign rom[13'h09f2] = 0; assign rom[13'h09f3] = 0; assign rom[13'h09f4] = 0; assign rom[13'h09f5] = 0; assign rom[13'h09f6] = 0; assign rom[13'h09f7] = 0; assign rom[13'h09f8] = 0; assign rom[13'h09f9] = 0; assign rom[13'h09fa] = 0; assign rom[13'h09fb] = 0; assign rom[13'h09fc] = 0; assign rom[13'h09fd] = 0; assign rom[13'h09fe] = 0; assign rom[13'h09ff] = 0; assign rom[13'h0a00] = 0; assign rom[13'h0a01] = 0; assign rom[13'h0a02] = 0; assign rom[13'h0a03] = 0; assign rom[13'h0a04] = 1; assign rom[13'h0a05] = 1; assign rom[13'h0a06] = 0; assign rom[13'h0a07] = 0; assign rom[13'h0a08] = 0; assign rom[13'h0a09] = 0; assign rom[13'h0a0a] = 0; assign rom[13'h0a0b] = 1; assign rom[13'h0a0c] = 1; assign rom[13'h0a0d] = 0; assign rom[13'h0a0e] = 0; assign rom[13'h0a0f] = 0; assign rom[13'h0a10] = 0; assign rom[13'h0a11] = 0; assign rom[13'h0a12] = 1; assign rom[13'h0a13] = 1; assign rom[13'h0a14] = 0; assign rom[13'h0a15] = 0; assign rom[13'h0a16] = 0; assign rom[13'h0a17] = 0; assign rom[13'h0a18] = 0; assign rom[13'h0a19] = 0; assign rom[13'h0a1a] = 1; assign rom[13'h0a1b] = 1; assign rom[13'h0a1c] = 0; assign rom[13'h0a1d] = 0; assign rom[13'h0a1e] = 0; assign rom[13'h0a1f] = 0; assign rom[13'h0a20] = 0; assign rom[13'h0a21] = 0; assign rom[13'h0a22] = 1; assign rom[13'h0a23] = 1; assign rom[13'h0a24] = 0; assign rom[13'h0a25] = 0; assign rom[13'h0a26] = 0; assign rom[13'h0a27] = 0; assign rom[13'h0a28] = 0; assign rom[13'h0a29] = 0; assign rom[13'h0a2a] = 0; assign rom[13'h0a2b] = 1; assign rom[13'h0a2c] = 1; assign rom[13'h0a2d] = 0; assign rom[13'h0a2e] = 0; assign rom[13'h0a2f] = 0; assign rom[13'h0a30] = 0; assign rom[13'h0a31] = 0; assign rom[13'h0a32] = 0; assign rom[13'h0a33] = 0; assign rom[13'h0a34] = 1; assign rom[13'h0a35] = 1; assign rom[13'h0a36] = 0; assign rom[13'h0a37] = 0; assign rom[13'h0a38] = 0; assign rom[13'h0a39] = 0; assign rom[13'h0a3a] = 0; assign rom[13'h0a3b] = 0; assign rom[13'h0a3c] = 0; assign rom[13'h0a3d] = 0; assign rom[13'h0a3e] = 0; assign rom[13'h0a3f] = 0; assign rom[13'h0a40] = 0; assign rom[13'h0a41] = 0; assign rom[13'h0a42] = 1; assign rom[13'h0a43] = 1; assign rom[13'h0a44] = 0; assign rom[13'h0a45] = 0; assign rom[13'h0a46] = 0; assign rom[13'h0a47] = 0; assign rom[13'h0a48] = 0; assign rom[13'h0a49] = 0; assign rom[13'h0a4a] = 0; assign rom[13'h0a4b] = 1; assign rom[13'h0a4c] = 1; assign rom[13'h0a4d] = 0; assign rom[13'h0a4e] = 0; assign rom[13'h0a4f] = 0; assign rom[13'h0a50] = 0; assign rom[13'h0a51] = 0; assign rom[13'h0a52] = 0; assign rom[13'h0a53] = 0; assign rom[13'h0a54] = 1; assign rom[13'h0a55] = 1; assign rom[13'h0a56] = 0; assign rom[13'h0a57] = 0; assign rom[13'h0a58] = 0; assign rom[13'h0a59] = 0; assign rom[13'h0a5a] = 0; assign rom[13'h0a5b] = 0; assign rom[13'h0a5c] = 1; assign rom[13'h0a5d] = 1; assign rom[13'h0a5e] = 0; assign rom[13'h0a5f] = 0; assign rom[13'h0a60] = 0; assign rom[13'h0a61] = 0; assign rom[13'h0a62] = 0; assign rom[13'h0a63] = 0; assign rom[13'h0a64] = 1; assign rom[13'h0a65] = 1; assign rom[13'h0a66] = 0; assign rom[13'h0a67] = 0; assign rom[13'h0a68] = 0; assign rom[13'h0a69] = 0; assign rom[13'h0a6a] = 0; assign rom[13'h0a6b] = 1; assign rom[13'h0a6c] = 1; assign rom[13'h0a6d] = 0; assign rom[13'h0a6e] = 0; assign rom[13'h0a6f] = 0; assign rom[13'h0a70] = 0; assign rom[13'h0a71] = 0; assign rom[13'h0a72] = 1; assign rom[13'h0a73] = 1; assign rom[13'h0a74] = 0; assign rom[13'h0a75] = 0; assign rom[13'h0a76] = 0; assign rom[13'h0a77] = 0; assign rom[13'h0a78] = 0; assign rom[13'h0a79] = 0; assign rom[13'h0a7a] = 0; assign rom[13'h0a7b] = 0; assign rom[13'h0a7c] = 0; assign rom[13'h0a7d] = 0; assign rom[13'h0a7e] = 0; assign rom[13'h0a7f] = 0; assign rom[13'h0a80] = 0; assign rom[13'h0a81] = 0; assign rom[13'h0a82] = 0; assign rom[13'h0a83] = 0; assign rom[13'h0a84] = 0; assign rom[13'h0a85] = 0; assign rom[13'h0a86] = 0; assign rom[13'h0a87] = 0; assign rom[13'h0a88] = 0; assign rom[13'h0a89] = 1; assign rom[13'h0a8a] = 1; assign rom[13'h0a8b] = 0; assign rom[13'h0a8c] = 1; assign rom[13'h0a8d] = 1; assign rom[13'h0a8e] = 0; assign rom[13'h0a8f] = 0; assign rom[13'h0a90] = 0; assign rom[13'h0a91] = 0; assign rom[13'h0a92] = 1; assign rom[13'h0a93] = 1; assign rom[13'h0a94] = 1; assign rom[13'h0a95] = 0; assign rom[13'h0a96] = 0; assign rom[13'h0a97] = 0; assign rom[13'h0a98] = 1; assign rom[13'h0a99] = 1; assign rom[13'h0a9a] = 1; assign rom[13'h0a9b] = 1; assign rom[13'h0a9c] = 1; assign rom[13'h0a9d] = 1; assign rom[13'h0a9e] = 1; assign rom[13'h0a9f] = 0; assign rom[13'h0aa0] = 0; assign rom[13'h0aa1] = 0; assign rom[13'h0aa2] = 1; assign rom[13'h0aa3] = 1; assign rom[13'h0aa4] = 1; assign rom[13'h0aa5] = 0; assign rom[13'h0aa6] = 0; assign rom[13'h0aa7] = 0; assign rom[13'h0aa8] = 0; assign rom[13'h0aa9] = 1; assign rom[13'h0aaa] = 1; assign rom[13'h0aab] = 0; assign rom[13'h0aac] = 1; assign rom[13'h0aad] = 1; assign rom[13'h0aae] = 0; assign rom[13'h0aaf] = 0; assign rom[13'h0ab0] = 0; assign rom[13'h0ab1] = 0; assign rom[13'h0ab2] = 0; assign rom[13'h0ab3] = 0; assign rom[13'h0ab4] = 0; assign rom[13'h0ab5] = 0; assign rom[13'h0ab6] = 0; assign rom[13'h0ab7] = 0; assign rom[13'h0ab8] = 0; assign rom[13'h0ab9] = 0; assign rom[13'h0aba] = 0; assign rom[13'h0abb] = 0; assign rom[13'h0abc] = 0; assign rom[13'h0abd] = 0; assign rom[13'h0abe] = 0; assign rom[13'h0abf] = 0; assign rom[13'h0ac0] = 0; assign rom[13'h0ac1] = 0; assign rom[13'h0ac2] = 0; assign rom[13'h0ac3] = 0; assign rom[13'h0ac4] = 0; assign rom[13'h0ac5] = 0; assign rom[13'h0ac6] = 0; assign rom[13'h0ac7] = 0; assign rom[13'h0ac8] = 0; assign rom[13'h0ac9] = 0; assign rom[13'h0aca] = 0; assign rom[13'h0acb] = 1; assign rom[13'h0acc] = 1; assign rom[13'h0acd] = 0; assign rom[13'h0ace] = 0; assign rom[13'h0acf] = 0; assign rom[13'h0ad0] = 0; assign rom[13'h0ad1] = 0; assign rom[13'h0ad2] = 0; assign rom[13'h0ad3] = 1; assign rom[13'h0ad4] = 1; assign rom[13'h0ad5] = 0; assign rom[13'h0ad6] = 0; assign rom[13'h0ad7] = 0; assign rom[13'h0ad8] = 0; assign rom[13'h0ad9] = 1; assign rom[13'h0ada] = 1; assign rom[13'h0adb] = 1; assign rom[13'h0adc] = 1; assign rom[13'h0add] = 1; assign rom[13'h0ade] = 1; assign rom[13'h0adf] = 0; assign rom[13'h0ae0] = 0; assign rom[13'h0ae1] = 0; assign rom[13'h0ae2] = 0; assign rom[13'h0ae3] = 1; assign rom[13'h0ae4] = 1; assign rom[13'h0ae5] = 0; assign rom[13'h0ae6] = 0; assign rom[13'h0ae7] = 0; assign rom[13'h0ae8] = 0; assign rom[13'h0ae9] = 0; assign rom[13'h0aea] = 0; assign rom[13'h0aeb] = 1; assign rom[13'h0aec] = 1; assign rom[13'h0aed] = 0; assign rom[13'h0aee] = 0; assign rom[13'h0aef] = 0; assign rom[13'h0af0] = 0; assign rom[13'h0af1] = 0; assign rom[13'h0af2] = 0; assign rom[13'h0af3] = 0; assign rom[13'h0af4] = 0; assign rom[13'h0af5] = 0; assign rom[13'h0af6] = 0; assign rom[13'h0af7] = 0; assign rom[13'h0af8] = 0; assign rom[13'h0af9] = 0; assign rom[13'h0afa] = 0; assign rom[13'h0afb] = 0; assign rom[13'h0afc] = 0; assign rom[13'h0afd] = 0; assign rom[13'h0afe] = 0; assign rom[13'h0aff] = 0; assign rom[13'h0b00] = 0; assign rom[13'h0b01] = 0; assign rom[13'h0b02] = 0; assign rom[13'h0b03] = 0; assign rom[13'h0b04] = 0; assign rom[13'h0b05] = 0; assign rom[13'h0b06] = 0; assign rom[13'h0b07] = 0; assign rom[13'h0b08] = 0; assign rom[13'h0b09] = 0; assign rom[13'h0b0a] = 0; assign rom[13'h0b0b] = 0; assign rom[13'h0b0c] = 0; assign rom[13'h0b0d] = 0; assign rom[13'h0b0e] = 0; assign rom[13'h0b0f] = 0; assign rom[13'h0b10] = 0; assign rom[13'h0b11] = 0; assign rom[13'h0b12] = 0; assign rom[13'h0b13] = 0; assign rom[13'h0b14] = 0; assign rom[13'h0b15] = 0; assign rom[13'h0b16] = 0; assign rom[13'h0b17] = 0; assign rom[13'h0b18] = 0; assign rom[13'h0b19] = 0; assign rom[13'h0b1a] = 0; assign rom[13'h0b1b] = 0; assign rom[13'h0b1c] = 0; assign rom[13'h0b1d] = 0; assign rom[13'h0b1e] = 0; assign rom[13'h0b1f] = 0; assign rom[13'h0b20] = 0; assign rom[13'h0b21] = 0; assign rom[13'h0b22] = 0; assign rom[13'h0b23] = 0; assign rom[13'h0b24] = 0; assign rom[13'h0b25] = 0; assign rom[13'h0b26] = 0; assign rom[13'h0b27] = 0; assign rom[13'h0b28] = 0; assign rom[13'h0b29] = 0; assign rom[13'h0b2a] = 0; assign rom[13'h0b2b] = 1; assign rom[13'h0b2c] = 1; assign rom[13'h0b2d] = 0; assign rom[13'h0b2e] = 0; assign rom[13'h0b2f] = 0; assign rom[13'h0b30] = 0; assign rom[13'h0b31] = 0; assign rom[13'h0b32] = 0; assign rom[13'h0b33] = 1; assign rom[13'h0b34] = 1; assign rom[13'h0b35] = 0; assign rom[13'h0b36] = 0; assign rom[13'h0b37] = 0; assign rom[13'h0b38] = 0; assign rom[13'h0b39] = 0; assign rom[13'h0b3a] = 0; assign rom[13'h0b3b] = 1; assign rom[13'h0b3c] = 0; assign rom[13'h0b3d] = 0; assign rom[13'h0b3e] = 0; assign rom[13'h0b3f] = 0; assign rom[13'h0b40] = 0; assign rom[13'h0b41] = 0; assign rom[13'h0b42] = 0; assign rom[13'h0b43] = 0; assign rom[13'h0b44] = 0; assign rom[13'h0b45] = 0; assign rom[13'h0b46] = 0; assign rom[13'h0b47] = 0; assign rom[13'h0b48] = 0; assign rom[13'h0b49] = 0; assign rom[13'h0b4a] = 0; assign rom[13'h0b4b] = 0; assign rom[13'h0b4c] = 0; assign rom[13'h0b4d] = 0; assign rom[13'h0b4e] = 0; assign rom[13'h0b4f] = 0; assign rom[13'h0b50] = 0; assign rom[13'h0b51] = 0; assign rom[13'h0b52] = 0; assign rom[13'h0b53] = 0; assign rom[13'h0b54] = 0; assign rom[13'h0b55] = 0; assign rom[13'h0b56] = 0; assign rom[13'h0b57] = 0; assign rom[13'h0b58] = 0; assign rom[13'h0b59] = 1; assign rom[13'h0b5a] = 1; assign rom[13'h0b5b] = 1; assign rom[13'h0b5c] = 1; assign rom[13'h0b5d] = 1; assign rom[13'h0b5e] = 1; assign rom[13'h0b5f] = 0; assign rom[13'h0b60] = 0; assign rom[13'h0b61] = 0; assign rom[13'h0b62] = 0; assign rom[13'h0b63] = 0; assign rom[13'h0b64] = 0; assign rom[13'h0b65] = 0; assign rom[13'h0b66] = 0; assign rom[13'h0b67] = 0; assign rom[13'h0b68] = 0; assign rom[13'h0b69] = 0; assign rom[13'h0b6a] = 0; assign rom[13'h0b6b] = 0; assign rom[13'h0b6c] = 0; assign rom[13'h0b6d] = 0; assign rom[13'h0b6e] = 0; assign rom[13'h0b6f] = 0; assign rom[13'h0b70] = 0; assign rom[13'h0b71] = 0; assign rom[13'h0b72] = 0; assign rom[13'h0b73] = 0; assign rom[13'h0b74] = 0; assign rom[13'h0b75] = 0; assign rom[13'h0b76] = 0; assign rom[13'h0b77] = 0; assign rom[13'h0b78] = 0; assign rom[13'h0b79] = 0; assign rom[13'h0b7a] = 0; assign rom[13'h0b7b] = 0; assign rom[13'h0b7c] = 0; assign rom[13'h0b7d] = 0; assign rom[13'h0b7e] = 0; assign rom[13'h0b7f] = 0; assign rom[13'h0b80] = 0; assign rom[13'h0b81] = 0; assign rom[13'h0b82] = 0; assign rom[13'h0b83] = 0; assign rom[13'h0b84] = 0; assign rom[13'h0b85] = 0; assign rom[13'h0b86] = 0; assign rom[13'h0b87] = 0; assign rom[13'h0b88] = 0; assign rom[13'h0b89] = 0; assign rom[13'h0b8a] = 0; assign rom[13'h0b8b] = 0; assign rom[13'h0b8c] = 0; assign rom[13'h0b8d] = 0; assign rom[13'h0b8e] = 0; assign rom[13'h0b8f] = 0; assign rom[13'h0b90] = 0; assign rom[13'h0b91] = 0; assign rom[13'h0b92] = 0; assign rom[13'h0b93] = 0; assign rom[13'h0b94] = 0; assign rom[13'h0b95] = 0; assign rom[13'h0b96] = 0; assign rom[13'h0b97] = 0; assign rom[13'h0b98] = 0; assign rom[13'h0b99] = 0; assign rom[13'h0b9a] = 0; assign rom[13'h0b9b] = 0; assign rom[13'h0b9c] = 0; assign rom[13'h0b9d] = 0; assign rom[13'h0b9e] = 0; assign rom[13'h0b9f] = 0; assign rom[13'h0ba0] = 0; assign rom[13'h0ba1] = 0; assign rom[13'h0ba2] = 0; assign rom[13'h0ba3] = 0; assign rom[13'h0ba4] = 0; assign rom[13'h0ba5] = 0; assign rom[13'h0ba6] = 0; assign rom[13'h0ba7] = 0; assign rom[13'h0ba8] = 0; assign rom[13'h0ba9] = 0; assign rom[13'h0baa] = 0; assign rom[13'h0bab] = 1; assign rom[13'h0bac] = 1; assign rom[13'h0bad] = 0; assign rom[13'h0bae] = 0; assign rom[13'h0baf] = 0; assign rom[13'h0bb0] = 0; assign rom[13'h0bb1] = 0; assign rom[13'h0bb2] = 0; assign rom[13'h0bb3] = 1; assign rom[13'h0bb4] = 1; assign rom[13'h0bb5] = 0; assign rom[13'h0bb6] = 0; assign rom[13'h0bb7] = 0; assign rom[13'h0bb8] = 0; assign rom[13'h0bb9] = 0; assign rom[13'h0bba] = 0; assign rom[13'h0bbb] = 0; assign rom[13'h0bbc] = 0; assign rom[13'h0bbd] = 0; assign rom[13'h0bbe] = 0; assign rom[13'h0bbf] = 0; assign rom[13'h0bc0] = 0; assign rom[13'h0bc1] = 0; assign rom[13'h0bc2] = 0; assign rom[13'h0bc3] = 0; assign rom[13'h0bc4] = 0; assign rom[13'h0bc5] = 0; assign rom[13'h0bc6] = 1; assign rom[13'h0bc7] = 0; assign rom[13'h0bc8] = 0; assign rom[13'h0bc9] = 0; assign rom[13'h0bca] = 0; assign rom[13'h0bcb] = 0; assign rom[13'h0bcc] = 0; assign rom[13'h0bcd] = 1; assign rom[13'h0bce] = 1; assign rom[13'h0bcf] = 0; assign rom[13'h0bd0] = 0; assign rom[13'h0bd1] = 0; assign rom[13'h0bd2] = 0; assign rom[13'h0bd3] = 0; assign rom[13'h0bd4] = 1; assign rom[13'h0bd5] = 1; assign rom[13'h0bd6] = 0; assign rom[13'h0bd7] = 0; assign rom[13'h0bd8] = 0; assign rom[13'h0bd9] = 0; assign rom[13'h0bda] = 0; assign rom[13'h0bdb] = 1; assign rom[13'h0bdc] = 1; assign rom[13'h0bdd] = 0; assign rom[13'h0bde] = 0; assign rom[13'h0bdf] = 0; assign rom[13'h0be0] = 0; assign rom[13'h0be1] = 0; assign rom[13'h0be2] = 1; assign rom[13'h0be3] = 1; assign rom[13'h0be4] = 0; assign rom[13'h0be5] = 0; assign rom[13'h0be6] = 0; assign rom[13'h0be7] = 0; assign rom[13'h0be8] = 0; assign rom[13'h0be9] = 1; assign rom[13'h0bea] = 1; assign rom[13'h0beb] = 0; assign rom[13'h0bec] = 0; assign rom[13'h0bed] = 0; assign rom[13'h0bee] = 0; assign rom[13'h0bef] = 0; assign rom[13'h0bf0] = 0; assign rom[13'h0bf1] = 1; assign rom[13'h0bf2] = 0; assign rom[13'h0bf3] = 0; assign rom[13'h0bf4] = 0; assign rom[13'h0bf5] = 0; assign rom[13'h0bf6] = 0; assign rom[13'h0bf7] = 0; assign rom[13'h0bf8] = 0; assign rom[13'h0bf9] = 0; assign rom[13'h0bfa] = 0; assign rom[13'h0bfb] = 0; assign rom[13'h0bfc] = 0; assign rom[13'h0bfd] = 0; assign rom[13'h0bfe] = 0; assign rom[13'h0bff] = 0; assign rom[13'h0c00] = 0; assign rom[13'h0c01] = 0; assign rom[13'h0c02] = 1; assign rom[13'h0c03] = 1; assign rom[13'h0c04] = 1; assign rom[13'h0c05] = 1; assign rom[13'h0c06] = 0; assign rom[13'h0c07] = 0; assign rom[13'h0c08] = 0; assign rom[13'h0c09] = 1; assign rom[13'h0c0a] = 1; assign rom[13'h0c0b] = 0; assign rom[13'h0c0c] = 0; assign rom[13'h0c0d] = 1; assign rom[13'h0c0e] = 1; assign rom[13'h0c0f] = 0; assign rom[13'h0c10] = 0; assign rom[13'h0c11] = 1; assign rom[13'h0c12] = 1; assign rom[13'h0c13] = 0; assign rom[13'h0c14] = 1; assign rom[13'h0c15] = 1; assign rom[13'h0c16] = 1; assign rom[13'h0c17] = 0; assign rom[13'h0c18] = 0; assign rom[13'h0c19] = 1; assign rom[13'h0c1a] = 1; assign rom[13'h0c1b] = 1; assign rom[13'h0c1c] = 0; assign rom[13'h0c1d] = 1; assign rom[13'h0c1e] = 1; assign rom[13'h0c1f] = 0; assign rom[13'h0c20] = 0; assign rom[13'h0c21] = 1; assign rom[13'h0c22] = 1; assign rom[13'h0c23] = 0; assign rom[13'h0c24] = 0; assign rom[13'h0c25] = 1; assign rom[13'h0c26] = 1; assign rom[13'h0c27] = 0; assign rom[13'h0c28] = 0; assign rom[13'h0c29] = 1; assign rom[13'h0c2a] = 1; assign rom[13'h0c2b] = 0; assign rom[13'h0c2c] = 0; assign rom[13'h0c2d] = 1; assign rom[13'h0c2e] = 1; assign rom[13'h0c2f] = 0; assign rom[13'h0c30] = 0; assign rom[13'h0c31] = 0; assign rom[13'h0c32] = 1; assign rom[13'h0c33] = 1; assign rom[13'h0c34] = 1; assign rom[13'h0c35] = 1; assign rom[13'h0c36] = 0; assign rom[13'h0c37] = 0; assign rom[13'h0c38] = 0; assign rom[13'h0c39] = 0; assign rom[13'h0c3a] = 0; assign rom[13'h0c3b] = 0; assign rom[13'h0c3c] = 0; assign rom[13'h0c3d] = 0; assign rom[13'h0c3e] = 0; assign rom[13'h0c3f] = 0; assign rom[13'h0c40] = 0; assign rom[13'h0c41] = 0; assign rom[13'h0c42] = 0; assign rom[13'h0c43] = 1; assign rom[13'h0c44] = 1; assign rom[13'h0c45] = 0; assign rom[13'h0c46] = 0; assign rom[13'h0c47] = 0; assign rom[13'h0c48] = 0; assign rom[13'h0c49] = 0; assign rom[13'h0c4a] = 0; assign rom[13'h0c4b] = 1; assign rom[13'h0c4c] = 1; assign rom[13'h0c4d] = 0; assign rom[13'h0c4e] = 0; assign rom[13'h0c4f] = 0; assign rom[13'h0c50] = 0; assign rom[13'h0c51] = 0; assign rom[13'h0c52] = 1; assign rom[13'h0c53] = 1; assign rom[13'h0c54] = 1; assign rom[13'h0c55] = 0; assign rom[13'h0c56] = 0; assign rom[13'h0c57] = 0; assign rom[13'h0c58] = 0; assign rom[13'h0c59] = 0; assign rom[13'h0c5a] = 0; assign rom[13'h0c5b] = 1; assign rom[13'h0c5c] = 1; assign rom[13'h0c5d] = 0; assign rom[13'h0c5e] = 0; assign rom[13'h0c5f] = 0; assign rom[13'h0c60] = 0; assign rom[13'h0c61] = 0; assign rom[13'h0c62] = 0; assign rom[13'h0c63] = 1; assign rom[13'h0c64] = 1; assign rom[13'h0c65] = 0; assign rom[13'h0c66] = 0; assign rom[13'h0c67] = 0; assign rom[13'h0c68] = 0; assign rom[13'h0c69] = 0; assign rom[13'h0c6a] = 0; assign rom[13'h0c6b] = 1; assign rom[13'h0c6c] = 1; assign rom[13'h0c6d] = 0; assign rom[13'h0c6e] = 0; assign rom[13'h0c6f] = 0; assign rom[13'h0c70] = 0; assign rom[13'h0c71] = 0; assign rom[13'h0c72] = 1; assign rom[13'h0c73] = 1; assign rom[13'h0c74] = 1; assign rom[13'h0c75] = 1; assign rom[13'h0c76] = 0; assign rom[13'h0c77] = 0; assign rom[13'h0c78] = 0; assign rom[13'h0c79] = 0; assign rom[13'h0c7a] = 0; assign rom[13'h0c7b] = 0; assign rom[13'h0c7c] = 0; assign rom[13'h0c7d] = 0; assign rom[13'h0c7e] = 0; assign rom[13'h0c7f] = 0; assign rom[13'h0c80] = 0; assign rom[13'h0c81] = 1; assign rom[13'h0c82] = 1; assign rom[13'h0c83] = 1; assign rom[13'h0c84] = 1; assign rom[13'h0c85] = 1; assign rom[13'h0c86] = 0; assign rom[13'h0c87] = 0; assign rom[13'h0c88] = 0; assign rom[13'h0c89] = 0; assign rom[13'h0c8a] = 0; assign rom[13'h0c8b] = 0; assign rom[13'h0c8c] = 0; assign rom[13'h0c8d] = 1; assign rom[13'h0c8e] = 1; assign rom[13'h0c8f] = 0; assign rom[13'h0c90] = 0; assign rom[13'h0c91] = 0; assign rom[13'h0c92] = 0; assign rom[13'h0c93] = 0; assign rom[13'h0c94] = 0; assign rom[13'h0c95] = 1; assign rom[13'h0c96] = 1; assign rom[13'h0c97] = 0; assign rom[13'h0c98] = 0; assign rom[13'h0c99] = 0; assign rom[13'h0c9a] = 1; assign rom[13'h0c9b] = 1; assign rom[13'h0c9c] = 1; assign rom[13'h0c9d] = 1; assign rom[13'h0c9e] = 0; assign rom[13'h0c9f] = 0; assign rom[13'h0ca0] = 0; assign rom[13'h0ca1] = 1; assign rom[13'h0ca2] = 1; assign rom[13'h0ca3] = 0; assign rom[13'h0ca4] = 0; assign rom[13'h0ca5] = 0; assign rom[13'h0ca6] = 0; assign rom[13'h0ca7] = 0; assign rom[13'h0ca8] = 0; assign rom[13'h0ca9] = 1; assign rom[13'h0caa] = 1; assign rom[13'h0cab] = 0; assign rom[13'h0cac] = 0; assign rom[13'h0cad] = 0; assign rom[13'h0cae] = 0; assign rom[13'h0caf] = 0; assign rom[13'h0cb0] = 0; assign rom[13'h0cb1] = 1; assign rom[13'h0cb2] = 1; assign rom[13'h0cb3] = 1; assign rom[13'h0cb4] = 1; assign rom[13'h0cb5] = 1; assign rom[13'h0cb6] = 0; assign rom[13'h0cb7] = 0; assign rom[13'h0cb8] = 0; assign rom[13'h0cb9] = 0; assign rom[13'h0cba] = 0; assign rom[13'h0cbb] = 0; assign rom[13'h0cbc] = 0; assign rom[13'h0cbd] = 0; assign rom[13'h0cbe] = 0; assign rom[13'h0cbf] = 0; assign rom[13'h0cc0] = 0; assign rom[13'h0cc1] = 1; assign rom[13'h0cc2] = 1; assign rom[13'h0cc3] = 1; assign rom[13'h0cc4] = 1; assign rom[13'h0cc5] = 1; assign rom[13'h0cc6] = 0; assign rom[13'h0cc7] = 0; assign rom[13'h0cc8] = 0; assign rom[13'h0cc9] = 0; assign rom[13'h0cca] = 0; assign rom[13'h0ccb] = 0; assign rom[13'h0ccc] = 0; assign rom[13'h0ccd] = 1; assign rom[13'h0cce] = 1; assign rom[13'h0ccf] = 0; assign rom[13'h0cd0] = 0; assign rom[13'h0cd1] = 0; assign rom[13'h0cd2] = 0; assign rom[13'h0cd3] = 0; assign rom[13'h0cd4] = 0; assign rom[13'h0cd5] = 1; assign rom[13'h0cd6] = 1; assign rom[13'h0cd7] = 0; assign rom[13'h0cd8] = 0; assign rom[13'h0cd9] = 0; assign rom[13'h0cda] = 1; assign rom[13'h0cdb] = 1; assign rom[13'h0cdc] = 1; assign rom[13'h0cdd] = 1; assign rom[13'h0cde] = 0; assign rom[13'h0cdf] = 0; assign rom[13'h0ce0] = 0; assign rom[13'h0ce1] = 0; assign rom[13'h0ce2] = 0; assign rom[13'h0ce3] = 0; assign rom[13'h0ce4] = 0; assign rom[13'h0ce5] = 1; assign rom[13'h0ce6] = 1; assign rom[13'h0ce7] = 0; assign rom[13'h0ce8] = 0; assign rom[13'h0ce9] = 0; assign rom[13'h0cea] = 0; assign rom[13'h0ceb] = 0; assign rom[13'h0cec] = 0; assign rom[13'h0ced] = 1; assign rom[13'h0cee] = 1; assign rom[13'h0cef] = 0; assign rom[13'h0cf0] = 0; assign rom[13'h0cf1] = 1; assign rom[13'h0cf2] = 1; assign rom[13'h0cf3] = 1; assign rom[13'h0cf4] = 1; assign rom[13'h0cf5] = 1; assign rom[13'h0cf6] = 0; assign rom[13'h0cf7] = 0; assign rom[13'h0cf8] = 0; assign rom[13'h0cf9] = 0; assign rom[13'h0cfa] = 0; assign rom[13'h0cfb] = 0; assign rom[13'h0cfc] = 0; assign rom[13'h0cfd] = 0; assign rom[13'h0cfe] = 0; assign rom[13'h0cff] = 0; assign rom[13'h0d00] = 0; assign rom[13'h0d01] = 1; assign rom[13'h0d02] = 1; assign rom[13'h0d03] = 0; assign rom[13'h0d04] = 0; assign rom[13'h0d05] = 1; assign rom[13'h0d06] = 1; assign rom[13'h0d07] = 0; assign rom[13'h0d08] = 0; assign rom[13'h0d09] = 1; assign rom[13'h0d0a] = 1; assign rom[13'h0d0b] = 0; assign rom[13'h0d0c] = 0; assign rom[13'h0d0d] = 1; assign rom[13'h0d0e] = 1; assign rom[13'h0d0f] = 0; assign rom[13'h0d10] = 0; assign rom[13'h0d11] = 1; assign rom[13'h0d12] = 1; assign rom[13'h0d13] = 0; assign rom[13'h0d14] = 0; assign rom[13'h0d15] = 1; assign rom[13'h0d16] = 1; assign rom[13'h0d17] = 0; assign rom[13'h0d18] = 0; assign rom[13'h0d19] = 1; assign rom[13'h0d1a] = 1; assign rom[13'h0d1b] = 1; assign rom[13'h0d1c] = 1; assign rom[13'h0d1d] = 1; assign rom[13'h0d1e] = 1; assign rom[13'h0d1f] = 0; assign rom[13'h0d20] = 0; assign rom[13'h0d21] = 0; assign rom[13'h0d22] = 0; assign rom[13'h0d23] = 0; assign rom[13'h0d24] = 0; assign rom[13'h0d25] = 1; assign rom[13'h0d26] = 1; assign rom[13'h0d27] = 0; assign rom[13'h0d28] = 0; assign rom[13'h0d29] = 0; assign rom[13'h0d2a] = 0; assign rom[13'h0d2b] = 0; assign rom[13'h0d2c] = 0; assign rom[13'h0d2d] = 1; assign rom[13'h0d2e] = 1; assign rom[13'h0d2f] = 0; assign rom[13'h0d30] = 0; assign rom[13'h0d31] = 0; assign rom[13'h0d32] = 0; assign rom[13'h0d33] = 0; assign rom[13'h0d34] = 0; assign rom[13'h0d35] = 1; assign rom[13'h0d36] = 1; assign rom[13'h0d37] = 0; assign rom[13'h0d38] = 0; assign rom[13'h0d39] = 0; assign rom[13'h0d3a] = 0; assign rom[13'h0d3b] = 0; assign rom[13'h0d3c] = 0; assign rom[13'h0d3d] = 0; assign rom[13'h0d3e] = 0; assign rom[13'h0d3f] = 0; assign rom[13'h0d40] = 0; assign rom[13'h0d41] = 1; assign rom[13'h0d42] = 1; assign rom[13'h0d43] = 1; assign rom[13'h0d44] = 1; assign rom[13'h0d45] = 1; assign rom[13'h0d46] = 1; assign rom[13'h0d47] = 0; assign rom[13'h0d48] = 0; assign rom[13'h0d49] = 1; assign rom[13'h0d4a] = 1; assign rom[13'h0d4b] = 0; assign rom[13'h0d4c] = 0; assign rom[13'h0d4d] = 0; assign rom[13'h0d4e] = 0; assign rom[13'h0d4f] = 0; assign rom[13'h0d50] = 0; assign rom[13'h0d51] = 1; assign rom[13'h0d52] = 1; assign rom[13'h0d53] = 0; assign rom[13'h0d54] = 0; assign rom[13'h0d55] = 0; assign rom[13'h0d56] = 0; assign rom[13'h0d57] = 0; assign rom[13'h0d58] = 0; assign rom[13'h0d59] = 1; assign rom[13'h0d5a] = 1; assign rom[13'h0d5b] = 1; assign rom[13'h0d5c] = 1; assign rom[13'h0d5d] = 1; assign rom[13'h0d5e] = 0; assign rom[13'h0d5f] = 0; assign rom[13'h0d60] = 0; assign rom[13'h0d61] = 0; assign rom[13'h0d62] = 0; assign rom[13'h0d63] = 0; assign rom[13'h0d64] = 0; assign rom[13'h0d65] = 1; assign rom[13'h0d66] = 1; assign rom[13'h0d67] = 0; assign rom[13'h0d68] = 0; assign rom[13'h0d69] = 0; assign rom[13'h0d6a] = 0; assign rom[13'h0d6b] = 0; assign rom[13'h0d6c] = 0; assign rom[13'h0d6d] = 1; assign rom[13'h0d6e] = 1; assign rom[13'h0d6f] = 0; assign rom[13'h0d70] = 0; assign rom[13'h0d71] = 1; assign rom[13'h0d72] = 1; assign rom[13'h0d73] = 1; assign rom[13'h0d74] = 1; assign rom[13'h0d75] = 1; assign rom[13'h0d76] = 0; assign rom[13'h0d77] = 0; assign rom[13'h0d78] = 0; assign rom[13'h0d79] = 0; assign rom[13'h0d7a] = 0; assign rom[13'h0d7b] = 0; assign rom[13'h0d7c] = 0; assign rom[13'h0d7d] = 0; assign rom[13'h0d7e] = 0; assign rom[13'h0d7f] = 0; assign rom[13'h0d80] = 0; assign rom[13'h0d81] = 0; assign rom[13'h0d82] = 1; assign rom[13'h0d83] = 1; assign rom[13'h0d84] = 1; assign rom[13'h0d85] = 1; assign rom[13'h0d86] = 0; assign rom[13'h0d87] = 0; assign rom[13'h0d88] = 0; assign rom[13'h0d89] = 1; assign rom[13'h0d8a] = 1; assign rom[13'h0d8b] = 0; assign rom[13'h0d8c] = 0; assign rom[13'h0d8d] = 0; assign rom[13'h0d8e] = 0; assign rom[13'h0d8f] = 0; assign rom[13'h0d90] = 0; assign rom[13'h0d91] = 1; assign rom[13'h0d92] = 1; assign rom[13'h0d93] = 0; assign rom[13'h0d94] = 0; assign rom[13'h0d95] = 0; assign rom[13'h0d96] = 0; assign rom[13'h0d97] = 0; assign rom[13'h0d98] = 0; assign rom[13'h0d99] = 1; assign rom[13'h0d9a] = 1; assign rom[13'h0d9b] = 1; assign rom[13'h0d9c] = 1; assign rom[13'h0d9d] = 1; assign rom[13'h0d9e] = 0; assign rom[13'h0d9f] = 0; assign rom[13'h0da0] = 0; assign rom[13'h0da1] = 1; assign rom[13'h0da2] = 1; assign rom[13'h0da3] = 0; assign rom[13'h0da4] = 0; assign rom[13'h0da5] = 1; assign rom[13'h0da6] = 1; assign rom[13'h0da7] = 0; assign rom[13'h0da8] = 0; assign rom[13'h0da9] = 1; assign rom[13'h0daa] = 1; assign rom[13'h0dab] = 0; assign rom[13'h0dac] = 0; assign rom[13'h0dad] = 1; assign rom[13'h0dae] = 1; assign rom[13'h0daf] = 0; assign rom[13'h0db0] = 0; assign rom[13'h0db1] = 0; assign rom[13'h0db2] = 1; assign rom[13'h0db3] = 1; assign rom[13'h0db4] = 1; assign rom[13'h0db5] = 1; assign rom[13'h0db6] = 0; assign rom[13'h0db7] = 0; assign rom[13'h0db8] = 0; assign rom[13'h0db9] = 0; assign rom[13'h0dba] = 0; assign rom[13'h0dbb] = 0; assign rom[13'h0dbc] = 0; assign rom[13'h0dbd] = 0; assign rom[13'h0dbe] = 0; assign rom[13'h0dbf] = 0; assign rom[13'h0dc0] = 0; assign rom[13'h0dc1] = 1; assign rom[13'h0dc2] = 1; assign rom[13'h0dc3] = 1; assign rom[13'h0dc4] = 1; assign rom[13'h0dc5] = 1; assign rom[13'h0dc6] = 1; assign rom[13'h0dc7] = 0; assign rom[13'h0dc8] = 0; assign rom[13'h0dc9] = 0; assign rom[13'h0dca] = 0; assign rom[13'h0dcb] = 0; assign rom[13'h0dcc] = 0; assign rom[13'h0dcd] = 1; assign rom[13'h0dce] = 1; assign rom[13'h0dcf] = 0; assign rom[13'h0dd0] = 0; assign rom[13'h0dd1] = 0; assign rom[13'h0dd2] = 0; assign rom[13'h0dd3] = 0; assign rom[13'h0dd4] = 1; assign rom[13'h0dd5] = 1; assign rom[13'h0dd6] = 0; assign rom[13'h0dd7] = 0; assign rom[13'h0dd8] = 0; assign rom[13'h0dd9] = 0; assign rom[13'h0dda] = 0; assign rom[13'h0ddb] = 1; assign rom[13'h0ddc] = 1; assign rom[13'h0ddd] = 0; assign rom[13'h0dde] = 0; assign rom[13'h0ddf] = 0; assign rom[13'h0de0] = 0; assign rom[13'h0de1] = 0; assign rom[13'h0de2] = 0; assign rom[13'h0de3] = 1; assign rom[13'h0de4] = 1; assign rom[13'h0de5] = 0; assign rom[13'h0de6] = 0; assign rom[13'h0de7] = 0; assign rom[13'h0de8] = 0; assign rom[13'h0de9] = 0; assign rom[13'h0dea] = 0; assign rom[13'h0deb] = 1; assign rom[13'h0dec] = 1; assign rom[13'h0ded] = 0; assign rom[13'h0dee] = 0; assign rom[13'h0def] = 0; assign rom[13'h0df0] = 0; assign rom[13'h0df1] = 0; assign rom[13'h0df2] = 0; assign rom[13'h0df3] = 1; assign rom[13'h0df4] = 1; assign rom[13'h0df5] = 0; assign rom[13'h0df6] = 0; assign rom[13'h0df7] = 0; assign rom[13'h0df8] = 0; assign rom[13'h0df9] = 0; assign rom[13'h0dfa] = 0; assign rom[13'h0dfb] = 0; assign rom[13'h0dfc] = 0; assign rom[13'h0dfd] = 0; assign rom[13'h0dfe] = 0; assign rom[13'h0dff] = 0; assign rom[13'h0e00] = 0; assign rom[13'h0e01] = 0; assign rom[13'h0e02] = 1; assign rom[13'h0e03] = 1; assign rom[13'h0e04] = 1; assign rom[13'h0e05] = 1; assign rom[13'h0e06] = 0; assign rom[13'h0e07] = 0; assign rom[13'h0e08] = 0; assign rom[13'h0e09] = 1; assign rom[13'h0e0a] = 1; assign rom[13'h0e0b] = 0; assign rom[13'h0e0c] = 0; assign rom[13'h0e0d] = 1; assign rom[13'h0e0e] = 1; assign rom[13'h0e0f] = 0; assign rom[13'h0e10] = 0; assign rom[13'h0e11] = 1; assign rom[13'h0e12] = 1; assign rom[13'h0e13] = 0; assign rom[13'h0e14] = 0; assign rom[13'h0e15] = 1; assign rom[13'h0e16] = 1; assign rom[13'h0e17] = 0; assign rom[13'h0e18] = 0; assign rom[13'h0e19] = 0; assign rom[13'h0e1a] = 1; assign rom[13'h0e1b] = 1; assign rom[13'h0e1c] = 1; assign rom[13'h0e1d] = 1; assign rom[13'h0e1e] = 0; assign rom[13'h0e1f] = 0; assign rom[13'h0e20] = 0; assign rom[13'h0e21] = 1; assign rom[13'h0e22] = 1; assign rom[13'h0e23] = 0; assign rom[13'h0e24] = 0; assign rom[13'h0e25] = 1; assign rom[13'h0e26] = 1; assign rom[13'h0e27] = 0; assign rom[13'h0e28] = 0; assign rom[13'h0e29] = 1; assign rom[13'h0e2a] = 1; assign rom[13'h0e2b] = 0; assign rom[13'h0e2c] = 0; assign rom[13'h0e2d] = 1; assign rom[13'h0e2e] = 1; assign rom[13'h0e2f] = 0; assign rom[13'h0e30] = 0; assign rom[13'h0e31] = 0; assign rom[13'h0e32] = 1; assign rom[13'h0e33] = 1; assign rom[13'h0e34] = 1; assign rom[13'h0e35] = 1; assign rom[13'h0e36] = 0; assign rom[13'h0e37] = 0; assign rom[13'h0e38] = 0; assign rom[13'h0e39] = 0; assign rom[13'h0e3a] = 0; assign rom[13'h0e3b] = 0; assign rom[13'h0e3c] = 0; assign rom[13'h0e3d] = 0; assign rom[13'h0e3e] = 0; assign rom[13'h0e3f] = 0; assign rom[13'h0e40] = 0; assign rom[13'h0e41] = 0; assign rom[13'h0e42] = 1; assign rom[13'h0e43] = 1; assign rom[13'h0e44] = 1; assign rom[13'h0e45] = 1; assign rom[13'h0e46] = 0; assign rom[13'h0e47] = 0; assign rom[13'h0e48] = 0; assign rom[13'h0e49] = 1; assign rom[13'h0e4a] = 1; assign rom[13'h0e4b] = 0; assign rom[13'h0e4c] = 0; assign rom[13'h0e4d] = 1; assign rom[13'h0e4e] = 1; assign rom[13'h0e4f] = 0; assign rom[13'h0e50] = 0; assign rom[13'h0e51] = 1; assign rom[13'h0e52] = 1; assign rom[13'h0e53] = 0; assign rom[13'h0e54] = 0; assign rom[13'h0e55] = 1; assign rom[13'h0e56] = 1; assign rom[13'h0e57] = 0; assign rom[13'h0e58] = 0; assign rom[13'h0e59] = 0; assign rom[13'h0e5a] = 1; assign rom[13'h0e5b] = 1; assign rom[13'h0e5c] = 1; assign rom[13'h0e5d] = 1; assign rom[13'h0e5e] = 1; assign rom[13'h0e5f] = 0; assign rom[13'h0e60] = 0; assign rom[13'h0e61] = 0; assign rom[13'h0e62] = 0; assign rom[13'h0e63] = 0; assign rom[13'h0e64] = 0; assign rom[13'h0e65] = 1; assign rom[13'h0e66] = 1; assign rom[13'h0e67] = 0; assign rom[13'h0e68] = 0; assign rom[13'h0e69] = 0; assign rom[13'h0e6a] = 0; assign rom[13'h0e6b] = 0; assign rom[13'h0e6c] = 0; assign rom[13'h0e6d] = 1; assign rom[13'h0e6e] = 1; assign rom[13'h0e6f] = 0; assign rom[13'h0e70] = 0; assign rom[13'h0e71] = 0; assign rom[13'h0e72] = 1; assign rom[13'h0e73] = 1; assign rom[13'h0e74] = 1; assign rom[13'h0e75] = 1; assign rom[13'h0e76] = 0; assign rom[13'h0e77] = 0; assign rom[13'h0e78] = 0; assign rom[13'h0e79] = 0; assign rom[13'h0e7a] = 0; assign rom[13'h0e7b] = 0; assign rom[13'h0e7c] = 0; assign rom[13'h0e7d] = 0; assign rom[13'h0e7e] = 0; assign rom[13'h0e7f] = 0; assign rom[13'h0e80] = 0; assign rom[13'h0e81] = 0; assign rom[13'h0e82] = 0; assign rom[13'h0e83] = 0; assign rom[13'h0e84] = 0; assign rom[13'h0e85] = 0; assign rom[13'h0e86] = 0; assign rom[13'h0e87] = 0; assign rom[13'h0e88] = 0; assign rom[13'h0e89] = 0; assign rom[13'h0e8a] = 0; assign rom[13'h0e8b] = 1; assign rom[13'h0e8c] = 1; assign rom[13'h0e8d] = 0; assign rom[13'h0e8e] = 0; assign rom[13'h0e8f] = 0; assign rom[13'h0e90] = 0; assign rom[13'h0e91] = 0; assign rom[13'h0e92] = 0; assign rom[13'h0e93] = 1; assign rom[13'h0e94] = 1; assign rom[13'h0e95] = 0; assign rom[13'h0e96] = 0; assign rom[13'h0e97] = 0; assign rom[13'h0e98] = 0; assign rom[13'h0e99] = 0; assign rom[13'h0e9a] = 0; assign rom[13'h0e9b] = 0; assign rom[13'h0e9c] = 0; assign rom[13'h0e9d] = 0; assign rom[13'h0e9e] = 0; assign rom[13'h0e9f] = 0; assign rom[13'h0ea0] = 0; assign rom[13'h0ea1] = 0; assign rom[13'h0ea2] = 0; assign rom[13'h0ea3] = 1; assign rom[13'h0ea4] = 1; assign rom[13'h0ea5] = 0; assign rom[13'h0ea6] = 0; assign rom[13'h0ea7] = 0; assign rom[13'h0ea8] = 0; assign rom[13'h0ea9] = 0; assign rom[13'h0eaa] = 0; assign rom[13'h0eab] = 1; assign rom[13'h0eac] = 1; assign rom[13'h0ead] = 0; assign rom[13'h0eae] = 0; assign rom[13'h0eaf] = 0; assign rom[13'h0eb0] = 0; assign rom[13'h0eb1] = 0; assign rom[13'h0eb2] = 0; assign rom[13'h0eb3] = 0; assign rom[13'h0eb4] = 0; assign rom[13'h0eb5] = 0; assign rom[13'h0eb6] = 0; assign rom[13'h0eb7] = 0; assign rom[13'h0eb8] = 0; assign rom[13'h0eb9] = 0; assign rom[13'h0eba] = 0; assign rom[13'h0ebb] = 0; assign rom[13'h0ebc] = 0; assign rom[13'h0ebd] = 0; assign rom[13'h0ebe] = 0; assign rom[13'h0ebf] = 0; assign rom[13'h0ec0] = 0; assign rom[13'h0ec1] = 0; assign rom[13'h0ec2] = 0; assign rom[13'h0ec3] = 0; assign rom[13'h0ec4] = 0; assign rom[13'h0ec5] = 0; assign rom[13'h0ec6] = 0; assign rom[13'h0ec7] = 0; assign rom[13'h0ec8] = 0; assign rom[13'h0ec9] = 0; assign rom[13'h0eca] = 0; assign rom[13'h0ecb] = 0; assign rom[13'h0ecc] = 0; assign rom[13'h0ecd] = 0; assign rom[13'h0ece] = 0; assign rom[13'h0ecf] = 0; assign rom[13'h0ed0] = 0; assign rom[13'h0ed1] = 0; assign rom[13'h0ed2] = 0; assign rom[13'h0ed3] = 1; assign rom[13'h0ed4] = 1; assign rom[13'h0ed5] = 0; assign rom[13'h0ed6] = 0; assign rom[13'h0ed7] = 0; assign rom[13'h0ed8] = 0; assign rom[13'h0ed9] = 0; assign rom[13'h0eda] = 0; assign rom[13'h0edb] = 1; assign rom[13'h0edc] = 1; assign rom[13'h0edd] = 0; assign rom[13'h0ede] = 0; assign rom[13'h0edf] = 0; assign rom[13'h0ee0] = 0; assign rom[13'h0ee1] = 0; assign rom[13'h0ee2] = 0; assign rom[13'h0ee3] = 0; assign rom[13'h0ee4] = 0; assign rom[13'h0ee5] = 0; assign rom[13'h0ee6] = 0; assign rom[13'h0ee7] = 0; assign rom[13'h0ee8] = 0; assign rom[13'h0ee9] = 0; assign rom[13'h0eea] = 0; assign rom[13'h0eeb] = 1; assign rom[13'h0eec] = 1; assign rom[13'h0eed] = 0; assign rom[13'h0eee] = 0; assign rom[13'h0eef] = 0; assign rom[13'h0ef0] = 0; assign rom[13'h0ef1] = 0; assign rom[13'h0ef2] = 0; assign rom[13'h0ef3] = 1; assign rom[13'h0ef4] = 1; assign rom[13'h0ef5] = 0; assign rom[13'h0ef6] = 0; assign rom[13'h0ef7] = 0; assign rom[13'h0ef8] = 0; assign rom[13'h0ef9] = 0; assign rom[13'h0efa] = 0; assign rom[13'h0efb] = 1; assign rom[13'h0efc] = 0; assign rom[13'h0efd] = 0; assign rom[13'h0efe] = 0; assign rom[13'h0eff] = 0; assign rom[13'h0f00] = 0; assign rom[13'h0f01] = 0; assign rom[13'h0f02] = 0; assign rom[13'h0f03] = 0; assign rom[13'h0f04] = 1; assign rom[13'h0f05] = 1; assign rom[13'h0f06] = 0; assign rom[13'h0f07] = 0; assign rom[13'h0f08] = 0; assign rom[13'h0f09] = 0; assign rom[13'h0f0a] = 0; assign rom[13'h0f0b] = 1; assign rom[13'h0f0c] = 1; assign rom[13'h0f0d] = 0; assign rom[13'h0f0e] = 0; assign rom[13'h0f0f] = 0; assign rom[13'h0f10] = 0; assign rom[13'h0f11] = 0; assign rom[13'h0f12] = 1; assign rom[13'h0f13] = 1; assign rom[13'h0f14] = 0; assign rom[13'h0f15] = 0; assign rom[13'h0f16] = 0; assign rom[13'h0f17] = 0; assign rom[13'h0f18] = 0; assign rom[13'h0f19] = 1; assign rom[13'h0f1a] = 1; assign rom[13'h0f1b] = 0; assign rom[13'h0f1c] = 0; assign rom[13'h0f1d] = 0; assign rom[13'h0f1e] = 0; assign rom[13'h0f1f] = 0; assign rom[13'h0f20] = 0; assign rom[13'h0f21] = 0; assign rom[13'h0f22] = 1; assign rom[13'h0f23] = 1; assign rom[13'h0f24] = 0; assign rom[13'h0f25] = 0; assign rom[13'h0f26] = 0; assign rom[13'h0f27] = 0; assign rom[13'h0f28] = 0; assign rom[13'h0f29] = 0; assign rom[13'h0f2a] = 0; assign rom[13'h0f2b] = 1; assign rom[13'h0f2c] = 1; assign rom[13'h0f2d] = 0; assign rom[13'h0f2e] = 0; assign rom[13'h0f2f] = 0; assign rom[13'h0f30] = 0; assign rom[13'h0f31] = 0; assign rom[13'h0f32] = 0; assign rom[13'h0f33] = 0; assign rom[13'h0f34] = 1; assign rom[13'h0f35] = 1; assign rom[13'h0f36] = 0; assign rom[13'h0f37] = 0; assign rom[13'h0f38] = 0; assign rom[13'h0f39] = 0; assign rom[13'h0f3a] = 0; assign rom[13'h0f3b] = 0; assign rom[13'h0f3c] = 0; assign rom[13'h0f3d] = 0; assign rom[13'h0f3e] = 0; assign rom[13'h0f3f] = 0; assign rom[13'h0f40] = 0; assign rom[13'h0f41] = 0; assign rom[13'h0f42] = 0; assign rom[13'h0f43] = 0; assign rom[13'h0f44] = 0; assign rom[13'h0f45] = 0; assign rom[13'h0f46] = 0; assign rom[13'h0f47] = 0; assign rom[13'h0f48] = 0; assign rom[13'h0f49] = 0; assign rom[13'h0f4a] = 0; assign rom[13'h0f4b] = 0; assign rom[13'h0f4c] = 0; assign rom[13'h0f4d] = 0; assign rom[13'h0f4e] = 0; assign rom[13'h0f4f] = 0; assign rom[13'h0f50] = 0; assign rom[13'h0f51] = 1; assign rom[13'h0f52] = 1; assign rom[13'h0f53] = 1; assign rom[13'h0f54] = 1; assign rom[13'h0f55] = 1; assign rom[13'h0f56] = 1; assign rom[13'h0f57] = 0; assign rom[13'h0f58] = 0; assign rom[13'h0f59] = 0; assign rom[13'h0f5a] = 0; assign rom[13'h0f5b] = 0; assign rom[13'h0f5c] = 0; assign rom[13'h0f5d] = 0; assign rom[13'h0f5e] = 0; assign rom[13'h0f5f] = 0; assign rom[13'h0f60] = 0; assign rom[13'h0f61] = 1; assign rom[13'h0f62] = 1; assign rom[13'h0f63] = 1; assign rom[13'h0f64] = 1; assign rom[13'h0f65] = 1; assign rom[13'h0f66] = 1; assign rom[13'h0f67] = 0; assign rom[13'h0f68] = 0; assign rom[13'h0f69] = 0; assign rom[13'h0f6a] = 0; assign rom[13'h0f6b] = 0; assign rom[13'h0f6c] = 0; assign rom[13'h0f6d] = 0; assign rom[13'h0f6e] = 0; assign rom[13'h0f6f] = 0; assign rom[13'h0f70] = 0; assign rom[13'h0f71] = 0; assign rom[13'h0f72] = 0; assign rom[13'h0f73] = 0; assign rom[13'h0f74] = 0; assign rom[13'h0f75] = 0; assign rom[13'h0f76] = 0; assign rom[13'h0f77] = 0; assign rom[13'h0f78] = 0; assign rom[13'h0f79] = 0; assign rom[13'h0f7a] = 0; assign rom[13'h0f7b] = 0; assign rom[13'h0f7c] = 0; assign rom[13'h0f7d] = 0; assign rom[13'h0f7e] = 0; assign rom[13'h0f7f] = 0; assign rom[13'h0f80] = 0; assign rom[13'h0f81] = 0; assign rom[13'h0f82] = 1; assign rom[13'h0f83] = 1; assign rom[13'h0f84] = 0; assign rom[13'h0f85] = 0; assign rom[13'h0f86] = 0; assign rom[13'h0f87] = 0; assign rom[13'h0f88] = 0; assign rom[13'h0f89] = 0; assign rom[13'h0f8a] = 0; assign rom[13'h0f8b] = 1; assign rom[13'h0f8c] = 1; assign rom[13'h0f8d] = 0; assign rom[13'h0f8e] = 0; assign rom[13'h0f8f] = 0; assign rom[13'h0f90] = 0; assign rom[13'h0f91] = 0; assign rom[13'h0f92] = 0; assign rom[13'h0f93] = 0; assign rom[13'h0f94] = 1; assign rom[13'h0f95] = 1; assign rom[13'h0f96] = 0; assign rom[13'h0f97] = 0; assign rom[13'h0f98] = 0; assign rom[13'h0f99] = 0; assign rom[13'h0f9a] = 0; assign rom[13'h0f9b] = 0; assign rom[13'h0f9c] = 0; assign rom[13'h0f9d] = 1; assign rom[13'h0f9e] = 1; assign rom[13'h0f9f] = 0; assign rom[13'h0fa0] = 0; assign rom[13'h0fa1] = 0; assign rom[13'h0fa2] = 0; assign rom[13'h0fa3] = 0; assign rom[13'h0fa4] = 1; assign rom[13'h0fa5] = 1; assign rom[13'h0fa6] = 0; assign rom[13'h0fa7] = 0; assign rom[13'h0fa8] = 0; assign rom[13'h0fa9] = 0; assign rom[13'h0faa] = 0; assign rom[13'h0fab] = 1; assign rom[13'h0fac] = 1; assign rom[13'h0fad] = 0; assign rom[13'h0fae] = 0; assign rom[13'h0faf] = 0; assign rom[13'h0fb0] = 0; assign rom[13'h0fb1] = 0; assign rom[13'h0fb2] = 1; assign rom[13'h0fb3] = 1; assign rom[13'h0fb4] = 0; assign rom[13'h0fb5] = 0; assign rom[13'h0fb6] = 0; assign rom[13'h0fb7] = 0; assign rom[13'h0fb8] = 0; assign rom[13'h0fb9] = 0; assign rom[13'h0fba] = 0; assign rom[13'h0fbb] = 0; assign rom[13'h0fbc] = 0; assign rom[13'h0fbd] = 0; assign rom[13'h0fbe] = 0; assign rom[13'h0fbf] = 0; assign rom[13'h0fc0] = 0; assign rom[13'h0fc1] = 0; assign rom[13'h0fc2] = 1; assign rom[13'h0fc3] = 1; assign rom[13'h0fc4] = 1; assign rom[13'h0fc5] = 1; assign rom[13'h0fc6] = 0; assign rom[13'h0fc7] = 0; assign rom[13'h0fc8] = 0; assign rom[13'h0fc9] = 1; assign rom[13'h0fca] = 1; assign rom[13'h0fcb] = 0; assign rom[13'h0fcc] = 0; assign rom[13'h0fcd] = 1; assign rom[13'h0fce] = 1; assign rom[13'h0fcf] = 0; assign rom[13'h0fd0] = 0; assign rom[13'h0fd1] = 0; assign rom[13'h0fd2] = 0; assign rom[13'h0fd3] = 0; assign rom[13'h0fd4] = 0; assign rom[13'h0fd5] = 1; assign rom[13'h0fd6] = 1; assign rom[13'h0fd7] = 0; assign rom[13'h0fd8] = 0; assign rom[13'h0fd9] = 0; assign rom[13'h0fda] = 0; assign rom[13'h0fdb] = 1; assign rom[13'h0fdc] = 1; assign rom[13'h0fdd] = 1; assign rom[13'h0fde] = 0; assign rom[13'h0fdf] = 0; assign rom[13'h0fe0] = 0; assign rom[13'h0fe1] = 0; assign rom[13'h0fe2] = 0; assign rom[13'h0fe3] = 1; assign rom[13'h0fe4] = 1; assign rom[13'h0fe5] = 0; assign rom[13'h0fe6] = 0; assign rom[13'h0fe7] = 0; assign rom[13'h0fe8] = 0; assign rom[13'h0fe9] = 0; assign rom[13'h0fea] = 0; assign rom[13'h0feb] = 0; assign rom[13'h0fec] = 0; assign rom[13'h0fed] = 0; assign rom[13'h0fee] = 0; assign rom[13'h0fef] = 0; assign rom[13'h0ff0] = 0; assign rom[13'h0ff1] = 0; assign rom[13'h0ff2] = 0; assign rom[13'h0ff3] = 1; assign rom[13'h0ff4] = 1; assign rom[13'h0ff5] = 0; assign rom[13'h0ff6] = 0; assign rom[13'h0ff7] = 0; assign rom[13'h0ff8] = 0; assign rom[13'h0ff9] = 0; assign rom[13'h0ffa] = 0; assign rom[13'h0ffb] = 0; assign rom[13'h0ffc] = 0; assign rom[13'h0ffd] = 0; assign rom[13'h0ffe] = 0; assign rom[13'h0fff] = 0; assign rom[13'h1000] = 0; assign rom[13'h1001] = 0; assign rom[13'h1002] = 1; assign rom[13'h1003] = 1; assign rom[13'h1004] = 1; assign rom[13'h1005] = 1; assign rom[13'h1006] = 0; assign rom[13'h1007] = 0; assign rom[13'h1008] = 0; assign rom[13'h1009] = 1; assign rom[13'h100a] = 1; assign rom[13'h100b] = 0; assign rom[13'h100c] = 0; assign rom[13'h100d] = 1; assign rom[13'h100e] = 1; assign rom[13'h100f] = 0; assign rom[13'h1010] = 0; assign rom[13'h1011] = 1; assign rom[13'h1012] = 1; assign rom[13'h1013] = 0; assign rom[13'h1014] = 1; assign rom[13'h1015] = 1; assign rom[13'h1016] = 1; assign rom[13'h1017] = 0; assign rom[13'h1018] = 0; assign rom[13'h1019] = 1; assign rom[13'h101a] = 1; assign rom[13'h101b] = 0; assign rom[13'h101c] = 1; assign rom[13'h101d] = 0; assign rom[13'h101e] = 1; assign rom[13'h101f] = 0; assign rom[13'h1020] = 0; assign rom[13'h1021] = 1; assign rom[13'h1022] = 1; assign rom[13'h1023] = 0; assign rom[13'h1024] = 1; assign rom[13'h1025] = 1; assign rom[13'h1026] = 1; assign rom[13'h1027] = 0; assign rom[13'h1028] = 0; assign rom[13'h1029] = 1; assign rom[13'h102a] = 1; assign rom[13'h102b] = 0; assign rom[13'h102c] = 0; assign rom[13'h102d] = 0; assign rom[13'h102e] = 0; assign rom[13'h102f] = 0; assign rom[13'h1030] = 0; assign rom[13'h1031] = 0; assign rom[13'h1032] = 1; assign rom[13'h1033] = 1; assign rom[13'h1034] = 1; assign rom[13'h1035] = 1; assign rom[13'h1036] = 1; assign rom[13'h1037] = 0; assign rom[13'h1038] = 0; assign rom[13'h1039] = 0; assign rom[13'h103a] = 0; assign rom[13'h103b] = 0; assign rom[13'h103c] = 0; assign rom[13'h103d] = 0; assign rom[13'h103e] = 0; assign rom[13'h103f] = 0; assign rom[13'h1040] = 0; assign rom[13'h1041] = 0; assign rom[13'h1042] = 1; assign rom[13'h1043] = 1; assign rom[13'h1044] = 1; assign rom[13'h1045] = 1; assign rom[13'h1046] = 0; assign rom[13'h1047] = 0; assign rom[13'h1048] = 0; assign rom[13'h1049] = 1; assign rom[13'h104a] = 1; assign rom[13'h104b] = 0; assign rom[13'h104c] = 0; assign rom[13'h104d] = 1; assign rom[13'h104e] = 1; assign rom[13'h104f] = 0; assign rom[13'h1050] = 0; assign rom[13'h1051] = 1; assign rom[13'h1052] = 1; assign rom[13'h1053] = 0; assign rom[13'h1054] = 0; assign rom[13'h1055] = 1; assign rom[13'h1056] = 1; assign rom[13'h1057] = 0; assign rom[13'h1058] = 0; assign rom[13'h1059] = 1; assign rom[13'h105a] = 1; assign rom[13'h105b] = 1; assign rom[13'h105c] = 1; assign rom[13'h105d] = 1; assign rom[13'h105e] = 1; assign rom[13'h105f] = 0; assign rom[13'h1060] = 0; assign rom[13'h1061] = 1; assign rom[13'h1062] = 1; assign rom[13'h1063] = 0; assign rom[13'h1064] = 0; assign rom[13'h1065] = 1; assign rom[13'h1066] = 1; assign rom[13'h1067] = 0; assign rom[13'h1068] = 0; assign rom[13'h1069] = 1; assign rom[13'h106a] = 1; assign rom[13'h106b] = 0; assign rom[13'h106c] = 0; assign rom[13'h106d] = 1; assign rom[13'h106e] = 1; assign rom[13'h106f] = 0; assign rom[13'h1070] = 0; assign rom[13'h1071] = 1; assign rom[13'h1072] = 1; assign rom[13'h1073] = 0; assign rom[13'h1074] = 0; assign rom[13'h1075] = 1; assign rom[13'h1076] = 1; assign rom[13'h1077] = 0; assign rom[13'h1078] = 0; assign rom[13'h1079] = 0; assign rom[13'h107a] = 0; assign rom[13'h107b] = 0; assign rom[13'h107c] = 0; assign rom[13'h107d] = 0; assign rom[13'h107e] = 0; assign rom[13'h107f] = 0; assign rom[13'h1080] = 0; assign rom[13'h1081] = 1; assign rom[13'h1082] = 1; assign rom[13'h1083] = 1; assign rom[13'h1084] = 1; assign rom[13'h1085] = 1; assign rom[13'h1086] = 0; assign rom[13'h1087] = 0; assign rom[13'h1088] = 0; assign rom[13'h1089] = 1; assign rom[13'h108a] = 1; assign rom[13'h108b] = 0; assign rom[13'h108c] = 0; assign rom[13'h108d] = 1; assign rom[13'h108e] = 1; assign rom[13'h108f] = 0; assign rom[13'h1090] = 0; assign rom[13'h1091] = 1; assign rom[13'h1092] = 1; assign rom[13'h1093] = 0; assign rom[13'h1094] = 0; assign rom[13'h1095] = 1; assign rom[13'h1096] = 1; assign rom[13'h1097] = 0; assign rom[13'h1098] = 0; assign rom[13'h1099] = 1; assign rom[13'h109a] = 1; assign rom[13'h109b] = 1; assign rom[13'h109c] = 1; assign rom[13'h109d] = 1; assign rom[13'h109e] = 0; assign rom[13'h109f] = 0; assign rom[13'h10a0] = 0; assign rom[13'h10a1] = 1; assign rom[13'h10a2] = 1; assign rom[13'h10a3] = 0; assign rom[13'h10a4] = 0; assign rom[13'h10a5] = 1; assign rom[13'h10a6] = 1; assign rom[13'h10a7] = 0; assign rom[13'h10a8] = 0; assign rom[13'h10a9] = 1; assign rom[13'h10aa] = 1; assign rom[13'h10ab] = 0; assign rom[13'h10ac] = 0; assign rom[13'h10ad] = 1; assign rom[13'h10ae] = 1; assign rom[13'h10af] = 0; assign rom[13'h10b0] = 0; assign rom[13'h10b1] = 1; assign rom[13'h10b2] = 1; assign rom[13'h10b3] = 1; assign rom[13'h10b4] = 1; assign rom[13'h10b5] = 1; assign rom[13'h10b6] = 0; assign rom[13'h10b7] = 0; assign rom[13'h10b8] = 0; assign rom[13'h10b9] = 0; assign rom[13'h10ba] = 0; assign rom[13'h10bb] = 0; assign rom[13'h10bc] = 0; assign rom[13'h10bd] = 0; assign rom[13'h10be] = 0; assign rom[13'h10bf] = 0; assign rom[13'h10c0] = 0; assign rom[13'h10c1] = 0; assign rom[13'h10c2] = 1; assign rom[13'h10c3] = 1; assign rom[13'h10c4] = 1; assign rom[13'h10c5] = 1; assign rom[13'h10c6] = 0; assign rom[13'h10c7] = 0; assign rom[13'h10c8] = 0; assign rom[13'h10c9] = 1; assign rom[13'h10ca] = 1; assign rom[13'h10cb] = 0; assign rom[13'h10cc] = 0; assign rom[13'h10cd] = 1; assign rom[13'h10ce] = 1; assign rom[13'h10cf] = 0; assign rom[13'h10d0] = 0; assign rom[13'h10d1] = 1; assign rom[13'h10d2] = 1; assign rom[13'h10d3] = 0; assign rom[13'h10d4] = 0; assign rom[13'h10d5] = 0; assign rom[13'h10d6] = 0; assign rom[13'h10d7] = 0; assign rom[13'h10d8] = 0; assign rom[13'h10d9] = 1; assign rom[13'h10da] = 1; assign rom[13'h10db] = 0; assign rom[13'h10dc] = 0; assign rom[13'h10dd] = 0; assign rom[13'h10de] = 0; assign rom[13'h10df] = 0; assign rom[13'h10e0] = 0; assign rom[13'h10e1] = 1; assign rom[13'h10e2] = 1; assign rom[13'h10e3] = 0; assign rom[13'h10e4] = 0; assign rom[13'h10e5] = 0; assign rom[13'h10e6] = 0; assign rom[13'h10e7] = 0; assign rom[13'h10e8] = 0; assign rom[13'h10e9] = 1; assign rom[13'h10ea] = 1; assign rom[13'h10eb] = 0; assign rom[13'h10ec] = 0; assign rom[13'h10ed] = 1; assign rom[13'h10ee] = 1; assign rom[13'h10ef] = 0; assign rom[13'h10f0] = 0; assign rom[13'h10f1] = 0; assign rom[13'h10f2] = 1; assign rom[13'h10f3] = 1; assign rom[13'h10f4] = 1; assign rom[13'h10f5] = 1; assign rom[13'h10f6] = 0; assign rom[13'h10f7] = 0; assign rom[13'h10f8] = 0; assign rom[13'h10f9] = 0; assign rom[13'h10fa] = 0; assign rom[13'h10fb] = 0; assign rom[13'h10fc] = 0; assign rom[13'h10fd] = 0; assign rom[13'h10fe] = 0; assign rom[13'h10ff] = 0; assign rom[13'h1100] = 0; assign rom[13'h1101] = 1; assign rom[13'h1102] = 1; assign rom[13'h1103] = 1; assign rom[13'h1104] = 1; assign rom[13'h1105] = 1; assign rom[13'h1106] = 0; assign rom[13'h1107] = 0; assign rom[13'h1108] = 0; assign rom[13'h1109] = 1; assign rom[13'h110a] = 1; assign rom[13'h110b] = 0; assign rom[13'h110c] = 0; assign rom[13'h110d] = 1; assign rom[13'h110e] = 1; assign rom[13'h110f] = 0; assign rom[13'h1110] = 0; assign rom[13'h1111] = 1; assign rom[13'h1112] = 1; assign rom[13'h1113] = 0; assign rom[13'h1114] = 0; assign rom[13'h1115] = 1; assign rom[13'h1116] = 1; assign rom[13'h1117] = 0; assign rom[13'h1118] = 0; assign rom[13'h1119] = 1; assign rom[13'h111a] = 1; assign rom[13'h111b] = 0; assign rom[13'h111c] = 0; assign rom[13'h111d] = 1; assign rom[13'h111e] = 1; assign rom[13'h111f] = 0; assign rom[13'h1120] = 0; assign rom[13'h1121] = 1; assign rom[13'h1122] = 1; assign rom[13'h1123] = 0; assign rom[13'h1124] = 0; assign rom[13'h1125] = 1; assign rom[13'h1126] = 1; assign rom[13'h1127] = 0; assign rom[13'h1128] = 0; assign rom[13'h1129] = 1; assign rom[13'h112a] = 1; assign rom[13'h112b] = 0; assign rom[13'h112c] = 0; assign rom[13'h112d] = 1; assign rom[13'h112e] = 1; assign rom[13'h112f] = 0; assign rom[13'h1130] = 0; assign rom[13'h1131] = 1; assign rom[13'h1132] = 1; assign rom[13'h1133] = 1; assign rom[13'h1134] = 1; assign rom[13'h1135] = 1; assign rom[13'h1136] = 0; assign rom[13'h1137] = 0; assign rom[13'h1138] = 0; assign rom[13'h1139] = 0; assign rom[13'h113a] = 0; assign rom[13'h113b] = 0; assign rom[13'h113c] = 0; assign rom[13'h113d] = 0; assign rom[13'h113e] = 0; assign rom[13'h113f] = 0; assign rom[13'h1140] = 0; assign rom[13'h1141] = 1; assign rom[13'h1142] = 1; assign rom[13'h1143] = 1; assign rom[13'h1144] = 1; assign rom[13'h1145] = 1; assign rom[13'h1146] = 1; assign rom[13'h1147] = 0; assign rom[13'h1148] = 0; assign rom[13'h1149] = 1; assign rom[13'h114a] = 1; assign rom[13'h114b] = 0; assign rom[13'h114c] = 0; assign rom[13'h114d] = 0; assign rom[13'h114e] = 0; assign rom[13'h114f] = 0; assign rom[13'h1150] = 0; assign rom[13'h1151] = 1; assign rom[13'h1152] = 1; assign rom[13'h1153] = 0; assign rom[13'h1154] = 0; assign rom[13'h1155] = 0; assign rom[13'h1156] = 0; assign rom[13'h1157] = 0; assign rom[13'h1158] = 0; assign rom[13'h1159] = 1; assign rom[13'h115a] = 1; assign rom[13'h115b] = 1; assign rom[13'h115c] = 1; assign rom[13'h115d] = 1; assign rom[13'h115e] = 0; assign rom[13'h115f] = 0; assign rom[13'h1160] = 0; assign rom[13'h1161] = 1; assign rom[13'h1162] = 1; assign rom[13'h1163] = 0; assign rom[13'h1164] = 0; assign rom[13'h1165] = 0; assign rom[13'h1166] = 0; assign rom[13'h1167] = 0; assign rom[13'h1168] = 0; assign rom[13'h1169] = 1; assign rom[13'h116a] = 1; assign rom[13'h116b] = 0; assign rom[13'h116c] = 0; assign rom[13'h116d] = 0; assign rom[13'h116e] = 0; assign rom[13'h116f] = 0; assign rom[13'h1170] = 0; assign rom[13'h1171] = 1; assign rom[13'h1172] = 1; assign rom[13'h1173] = 1; assign rom[13'h1174] = 1; assign rom[13'h1175] = 1; assign rom[13'h1176] = 1; assign rom[13'h1177] = 0; assign rom[13'h1178] = 0; assign rom[13'h1179] = 0; assign rom[13'h117a] = 0; assign rom[13'h117b] = 0; assign rom[13'h117c] = 0; assign rom[13'h117d] = 0; assign rom[13'h117e] = 0; assign rom[13'h117f] = 0; assign rom[13'h1180] = 0; assign rom[13'h1181] = 1; assign rom[13'h1182] = 1; assign rom[13'h1183] = 1; assign rom[13'h1184] = 1; assign rom[13'h1185] = 1; assign rom[13'h1186] = 1; assign rom[13'h1187] = 0; assign rom[13'h1188] = 0; assign rom[13'h1189] = 1; assign rom[13'h118a] = 1; assign rom[13'h118b] = 0; assign rom[13'h118c] = 0; assign rom[13'h118d] = 0; assign rom[13'h118e] = 0; assign rom[13'h118f] = 0; assign rom[13'h1190] = 0; assign rom[13'h1191] = 1; assign rom[13'h1192] = 1; assign rom[13'h1193] = 0; assign rom[13'h1194] = 0; assign rom[13'h1195] = 0; assign rom[13'h1196] = 0; assign rom[13'h1197] = 0; assign rom[13'h1198] = 0; assign rom[13'h1199] = 1; assign rom[13'h119a] = 1; assign rom[13'h119b] = 1; assign rom[13'h119c] = 1; assign rom[13'h119d] = 1; assign rom[13'h119e] = 0; assign rom[13'h119f] = 0; assign rom[13'h11a0] = 0; assign rom[13'h11a1] = 1; assign rom[13'h11a2] = 1; assign rom[13'h11a3] = 0; assign rom[13'h11a4] = 0; assign rom[13'h11a5] = 0; assign rom[13'h11a6] = 0; assign rom[13'h11a7] = 0; assign rom[13'h11a8] = 0; assign rom[13'h11a9] = 1; assign rom[13'h11aa] = 1; assign rom[13'h11ab] = 0; assign rom[13'h11ac] = 0; assign rom[13'h11ad] = 0; assign rom[13'h11ae] = 0; assign rom[13'h11af] = 0; assign rom[13'h11b0] = 0; assign rom[13'h11b1] = 1; assign rom[13'h11b2] = 1; assign rom[13'h11b3] = 0; assign rom[13'h11b4] = 0; assign rom[13'h11b5] = 0; assign rom[13'h11b6] = 0; assign rom[13'h11b7] = 0; assign rom[13'h11b8] = 0; assign rom[13'h11b9] = 0; assign rom[13'h11ba] = 0; assign rom[13'h11bb] = 0; assign rom[13'h11bc] = 0; assign rom[13'h11bd] = 0; assign rom[13'h11be] = 0; assign rom[13'h11bf] = 0; assign rom[13'h11c0] = 0; assign rom[13'h11c1] = 0; assign rom[13'h11c2] = 1; assign rom[13'h11c3] = 1; assign rom[13'h11c4] = 1; assign rom[13'h11c5] = 1; assign rom[13'h11c6] = 0; assign rom[13'h11c7] = 0; assign rom[13'h11c8] = 0; assign rom[13'h11c9] = 1; assign rom[13'h11ca] = 1; assign rom[13'h11cb] = 0; assign rom[13'h11cc] = 0; assign rom[13'h11cd] = 1; assign rom[13'h11ce] = 1; assign rom[13'h11cf] = 0; assign rom[13'h11d0] = 0; assign rom[13'h11d1] = 1; assign rom[13'h11d2] = 1; assign rom[13'h11d3] = 0; assign rom[13'h11d4] = 0; assign rom[13'h11d5] = 0; assign rom[13'h11d6] = 0; assign rom[13'h11d7] = 0; assign rom[13'h11d8] = 0; assign rom[13'h11d9] = 1; assign rom[13'h11da] = 1; assign rom[13'h11db] = 0; assign rom[13'h11dc] = 1; assign rom[13'h11dd] = 1; assign rom[13'h11de] = 1; assign rom[13'h11df] = 0; assign rom[13'h11e0] = 0; assign rom[13'h11e1] = 1; assign rom[13'h11e2] = 1; assign rom[13'h11e3] = 0; assign rom[13'h11e4] = 0; assign rom[13'h11e5] = 1; assign rom[13'h11e6] = 1; assign rom[13'h11e7] = 0; assign rom[13'h11e8] = 0; assign rom[13'h11e9] = 1; assign rom[13'h11ea] = 1; assign rom[13'h11eb] = 0; assign rom[13'h11ec] = 0; assign rom[13'h11ed] = 1; assign rom[13'h11ee] = 1; assign rom[13'h11ef] = 0; assign rom[13'h11f0] = 0; assign rom[13'h11f1] = 0; assign rom[13'h11f2] = 1; assign rom[13'h11f3] = 1; assign rom[13'h11f4] = 1; assign rom[13'h11f5] = 1; assign rom[13'h11f6] = 0; assign rom[13'h11f7] = 0; assign rom[13'h11f8] = 0; assign rom[13'h11f9] = 0; assign rom[13'h11fa] = 0; assign rom[13'h11fb] = 0; assign rom[13'h11fc] = 0; assign rom[13'h11fd] = 0; assign rom[13'h11fe] = 0; assign rom[13'h11ff] = 0; assign rom[13'h1200] = 0; assign rom[13'h1201] = 1; assign rom[13'h1202] = 1; assign rom[13'h1203] = 0; assign rom[13'h1204] = 0; assign rom[13'h1205] = 1; assign rom[13'h1206] = 1; assign rom[13'h1207] = 0; assign rom[13'h1208] = 0; assign rom[13'h1209] = 1; assign rom[13'h120a] = 1; assign rom[13'h120b] = 0; assign rom[13'h120c] = 0; assign rom[13'h120d] = 1; assign rom[13'h120e] = 1; assign rom[13'h120f] = 0; assign rom[13'h1210] = 0; assign rom[13'h1211] = 1; assign rom[13'h1212] = 1; assign rom[13'h1213] = 0; assign rom[13'h1214] = 0; assign rom[13'h1215] = 1; assign rom[13'h1216] = 1; assign rom[13'h1217] = 0; assign rom[13'h1218] = 0; assign rom[13'h1219] = 1; assign rom[13'h121a] = 1; assign rom[13'h121b] = 1; assign rom[13'h121c] = 1; assign rom[13'h121d] = 1; assign rom[13'h121e] = 1; assign rom[13'h121f] = 0; assign rom[13'h1220] = 0; assign rom[13'h1221] = 1; assign rom[13'h1222] = 1; assign rom[13'h1223] = 0; assign rom[13'h1224] = 0; assign rom[13'h1225] = 1; assign rom[13'h1226] = 1; assign rom[13'h1227] = 0; assign rom[13'h1228] = 0; assign rom[13'h1229] = 1; assign rom[13'h122a] = 1; assign rom[13'h122b] = 0; assign rom[13'h122c] = 0; assign rom[13'h122d] = 1; assign rom[13'h122e] = 1; assign rom[13'h122f] = 0; assign rom[13'h1230] = 0; assign rom[13'h1231] = 1; assign rom[13'h1232] = 1; assign rom[13'h1233] = 0; assign rom[13'h1234] = 0; assign rom[13'h1235] = 1; assign rom[13'h1236] = 1; assign rom[13'h1237] = 0; assign rom[13'h1238] = 0; assign rom[13'h1239] = 0; assign rom[13'h123a] = 0; assign rom[13'h123b] = 0; assign rom[13'h123c] = 0; assign rom[13'h123d] = 0; assign rom[13'h123e] = 0; assign rom[13'h123f] = 0; assign rom[13'h1240] = 0; assign rom[13'h1241] = 0; assign rom[13'h1242] = 1; assign rom[13'h1243] = 1; assign rom[13'h1244] = 1; assign rom[13'h1245] = 1; assign rom[13'h1246] = 0; assign rom[13'h1247] = 0; assign rom[13'h1248] = 0; assign rom[13'h1249] = 0; assign rom[13'h124a] = 0; assign rom[13'h124b] = 1; assign rom[13'h124c] = 1; assign rom[13'h124d] = 0; assign rom[13'h124e] = 0; assign rom[13'h124f] = 0; assign rom[13'h1250] = 0; assign rom[13'h1251] = 0; assign rom[13'h1252] = 0; assign rom[13'h1253] = 1; assign rom[13'h1254] = 1; assign rom[13'h1255] = 0; assign rom[13'h1256] = 0; assign rom[13'h1257] = 0; assign rom[13'h1258] = 0; assign rom[13'h1259] = 0; assign rom[13'h125a] = 0; assign rom[13'h125b] = 1; assign rom[13'h125c] = 1; assign rom[13'h125d] = 0; assign rom[13'h125e] = 0; assign rom[13'h125f] = 0; assign rom[13'h1260] = 0; assign rom[13'h1261] = 0; assign rom[13'h1262] = 0; assign rom[13'h1263] = 1; assign rom[13'h1264] = 1; assign rom[13'h1265] = 0; assign rom[13'h1266] = 0; assign rom[13'h1267] = 0; assign rom[13'h1268] = 0; assign rom[13'h1269] = 0; assign rom[13'h126a] = 0; assign rom[13'h126b] = 1; assign rom[13'h126c] = 1; assign rom[13'h126d] = 0; assign rom[13'h126e] = 0; assign rom[13'h126f] = 0; assign rom[13'h1270] = 0; assign rom[13'h1271] = 0; assign rom[13'h1272] = 1; assign rom[13'h1273] = 1; assign rom[13'h1274] = 1; assign rom[13'h1275] = 1; assign rom[13'h1276] = 0; assign rom[13'h1277] = 0; assign rom[13'h1278] = 0; assign rom[13'h1279] = 0; assign rom[13'h127a] = 0; assign rom[13'h127b] = 0; assign rom[13'h127c] = 0; assign rom[13'h127d] = 0; assign rom[13'h127e] = 0; assign rom[13'h127f] = 0; assign rom[13'h1280] = 0; assign rom[13'h1281] = 0; assign rom[13'h1282] = 1; assign rom[13'h1283] = 1; assign rom[13'h1284] = 1; assign rom[13'h1285] = 1; assign rom[13'h1286] = 1; assign rom[13'h1287] = 0; assign rom[13'h1288] = 0; assign rom[13'h1289] = 0; assign rom[13'h128a] = 0; assign rom[13'h128b] = 0; assign rom[13'h128c] = 1; assign rom[13'h128d] = 1; assign rom[13'h128e] = 0; assign rom[13'h128f] = 0; assign rom[13'h1290] = 0; assign rom[13'h1291] = 0; assign rom[13'h1292] = 0; assign rom[13'h1293] = 0; assign rom[13'h1294] = 1; assign rom[13'h1295] = 1; assign rom[13'h1296] = 0; assign rom[13'h1297] = 0; assign rom[13'h1298] = 0; assign rom[13'h1299] = 0; assign rom[13'h129a] = 0; assign rom[13'h129b] = 0; assign rom[13'h129c] = 1; assign rom[13'h129d] = 1; assign rom[13'h129e] = 0; assign rom[13'h129f] = 0; assign rom[13'h12a0] = 0; assign rom[13'h12a1] = 0; assign rom[13'h12a2] = 0; assign rom[13'h12a3] = 0; assign rom[13'h12a4] = 1; assign rom[13'h12a5] = 1; assign rom[13'h12a6] = 0; assign rom[13'h12a7] = 0; assign rom[13'h12a8] = 0; assign rom[13'h12a9] = 1; assign rom[13'h12aa] = 1; assign rom[13'h12ab] = 0; assign rom[13'h12ac] = 1; assign rom[13'h12ad] = 1; assign rom[13'h12ae] = 0; assign rom[13'h12af] = 0; assign rom[13'h12b0] = 0; assign rom[13'h12b1] = 0; assign rom[13'h12b2] = 1; assign rom[13'h12b3] = 1; assign rom[13'h12b4] = 1; assign rom[13'h12b5] = 0; assign rom[13'h12b6] = 0; assign rom[13'h12b7] = 0; assign rom[13'h12b8] = 0; assign rom[13'h12b9] = 0; assign rom[13'h12ba] = 0; assign rom[13'h12bb] = 0; assign rom[13'h12bc] = 0; assign rom[13'h12bd] = 0; assign rom[13'h12be] = 0; assign rom[13'h12bf] = 0; assign rom[13'h12c0] = 0; assign rom[13'h12c1] = 1; assign rom[13'h12c2] = 1; assign rom[13'h12c3] = 0; assign rom[13'h12c4] = 0; assign rom[13'h12c5] = 1; assign rom[13'h12c6] = 1; assign rom[13'h12c7] = 0; assign rom[13'h12c8] = 0; assign rom[13'h12c9] = 1; assign rom[13'h12ca] = 1; assign rom[13'h12cb] = 0; assign rom[13'h12cc] = 1; assign rom[13'h12cd] = 1; assign rom[13'h12ce] = 0; assign rom[13'h12cf] = 0; assign rom[13'h12d0] = 0; assign rom[13'h12d1] = 1; assign rom[13'h12d2] = 1; assign rom[13'h12d3] = 1; assign rom[13'h12d4] = 1; assign rom[13'h12d5] = 0; assign rom[13'h12d6] = 0; assign rom[13'h12d7] = 0; assign rom[13'h12d8] = 0; assign rom[13'h12d9] = 1; assign rom[13'h12da] = 1; assign rom[13'h12db] = 1; assign rom[13'h12dc] = 0; assign rom[13'h12dd] = 0; assign rom[13'h12de] = 0; assign rom[13'h12df] = 0; assign rom[13'h12e0] = 0; assign rom[13'h12e1] = 1; assign rom[13'h12e2] = 1; assign rom[13'h12e3] = 1; assign rom[13'h12e4] = 1; assign rom[13'h12e5] = 0; assign rom[13'h12e6] = 0; assign rom[13'h12e7] = 0; assign rom[13'h12e8] = 0; assign rom[13'h12e9] = 1; assign rom[13'h12ea] = 1; assign rom[13'h12eb] = 0; assign rom[13'h12ec] = 1; assign rom[13'h12ed] = 1; assign rom[13'h12ee] = 0; assign rom[13'h12ef] = 0; assign rom[13'h12f0] = 0; assign rom[13'h12f1] = 1; assign rom[13'h12f2] = 1; assign rom[13'h12f3] = 0; assign rom[13'h12f4] = 0; assign rom[13'h12f5] = 1; assign rom[13'h12f6] = 1; assign rom[13'h12f7] = 0; assign rom[13'h12f8] = 0; assign rom[13'h12f9] = 0; assign rom[13'h12fa] = 0; assign rom[13'h12fb] = 0; assign rom[13'h12fc] = 0; assign rom[13'h12fd] = 0; assign rom[13'h12fe] = 0; assign rom[13'h12ff] = 0; assign rom[13'h1300] = 0; assign rom[13'h1301] = 1; assign rom[13'h1302] = 1; assign rom[13'h1303] = 0; assign rom[13'h1304] = 0; assign rom[13'h1305] = 0; assign rom[13'h1306] = 0; assign rom[13'h1307] = 0; assign rom[13'h1308] = 0; assign rom[13'h1309] = 1; assign rom[13'h130a] = 1; assign rom[13'h130b] = 0; assign rom[13'h130c] = 0; assign rom[13'h130d] = 0; assign rom[13'h130e] = 0; assign rom[13'h130f] = 0; assign rom[13'h1310] = 0; assign rom[13'h1311] = 1; assign rom[13'h1312] = 1; assign rom[13'h1313] = 0; assign rom[13'h1314] = 0; assign rom[13'h1315] = 0; assign rom[13'h1316] = 0; assign rom[13'h1317] = 0; assign rom[13'h1318] = 0; assign rom[13'h1319] = 1; assign rom[13'h131a] = 1; assign rom[13'h131b] = 0; assign rom[13'h131c] = 0; assign rom[13'h131d] = 0; assign rom[13'h131e] = 0; assign rom[13'h131f] = 0; assign rom[13'h1320] = 0; assign rom[13'h1321] = 1; assign rom[13'h1322] = 1; assign rom[13'h1323] = 0; assign rom[13'h1324] = 0; assign rom[13'h1325] = 0; assign rom[13'h1326] = 0; assign rom[13'h1327] = 0; assign rom[13'h1328] = 0; assign rom[13'h1329] = 1; assign rom[13'h132a] = 1; assign rom[13'h132b] = 0; assign rom[13'h132c] = 0; assign rom[13'h132d] = 0; assign rom[13'h132e] = 0; assign rom[13'h132f] = 0; assign rom[13'h1330] = 0; assign rom[13'h1331] = 1; assign rom[13'h1332] = 1; assign rom[13'h1333] = 1; assign rom[13'h1334] = 1; assign rom[13'h1335] = 1; assign rom[13'h1336] = 1; assign rom[13'h1337] = 0; assign rom[13'h1338] = 0; assign rom[13'h1339] = 0; assign rom[13'h133a] = 0; assign rom[13'h133b] = 0; assign rom[13'h133c] = 0; assign rom[13'h133d] = 0; assign rom[13'h133e] = 0; assign rom[13'h133f] = 0; assign rom[13'h1340] = 1; assign rom[13'h1341] = 1; assign rom[13'h1342] = 0; assign rom[13'h1343] = 0; assign rom[13'h1344] = 0; assign rom[13'h1345] = 1; assign rom[13'h1346] = 1; assign rom[13'h1347] = 0; assign rom[13'h1348] = 1; assign rom[13'h1349] = 1; assign rom[13'h134a] = 1; assign rom[13'h134b] = 0; assign rom[13'h134c] = 1; assign rom[13'h134d] = 1; assign rom[13'h134e] = 1; assign rom[13'h134f] = 0; assign rom[13'h1350] = 1; assign rom[13'h1351] = 1; assign rom[13'h1352] = 1; assign rom[13'h1353] = 1; assign rom[13'h1354] = 1; assign rom[13'h1355] = 1; assign rom[13'h1356] = 1; assign rom[13'h1357] = 0; assign rom[13'h1358] = 1; assign rom[13'h1359] = 1; assign rom[13'h135a] = 0; assign rom[13'h135b] = 1; assign rom[13'h135c] = 0; assign rom[13'h135d] = 1; assign rom[13'h135e] = 1; assign rom[13'h135f] = 0; assign rom[13'h1360] = 1; assign rom[13'h1361] = 1; assign rom[13'h1362] = 0; assign rom[13'h1363] = 0; assign rom[13'h1364] = 0; assign rom[13'h1365] = 1; assign rom[13'h1366] = 1; assign rom[13'h1367] = 0; assign rom[13'h1368] = 1; assign rom[13'h1369] = 1; assign rom[13'h136a] = 0; assign rom[13'h136b] = 0; assign rom[13'h136c] = 0; assign rom[13'h136d] = 1; assign rom[13'h136e] = 1; assign rom[13'h136f] = 0; assign rom[13'h1370] = 1; assign rom[13'h1371] = 1; assign rom[13'h1372] = 0; assign rom[13'h1373] = 0; assign rom[13'h1374] = 0; assign rom[13'h1375] = 1; assign rom[13'h1376] = 1; assign rom[13'h1377] = 0; assign rom[13'h1378] = 0; assign rom[13'h1379] = 0; assign rom[13'h137a] = 0; assign rom[13'h137b] = 0; assign rom[13'h137c] = 0; assign rom[13'h137d] = 0; assign rom[13'h137e] = 0; assign rom[13'h137f] = 0; assign rom[13'h1380] = 0; assign rom[13'h1381] = 1; assign rom[13'h1382] = 1; assign rom[13'h1383] = 0; assign rom[13'h1384] = 0; assign rom[13'h1385] = 1; assign rom[13'h1386] = 1; assign rom[13'h1387] = 0; assign rom[13'h1388] = 0; assign rom[13'h1389] = 1; assign rom[13'h138a] = 1; assign rom[13'h138b] = 0; assign rom[13'h138c] = 0; assign rom[13'h138d] = 1; assign rom[13'h138e] = 1; assign rom[13'h138f] = 0; assign rom[13'h1390] = 0; assign rom[13'h1391] = 1; assign rom[13'h1392] = 1; assign rom[13'h1393] = 1; assign rom[13'h1394] = 0; assign rom[13'h1395] = 1; assign rom[13'h1396] = 1; assign rom[13'h1397] = 0; assign rom[13'h1398] = 0; assign rom[13'h1399] = 1; assign rom[13'h139a] = 1; assign rom[13'h139b] = 1; assign rom[13'h139c] = 1; assign rom[13'h139d] = 1; assign rom[13'h139e] = 1; assign rom[13'h139f] = 0; assign rom[13'h13a0] = 0; assign rom[13'h13a1] = 1; assign rom[13'h13a2] = 1; assign rom[13'h13a3] = 0; assign rom[13'h13a4] = 1; assign rom[13'h13a5] = 1; assign rom[13'h13a6] = 1; assign rom[13'h13a7] = 0; assign rom[13'h13a8] = 0; assign rom[13'h13a9] = 1; assign rom[13'h13aa] = 1; assign rom[13'h13ab] = 0; assign rom[13'h13ac] = 0; assign rom[13'h13ad] = 1; assign rom[13'h13ae] = 1; assign rom[13'h13af] = 0; assign rom[13'h13b0] = 0; assign rom[13'h13b1] = 1; assign rom[13'h13b2] = 1; assign rom[13'h13b3] = 0; assign rom[13'h13b4] = 0; assign rom[13'h13b5] = 1; assign rom[13'h13b6] = 1; assign rom[13'h13b7] = 0; assign rom[13'h13b8] = 0; assign rom[13'h13b9] = 0; assign rom[13'h13ba] = 0; assign rom[13'h13bb] = 0; assign rom[13'h13bc] = 0; assign rom[13'h13bd] = 0; assign rom[13'h13be] = 0; assign rom[13'h13bf] = 0; assign rom[13'h13c0] = 0; assign rom[13'h13c1] = 0; assign rom[13'h13c2] = 1; assign rom[13'h13c3] = 1; assign rom[13'h13c4] = 1; assign rom[13'h13c5] = 1; assign rom[13'h13c6] = 0; assign rom[13'h13c7] = 0; assign rom[13'h13c8] = 0; assign rom[13'h13c9] = 1; assign rom[13'h13ca] = 1; assign rom[13'h13cb] = 0; assign rom[13'h13cc] = 0; assign rom[13'h13cd] = 1; assign rom[13'h13ce] = 1; assign rom[13'h13cf] = 0; assign rom[13'h13d0] = 0; assign rom[13'h13d1] = 1; assign rom[13'h13d2] = 1; assign rom[13'h13d3] = 0; assign rom[13'h13d4] = 0; assign rom[13'h13d5] = 1; assign rom[13'h13d6] = 1; assign rom[13'h13d7] = 0; assign rom[13'h13d8] = 0; assign rom[13'h13d9] = 1; assign rom[13'h13da] = 1; assign rom[13'h13db] = 0; assign rom[13'h13dc] = 0; assign rom[13'h13dd] = 1; assign rom[13'h13de] = 1; assign rom[13'h13df] = 0; assign rom[13'h13e0] = 0; assign rom[13'h13e1] = 1; assign rom[13'h13e2] = 1; assign rom[13'h13e3] = 0; assign rom[13'h13e4] = 0; assign rom[13'h13e5] = 1; assign rom[13'h13e6] = 1; assign rom[13'h13e7] = 0; assign rom[13'h13e8] = 0; assign rom[13'h13e9] = 1; assign rom[13'h13ea] = 1; assign rom[13'h13eb] = 0; assign rom[13'h13ec] = 0; assign rom[13'h13ed] = 1; assign rom[13'h13ee] = 1; assign rom[13'h13ef] = 0; assign rom[13'h13f0] = 0; assign rom[13'h13f1] = 0; assign rom[13'h13f2] = 1; assign rom[13'h13f3] = 1; assign rom[13'h13f4] = 1; assign rom[13'h13f5] = 1; assign rom[13'h13f6] = 0; assign rom[13'h13f7] = 0; assign rom[13'h13f8] = 0; assign rom[13'h13f9] = 0; assign rom[13'h13fa] = 0; assign rom[13'h13fb] = 0; assign rom[13'h13fc] = 0; assign rom[13'h13fd] = 0; assign rom[13'h13fe] = 0; assign rom[13'h13ff] = 0; assign rom[13'h1400] = 0; assign rom[13'h1401] = 1; assign rom[13'h1402] = 1; assign rom[13'h1403] = 1; assign rom[13'h1404] = 1; assign rom[13'h1405] = 1; assign rom[13'h1406] = 0; assign rom[13'h1407] = 0; assign rom[13'h1408] = 0; assign rom[13'h1409] = 1; assign rom[13'h140a] = 1; assign rom[13'h140b] = 0; assign rom[13'h140c] = 0; assign rom[13'h140d] = 1; assign rom[13'h140e] = 1; assign rom[13'h140f] = 0; assign rom[13'h1410] = 0; assign rom[13'h1411] = 1; assign rom[13'h1412] = 1; assign rom[13'h1413] = 0; assign rom[13'h1414] = 0; assign rom[13'h1415] = 1; assign rom[13'h1416] = 1; assign rom[13'h1417] = 0; assign rom[13'h1418] = 0; assign rom[13'h1419] = 1; assign rom[13'h141a] = 1; assign rom[13'h141b] = 1; assign rom[13'h141c] = 1; assign rom[13'h141d] = 1; assign rom[13'h141e] = 0; assign rom[13'h141f] = 0; assign rom[13'h1420] = 0; assign rom[13'h1421] = 1; assign rom[13'h1422] = 1; assign rom[13'h1423] = 0; assign rom[13'h1424] = 0; assign rom[13'h1425] = 0; assign rom[13'h1426] = 0; assign rom[13'h1427] = 0; assign rom[13'h1428] = 0; assign rom[13'h1429] = 1; assign rom[13'h142a] = 1; assign rom[13'h142b] = 0; assign rom[13'h142c] = 0; assign rom[13'h142d] = 0; assign rom[13'h142e] = 0; assign rom[13'h142f] = 0; assign rom[13'h1430] = 0; assign rom[13'h1431] = 1; assign rom[13'h1432] = 1; assign rom[13'h1433] = 0; assign rom[13'h1434] = 0; assign rom[13'h1435] = 0; assign rom[13'h1436] = 0; assign rom[13'h1437] = 0; assign rom[13'h1438] = 0; assign rom[13'h1439] = 0; assign rom[13'h143a] = 0; assign rom[13'h143b] = 0; assign rom[13'h143c] = 0; assign rom[13'h143d] = 0; assign rom[13'h143e] = 0; assign rom[13'h143f] = 0; assign rom[13'h1440] = 0; assign rom[13'h1441] = 0; assign rom[13'h1442] = 1; assign rom[13'h1443] = 1; assign rom[13'h1444] = 1; assign rom[13'h1445] = 1; assign rom[13'h1446] = 0; assign rom[13'h1447] = 0; assign rom[13'h1448] = 0; assign rom[13'h1449] = 1; assign rom[13'h144a] = 1; assign rom[13'h144b] = 0; assign rom[13'h144c] = 0; assign rom[13'h144d] = 1; assign rom[13'h144e] = 1; assign rom[13'h144f] = 0; assign rom[13'h1450] = 0; assign rom[13'h1451] = 1; assign rom[13'h1452] = 1; assign rom[13'h1453] = 0; assign rom[13'h1454] = 0; assign rom[13'h1455] = 1; assign rom[13'h1456] = 1; assign rom[13'h1457] = 0; assign rom[13'h1458] = 0; assign rom[13'h1459] = 1; assign rom[13'h145a] = 1; assign rom[13'h145b] = 0; assign rom[13'h145c] = 0; assign rom[13'h145d] = 1; assign rom[13'h145e] = 1; assign rom[13'h145f] = 0; assign rom[13'h1460] = 0; assign rom[13'h1461] = 1; assign rom[13'h1462] = 1; assign rom[13'h1463] = 0; assign rom[13'h1464] = 1; assign rom[13'h1465] = 1; assign rom[13'h1466] = 1; assign rom[13'h1467] = 0; assign rom[13'h1468] = 0; assign rom[13'h1469] = 1; assign rom[13'h146a] = 1; assign rom[13'h146b] = 0; assign rom[13'h146c] = 0; assign rom[13'h146d] = 1; assign rom[13'h146e] = 1; assign rom[13'h146f] = 0; assign rom[13'h1470] = 0; assign rom[13'h1471] = 0; assign rom[13'h1472] = 1; assign rom[13'h1473] = 1; assign rom[13'h1474] = 1; assign rom[13'h1475] = 1; assign rom[13'h1476] = 1; assign rom[13'h1477] = 0; assign rom[13'h1478] = 0; assign rom[13'h1479] = 0; assign rom[13'h147a] = 0; assign rom[13'h147b] = 0; assign rom[13'h147c] = 0; assign rom[13'h147d] = 0; assign rom[13'h147e] = 0; assign rom[13'h147f] = 0; assign rom[13'h1480] = 0; assign rom[13'h1481] = 1; assign rom[13'h1482] = 1; assign rom[13'h1483] = 1; assign rom[13'h1484] = 1; assign rom[13'h1485] = 1; assign rom[13'h1486] = 0; assign rom[13'h1487] = 0; assign rom[13'h1488] = 0; assign rom[13'h1489] = 1; assign rom[13'h148a] = 1; assign rom[13'h148b] = 0; assign rom[13'h148c] = 0; assign rom[13'h148d] = 1; assign rom[13'h148e] = 1; assign rom[13'h148f] = 0; assign rom[13'h1490] = 0; assign rom[13'h1491] = 1; assign rom[13'h1492] = 1; assign rom[13'h1493] = 0; assign rom[13'h1494] = 0; assign rom[13'h1495] = 1; assign rom[13'h1496] = 1; assign rom[13'h1497] = 0; assign rom[13'h1498] = 0; assign rom[13'h1499] = 1; assign rom[13'h149a] = 1; assign rom[13'h149b] = 1; assign rom[13'h149c] = 1; assign rom[13'h149d] = 1; assign rom[13'h149e] = 0; assign rom[13'h149f] = 0; assign rom[13'h14a0] = 0; assign rom[13'h14a1] = 1; assign rom[13'h14a2] = 1; assign rom[13'h14a3] = 0; assign rom[13'h14a4] = 0; assign rom[13'h14a5] = 1; assign rom[13'h14a6] = 1; assign rom[13'h14a7] = 0; assign rom[13'h14a8] = 0; assign rom[13'h14a9] = 1; assign rom[13'h14aa] = 1; assign rom[13'h14ab] = 0; assign rom[13'h14ac] = 0; assign rom[13'h14ad] = 1; assign rom[13'h14ae] = 1; assign rom[13'h14af] = 0; assign rom[13'h14b0] = 0; assign rom[13'h14b1] = 1; assign rom[13'h14b2] = 1; assign rom[13'h14b3] = 0; assign rom[13'h14b4] = 0; assign rom[13'h14b5] = 1; assign rom[13'h14b6] = 1; assign rom[13'h14b7] = 0; assign rom[13'h14b8] = 0; assign rom[13'h14b9] = 0; assign rom[13'h14ba] = 0; assign rom[13'h14bb] = 0; assign rom[13'h14bc] = 0; assign rom[13'h14bd] = 0; assign rom[13'h14be] = 0; assign rom[13'h14bf] = 0; assign rom[13'h14c0] = 0; assign rom[13'h14c1] = 0; assign rom[13'h14c2] = 1; assign rom[13'h14c3] = 1; assign rom[13'h14c4] = 1; assign rom[13'h14c5] = 1; assign rom[13'h14c6] = 1; assign rom[13'h14c7] = 0; assign rom[13'h14c8] = 0; assign rom[13'h14c9] = 1; assign rom[13'h14ca] = 1; assign rom[13'h14cb] = 0; assign rom[13'h14cc] = 0; assign rom[13'h14cd] = 0; assign rom[13'h14ce] = 0; assign rom[13'h14cf] = 0; assign rom[13'h14d0] = 0; assign rom[13'h14d1] = 1; assign rom[13'h14d2] = 1; assign rom[13'h14d3] = 0; assign rom[13'h14d4] = 0; assign rom[13'h14d5] = 0; assign rom[13'h14d6] = 0; assign rom[13'h14d7] = 0; assign rom[13'h14d8] = 0; assign rom[13'h14d9] = 0; assign rom[13'h14da] = 1; assign rom[13'h14db] = 1; assign rom[13'h14dc] = 1; assign rom[13'h14dd] = 1; assign rom[13'h14de] = 0; assign rom[13'h14df] = 0; assign rom[13'h14e0] = 0; assign rom[13'h14e1] = 0; assign rom[13'h14e2] = 0; assign rom[13'h14e3] = 0; assign rom[13'h14e4] = 0; assign rom[13'h14e5] = 1; assign rom[13'h14e6] = 1; assign rom[13'h14e7] = 0; assign rom[13'h14e8] = 0; assign rom[13'h14e9] = 0; assign rom[13'h14ea] = 0; assign rom[13'h14eb] = 0; assign rom[13'h14ec] = 0; assign rom[13'h14ed] = 1; assign rom[13'h14ee] = 1; assign rom[13'h14ef] = 0; assign rom[13'h14f0] = 0; assign rom[13'h14f1] = 1; assign rom[13'h14f2] = 1; assign rom[13'h14f3] = 1; assign rom[13'h14f4] = 1; assign rom[13'h14f5] = 1; assign rom[13'h14f6] = 0; assign rom[13'h14f7] = 0; assign rom[13'h14f8] = 0; assign rom[13'h14f9] = 0; assign rom[13'h14fa] = 0; assign rom[13'h14fb] = 0; assign rom[13'h14fc] = 0; assign rom[13'h14fd] = 0; assign rom[13'h14fe] = 0; assign rom[13'h14ff] = 0; assign rom[13'h1500] = 0; assign rom[13'h1501] = 1; assign rom[13'h1502] = 1; assign rom[13'h1503] = 1; assign rom[13'h1504] = 1; assign rom[13'h1505] = 1; assign rom[13'h1506] = 1; assign rom[13'h1507] = 0; assign rom[13'h1508] = 0; assign rom[13'h1509] = 0; assign rom[13'h150a] = 0; assign rom[13'h150b] = 1; assign rom[13'h150c] = 1; assign rom[13'h150d] = 0; assign rom[13'h150e] = 0; assign rom[13'h150f] = 0; assign rom[13'h1510] = 0; assign rom[13'h1511] = 0; assign rom[13'h1512] = 0; assign rom[13'h1513] = 1; assign rom[13'h1514] = 1; assign rom[13'h1515] = 0; assign rom[13'h1516] = 0; assign rom[13'h1517] = 0; assign rom[13'h1518] = 0; assign rom[13'h1519] = 0; assign rom[13'h151a] = 0; assign rom[13'h151b] = 1; assign rom[13'h151c] = 1; assign rom[13'h151d] = 0; assign rom[13'h151e] = 0; assign rom[13'h151f] = 0; assign rom[13'h1520] = 0; assign rom[13'h1521] = 0; assign rom[13'h1522] = 0; assign rom[13'h1523] = 1; assign rom[13'h1524] = 1; assign rom[13'h1525] = 0; assign rom[13'h1526] = 0; assign rom[13'h1527] = 0; assign rom[13'h1528] = 0; assign rom[13'h1529] = 0; assign rom[13'h152a] = 0; assign rom[13'h152b] = 1; assign rom[13'h152c] = 1; assign rom[13'h152d] = 0; assign rom[13'h152e] = 0; assign rom[13'h152f] = 0; assign rom[13'h1530] = 0; assign rom[13'h1531] = 0; assign rom[13'h1532] = 0; assign rom[13'h1533] = 1; assign rom[13'h1534] = 1; assign rom[13'h1535] = 0; assign rom[13'h1536] = 0; assign rom[13'h1537] = 0; assign rom[13'h1538] = 0; assign rom[13'h1539] = 0; assign rom[13'h153a] = 0; assign rom[13'h153b] = 0; assign rom[13'h153c] = 0; assign rom[13'h153d] = 0; assign rom[13'h153e] = 0; assign rom[13'h153f] = 0; assign rom[13'h1540] = 0; assign rom[13'h1541] = 1; assign rom[13'h1542] = 1; assign rom[13'h1543] = 0; assign rom[13'h1544] = 0; assign rom[13'h1545] = 1; assign rom[13'h1546] = 1; assign rom[13'h1547] = 0; assign rom[13'h1548] = 0; assign rom[13'h1549] = 1; assign rom[13'h154a] = 1; assign rom[13'h154b] = 0; assign rom[13'h154c] = 0; assign rom[13'h154d] = 1; assign rom[13'h154e] = 1; assign rom[13'h154f] = 0; assign rom[13'h1550] = 0; assign rom[13'h1551] = 1; assign rom[13'h1552] = 1; assign rom[13'h1553] = 0; assign rom[13'h1554] = 0; assign rom[13'h1555] = 1; assign rom[13'h1556] = 1; assign rom[13'h1557] = 0; assign rom[13'h1558] = 0; assign rom[13'h1559] = 1; assign rom[13'h155a] = 1; assign rom[13'h155b] = 0; assign rom[13'h155c] = 0; assign rom[13'h155d] = 1; assign rom[13'h155e] = 1; assign rom[13'h155f] = 0; assign rom[13'h1560] = 0; assign rom[13'h1561] = 1; assign rom[13'h1562] = 1; assign rom[13'h1563] = 0; assign rom[13'h1564] = 0; assign rom[13'h1565] = 1; assign rom[13'h1566] = 1; assign rom[13'h1567] = 0; assign rom[13'h1568] = 0; assign rom[13'h1569] = 1; assign rom[13'h156a] = 1; assign rom[13'h156b] = 0; assign rom[13'h156c] = 0; assign rom[13'h156d] = 1; assign rom[13'h156e] = 1; assign rom[13'h156f] = 0; assign rom[13'h1570] = 0; assign rom[13'h1571] = 0; assign rom[13'h1572] = 1; assign rom[13'h1573] = 1; assign rom[13'h1574] = 1; assign rom[13'h1575] = 1; assign rom[13'h1576] = 0; assign rom[13'h1577] = 0; assign rom[13'h1578] = 0; assign rom[13'h1579] = 0; assign rom[13'h157a] = 0; assign rom[13'h157b] = 0; assign rom[13'h157c] = 0; assign rom[13'h157d] = 0; assign rom[13'h157e] = 0; assign rom[13'h157f] = 0; assign rom[13'h1580] = 0; assign rom[13'h1581] = 1; assign rom[13'h1582] = 1; assign rom[13'h1583] = 0; assign rom[13'h1584] = 0; assign rom[13'h1585] = 1; assign rom[13'h1586] = 1; assign rom[13'h1587] = 0; assign rom[13'h1588] = 0; assign rom[13'h1589] = 1; assign rom[13'h158a] = 1; assign rom[13'h158b] = 0; assign rom[13'h158c] = 0; assign rom[13'h158d] = 1; assign rom[13'h158e] = 1; assign rom[13'h158f] = 0; assign rom[13'h1590] = 0; assign rom[13'h1591] = 1; assign rom[13'h1592] = 1; assign rom[13'h1593] = 0; assign rom[13'h1594] = 0; assign rom[13'h1595] = 1; assign rom[13'h1596] = 1; assign rom[13'h1597] = 0; assign rom[13'h1598] = 0; assign rom[13'h1599] = 1; assign rom[13'h159a] = 1; assign rom[13'h159b] = 0; assign rom[13'h159c] = 0; assign rom[13'h159d] = 1; assign rom[13'h159e] = 1; assign rom[13'h159f] = 0; assign rom[13'h15a0] = 0; assign rom[13'h15a1] = 0; assign rom[13'h15a2] = 1; assign rom[13'h15a3] = 1; assign rom[13'h15a4] = 1; assign rom[13'h15a5] = 1; assign rom[13'h15a6] = 0; assign rom[13'h15a7] = 0; assign rom[13'h15a8] = 0; assign rom[13'h15a9] = 0; assign rom[13'h15aa] = 1; assign rom[13'h15ab] = 1; assign rom[13'h15ac] = 1; assign rom[13'h15ad] = 1; assign rom[13'h15ae] = 0; assign rom[13'h15af] = 0; assign rom[13'h15b0] = 0; assign rom[13'h15b1] = 0; assign rom[13'h15b2] = 0; assign rom[13'h15b3] = 1; assign rom[13'h15b4] = 1; assign rom[13'h15b5] = 0; assign rom[13'h15b6] = 0; assign rom[13'h15b7] = 0; assign rom[13'h15b8] = 0; assign rom[13'h15b9] = 0; assign rom[13'h15ba] = 0; assign rom[13'h15bb] = 0; assign rom[13'h15bc] = 0; assign rom[13'h15bd] = 0; assign rom[13'h15be] = 0; assign rom[13'h15bf] = 0; assign rom[13'h15c0] = 1; assign rom[13'h15c1] = 1; assign rom[13'h15c2] = 0; assign rom[13'h15c3] = 0; assign rom[13'h15c4] = 0; assign rom[13'h15c5] = 1; assign rom[13'h15c6] = 1; assign rom[13'h15c7] = 0; assign rom[13'h15c8] = 1; assign rom[13'h15c9] = 1; assign rom[13'h15ca] = 0; assign rom[13'h15cb] = 0; assign rom[13'h15cc] = 0; assign rom[13'h15cd] = 1; assign rom[13'h15ce] = 1; assign rom[13'h15cf] = 0; assign rom[13'h15d0] = 1; assign rom[13'h15d1] = 1; assign rom[13'h15d2] = 0; assign rom[13'h15d3] = 1; assign rom[13'h15d4] = 0; assign rom[13'h15d5] = 1; assign rom[13'h15d6] = 1; assign rom[13'h15d7] = 0; assign rom[13'h15d8] = 1; assign rom[13'h15d9] = 1; assign rom[13'h15da] = 0; assign rom[13'h15db] = 1; assign rom[13'h15dc] = 0; assign rom[13'h15dd] = 1; assign rom[13'h15de] = 1; assign rom[13'h15df] = 0; assign rom[13'h15e0] = 1; assign rom[13'h15e1] = 1; assign rom[13'h15e2] = 1; assign rom[13'h15e3] = 1; assign rom[13'h15e4] = 1; assign rom[13'h15e5] = 1; assign rom[13'h15e6] = 1; assign rom[13'h15e7] = 0; assign rom[13'h15e8] = 1; assign rom[13'h15e9] = 1; assign rom[13'h15ea] = 1; assign rom[13'h15eb] = 0; assign rom[13'h15ec] = 1; assign rom[13'h15ed] = 1; assign rom[13'h15ee] = 1; assign rom[13'h15ef] = 0; assign rom[13'h15f0] = 0; assign rom[13'h15f1] = 1; assign rom[13'h15f2] = 0; assign rom[13'h15f3] = 0; assign rom[13'h15f4] = 0; assign rom[13'h15f5] = 1; assign rom[13'h15f6] = 0; assign rom[13'h15f7] = 0; assign rom[13'h15f8] = 0; assign rom[13'h15f9] = 0; assign rom[13'h15fa] = 0; assign rom[13'h15fb] = 0; assign rom[13'h15fc] = 0; assign rom[13'h15fd] = 0; assign rom[13'h15fe] = 0; assign rom[13'h15ff] = 0; assign rom[13'h1600] = 0; assign rom[13'h1601] = 1; assign rom[13'h1602] = 1; assign rom[13'h1603] = 0; assign rom[13'h1604] = 0; assign rom[13'h1605] = 1; assign rom[13'h1606] = 1; assign rom[13'h1607] = 0; assign rom[13'h1608] = 0; assign rom[13'h1609] = 1; assign rom[13'h160a] = 1; assign rom[13'h160b] = 0; assign rom[13'h160c] = 0; assign rom[13'h160d] = 1; assign rom[13'h160e] = 1; assign rom[13'h160f] = 0; assign rom[13'h1610] = 0; assign rom[13'h1611] = 0; assign rom[13'h1612] = 1; assign rom[13'h1613] = 1; assign rom[13'h1614] = 1; assign rom[13'h1615] = 1; assign rom[13'h1616] = 0; assign rom[13'h1617] = 0; assign rom[13'h1618] = 0; assign rom[13'h1619] = 0; assign rom[13'h161a] = 0; assign rom[13'h161b] = 1; assign rom[13'h161c] = 1; assign rom[13'h161d] = 0; assign rom[13'h161e] = 0; assign rom[13'h161f] = 0; assign rom[13'h1620] = 0; assign rom[13'h1621] = 0; assign rom[13'h1622] = 1; assign rom[13'h1623] = 1; assign rom[13'h1624] = 1; assign rom[13'h1625] = 1; assign rom[13'h1626] = 0; assign rom[13'h1627] = 0; assign rom[13'h1628] = 0; assign rom[13'h1629] = 1; assign rom[13'h162a] = 1; assign rom[13'h162b] = 0; assign rom[13'h162c] = 0; assign rom[13'h162d] = 1; assign rom[13'h162e] = 1; assign rom[13'h162f] = 0; assign rom[13'h1630] = 0; assign rom[13'h1631] = 1; assign rom[13'h1632] = 1; assign rom[13'h1633] = 0; assign rom[13'h1634] = 0; assign rom[13'h1635] = 1; assign rom[13'h1636] = 1; assign rom[13'h1637] = 0; assign rom[13'h1638] = 0; assign rom[13'h1639] = 0; assign rom[13'h163a] = 0; assign rom[13'h163b] = 0; assign rom[13'h163c] = 0; assign rom[13'h163d] = 0; assign rom[13'h163e] = 0; assign rom[13'h163f] = 0; assign rom[13'h1640] = 0; assign rom[13'h1641] = 1; assign rom[13'h1642] = 1; assign rom[13'h1643] = 0; assign rom[13'h1644] = 0; assign rom[13'h1645] = 1; assign rom[13'h1646] = 1; assign rom[13'h1647] = 0; assign rom[13'h1648] = 0; assign rom[13'h1649] = 1; assign rom[13'h164a] = 1; assign rom[13'h164b] = 0; assign rom[13'h164c] = 0; assign rom[13'h164d] = 1; assign rom[13'h164e] = 1; assign rom[13'h164f] = 0; assign rom[13'h1650] = 0; assign rom[13'h1651] = 1; assign rom[13'h1652] = 1; assign rom[13'h1653] = 0; assign rom[13'h1654] = 0; assign rom[13'h1655] = 1; assign rom[13'h1656] = 1; assign rom[13'h1657] = 0; assign rom[13'h1658] = 0; assign rom[13'h1659] = 0; assign rom[13'h165a] = 1; assign rom[13'h165b] = 1; assign rom[13'h165c] = 1; assign rom[13'h165d] = 1; assign rom[13'h165e] = 0; assign rom[13'h165f] = 0; assign rom[13'h1660] = 0; assign rom[13'h1661] = 0; assign rom[13'h1662] = 0; assign rom[13'h1663] = 1; assign rom[13'h1664] = 1; assign rom[13'h1665] = 0; assign rom[13'h1666] = 0; assign rom[13'h1667] = 0; assign rom[13'h1668] = 0; assign rom[13'h1669] = 0; assign rom[13'h166a] = 0; assign rom[13'h166b] = 1; assign rom[13'h166c] = 1; assign rom[13'h166d] = 0; assign rom[13'h166e] = 0; assign rom[13'h166f] = 0; assign rom[13'h1670] = 0; assign rom[13'h1671] = 0; assign rom[13'h1672] = 0; assign rom[13'h1673] = 1; assign rom[13'h1674] = 1; assign rom[13'h1675] = 0; assign rom[13'h1676] = 0; assign rom[13'h1677] = 0; assign rom[13'h1678] = 0; assign rom[13'h1679] = 0; assign rom[13'h167a] = 0; assign rom[13'h167b] = 0; assign rom[13'h167c] = 0; assign rom[13'h167d] = 0; assign rom[13'h167e] = 0; assign rom[13'h167f] = 0; assign rom[13'h1680] = 0; assign rom[13'h1681] = 1; assign rom[13'h1682] = 1; assign rom[13'h1683] = 1; assign rom[13'h1684] = 1; assign rom[13'h1685] = 1; assign rom[13'h1686] = 1; assign rom[13'h1687] = 0; assign rom[13'h1688] = 0; assign rom[13'h1689] = 0; assign rom[13'h168a] = 0; assign rom[13'h168b] = 0; assign rom[13'h168c] = 0; assign rom[13'h168d] = 1; assign rom[13'h168e] = 1; assign rom[13'h168f] = 0; assign rom[13'h1690] = 0; assign rom[13'h1691] = 0; assign rom[13'h1692] = 0; assign rom[13'h1693] = 0; assign rom[13'h1694] = 1; assign rom[13'h1695] = 1; assign rom[13'h1696] = 0; assign rom[13'h1697] = 0; assign rom[13'h1698] = 0; assign rom[13'h1699] = 0; assign rom[13'h169a] = 0; assign rom[13'h169b] = 1; assign rom[13'h169c] = 1; assign rom[13'h169d] = 0; assign rom[13'h169e] = 0; assign rom[13'h169f] = 0; assign rom[13'h16a0] = 0; assign rom[13'h16a1] = 0; assign rom[13'h16a2] = 1; assign rom[13'h16a3] = 1; assign rom[13'h16a4] = 0; assign rom[13'h16a5] = 0; assign rom[13'h16a6] = 0; assign rom[13'h16a7] = 0; assign rom[13'h16a8] = 0; assign rom[13'h16a9] = 1; assign rom[13'h16aa] = 1; assign rom[13'h16ab] = 0; assign rom[13'h16ac] = 0; assign rom[13'h16ad] = 0; assign rom[13'h16ae] = 0; assign rom[13'h16af] = 0; assign rom[13'h16b0] = 0; assign rom[13'h16b1] = 1; assign rom[13'h16b2] = 1; assign rom[13'h16b3] = 1; assign rom[13'h16b4] = 1; assign rom[13'h16b5] = 1; assign rom[13'h16b6] = 1; assign rom[13'h16b7] = 0; assign rom[13'h16b8] = 0; assign rom[13'h16b9] = 0; assign rom[13'h16ba] = 0; assign rom[13'h16bb] = 0; assign rom[13'h16bc] = 0; assign rom[13'h16bd] = 0; assign rom[13'h16be] = 0; assign rom[13'h16bf] = 0; assign rom[13'h16c0] = 0; assign rom[13'h16c1] = 0; assign rom[13'h16c2] = 1; assign rom[13'h16c3] = 1; assign rom[13'h16c4] = 1; assign rom[13'h16c5] = 1; assign rom[13'h16c6] = 0; assign rom[13'h16c7] = 0; assign rom[13'h16c8] = 0; assign rom[13'h16c9] = 0; assign rom[13'h16ca] = 1; assign rom[13'h16cb] = 1; assign rom[13'h16cc] = 0; assign rom[13'h16cd] = 0; assign rom[13'h16ce] = 0; assign rom[13'h16cf] = 0; assign rom[13'h16d0] = 0; assign rom[13'h16d1] = 0; assign rom[13'h16d2] = 1; assign rom[13'h16d3] = 1; assign rom[13'h16d4] = 0; assign rom[13'h16d5] = 0; assign rom[13'h16d6] = 0; assign rom[13'h16d7] = 0; assign rom[13'h16d8] = 0; assign rom[13'h16d9] = 0; assign rom[13'h16da] = 1; assign rom[13'h16db] = 1; assign rom[13'h16dc] = 0; assign rom[13'h16dd] = 0; assign rom[13'h16de] = 0; assign rom[13'h16df] = 0; assign rom[13'h16e0] = 0; assign rom[13'h16e1] = 0; assign rom[13'h16e2] = 1; assign rom[13'h16e3] = 1; assign rom[13'h16e4] = 0; assign rom[13'h16e5] = 0; assign rom[13'h16e6] = 0; assign rom[13'h16e7] = 0; assign rom[13'h16e8] = 0; assign rom[13'h16e9] = 0; assign rom[13'h16ea] = 1; assign rom[13'h16eb] = 1; assign rom[13'h16ec] = 0; assign rom[13'h16ed] = 0; assign rom[13'h16ee] = 0; assign rom[13'h16ef] = 0; assign rom[13'h16f0] = 0; assign rom[13'h16f1] = 0; assign rom[13'h16f2] = 1; assign rom[13'h16f3] = 1; assign rom[13'h16f4] = 1; assign rom[13'h16f5] = 1; assign rom[13'h16f6] = 0; assign rom[13'h16f7] = 0; assign rom[13'h16f8] = 0; assign rom[13'h16f9] = 0; assign rom[13'h16fa] = 0; assign rom[13'h16fb] = 0; assign rom[13'h16fc] = 0; assign rom[13'h16fd] = 0; assign rom[13'h16fe] = 0; assign rom[13'h16ff] = 0; assign rom[13'h1700] = 0; assign rom[13'h1701] = 1; assign rom[13'h1702] = 0; assign rom[13'h1703] = 0; assign rom[13'h1704] = 0; assign rom[13'h1705] = 0; assign rom[13'h1706] = 0; assign rom[13'h1707] = 0; assign rom[13'h1708] = 0; assign rom[13'h1709] = 1; assign rom[13'h170a] = 1; assign rom[13'h170b] = 0; assign rom[13'h170c] = 0; assign rom[13'h170d] = 0; assign rom[13'h170e] = 0; assign rom[13'h170f] = 0; assign rom[13'h1710] = 0; assign rom[13'h1711] = 0; assign rom[13'h1712] = 1; assign rom[13'h1713] = 1; assign rom[13'h1714] = 0; assign rom[13'h1715] = 0; assign rom[13'h1716] = 0; assign rom[13'h1717] = 0; assign rom[13'h1718] = 0; assign rom[13'h1719] = 0; assign rom[13'h171a] = 0; assign rom[13'h171b] = 1; assign rom[13'h171c] = 1; assign rom[13'h171d] = 0; assign rom[13'h171e] = 0; assign rom[13'h171f] = 0; assign rom[13'h1720] = 0; assign rom[13'h1721] = 0; assign rom[13'h1722] = 0; assign rom[13'h1723] = 0; assign rom[13'h1724] = 1; assign rom[13'h1725] = 1; assign rom[13'h1726] = 0; assign rom[13'h1727] = 0; assign rom[13'h1728] = 0; assign rom[13'h1729] = 0; assign rom[13'h172a] = 0; assign rom[13'h172b] = 0; assign rom[13'h172c] = 0; assign rom[13'h172d] = 1; assign rom[13'h172e] = 1; assign rom[13'h172f] = 0; assign rom[13'h1730] = 0; assign rom[13'h1731] = 0; assign rom[13'h1732] = 0; assign rom[13'h1733] = 0; assign rom[13'h1734] = 0; assign rom[13'h1735] = 0; assign rom[13'h1736] = 1; assign rom[13'h1737] = 0; assign rom[13'h1738] = 0; assign rom[13'h1739] = 0; assign rom[13'h173a] = 0; assign rom[13'h173b] = 0; assign rom[13'h173c] = 0; assign rom[13'h173d] = 0; assign rom[13'h173e] = 0; assign rom[13'h173f] = 0; assign rom[13'h1740] = 0; assign rom[13'h1741] = 0; assign rom[13'h1742] = 1; assign rom[13'h1743] = 1; assign rom[13'h1744] = 1; assign rom[13'h1745] = 1; assign rom[13'h1746] = 0; assign rom[13'h1747] = 0; assign rom[13'h1748] = 0; assign rom[13'h1749] = 0; assign rom[13'h174a] = 0; assign rom[13'h174b] = 0; assign rom[13'h174c] = 1; assign rom[13'h174d] = 1; assign rom[13'h174e] = 0; assign rom[13'h174f] = 0; assign rom[13'h1750] = 0; assign rom[13'h1751] = 0; assign rom[13'h1752] = 0; assign rom[13'h1753] = 0; assign rom[13'h1754] = 1; assign rom[13'h1755] = 1; assign rom[13'h1756] = 0; assign rom[13'h1757] = 0; assign rom[13'h1758] = 0; assign rom[13'h1759] = 0; assign rom[13'h175a] = 0; assign rom[13'h175b] = 0; assign rom[13'h175c] = 1; assign rom[13'h175d] = 1; assign rom[13'h175e] = 0; assign rom[13'h175f] = 0; assign rom[13'h1760] = 0; assign rom[13'h1761] = 0; assign rom[13'h1762] = 0; assign rom[13'h1763] = 0; assign rom[13'h1764] = 1; assign rom[13'h1765] = 1; assign rom[13'h1766] = 0; assign rom[13'h1767] = 0; assign rom[13'h1768] = 0; assign rom[13'h1769] = 0; assign rom[13'h176a] = 0; assign rom[13'h176b] = 0; assign rom[13'h176c] = 1; assign rom[13'h176d] = 1; assign rom[13'h176e] = 0; assign rom[13'h176f] = 0; assign rom[13'h1770] = 0; assign rom[13'h1771] = 0; assign rom[13'h1772] = 1; assign rom[13'h1773] = 1; assign rom[13'h1774] = 1; assign rom[13'h1775] = 1; assign rom[13'h1776] = 0; assign rom[13'h1777] = 0; assign rom[13'h1778] = 0; assign rom[13'h1779] = 0; assign rom[13'h177a] = 0; assign rom[13'h177b] = 0; assign rom[13'h177c] = 0; assign rom[13'h177d] = 0; assign rom[13'h177e] = 0; assign rom[13'h177f] = 0; assign rom[13'h1780] = 0; assign rom[13'h1781] = 0; assign rom[13'h1782] = 0; assign rom[13'h1783] = 1; assign rom[13'h1784] = 0; assign rom[13'h1785] = 0; assign rom[13'h1786] = 0; assign rom[13'h1787] = 0; assign rom[13'h1788] = 0; assign rom[13'h1789] = 0; assign rom[13'h178a] = 1; assign rom[13'h178b] = 1; assign rom[13'h178c] = 1; assign rom[13'h178d] = 0; assign rom[13'h178e] = 0; assign rom[13'h178f] = 0; assign rom[13'h1790] = 0; assign rom[13'h1791] = 1; assign rom[13'h1792] = 1; assign rom[13'h1793] = 0; assign rom[13'h1794] = 1; assign rom[13'h1795] = 1; assign rom[13'h1796] = 0; assign rom[13'h1797] = 0; assign rom[13'h1798] = 0; assign rom[13'h1799] = 0; assign rom[13'h179a] = 0; assign rom[13'h179b] = 0; assign rom[13'h179c] = 0; assign rom[13'h179d] = 0; assign rom[13'h179e] = 0; assign rom[13'h179f] = 0; assign rom[13'h17a0] = 0; assign rom[13'h17a1] = 0; assign rom[13'h17a2] = 0; assign rom[13'h17a3] = 0; assign rom[13'h17a4] = 0; assign rom[13'h17a5] = 0; assign rom[13'h17a6] = 0; assign rom[13'h17a7] = 0; assign rom[13'h17a8] = 0; assign rom[13'h17a9] = 0; assign rom[13'h17aa] = 0; assign rom[13'h17ab] = 0; assign rom[13'h17ac] = 0; assign rom[13'h17ad] = 0; assign rom[13'h17ae] = 0; assign rom[13'h17af] = 0; assign rom[13'h17b0] = 0; assign rom[13'h17b1] = 0; assign rom[13'h17b2] = 0; assign rom[13'h17b3] = 0; assign rom[13'h17b4] = 0; assign rom[13'h17b5] = 0; assign rom[13'h17b6] = 0; assign rom[13'h17b7] = 0; assign rom[13'h17b8] = 0; assign rom[13'h17b9] = 0; assign rom[13'h17ba] = 0; assign rom[13'h17bb] = 0; assign rom[13'h17bc] = 0; assign rom[13'h17bd] = 0; assign rom[13'h17be] = 0; assign rom[13'h17bf] = 0; assign rom[13'h17c0] = 0; assign rom[13'h17c1] = 0; assign rom[13'h17c2] = 0; assign rom[13'h17c3] = 0; assign rom[13'h17c4] = 0; assign rom[13'h17c5] = 0; assign rom[13'h17c6] = 0; assign rom[13'h17c7] = 0; assign rom[13'h17c8] = 0; assign rom[13'h17c9] = 0; assign rom[13'h17ca] = 0; assign rom[13'h17cb] = 0; assign rom[13'h17cc] = 0; assign rom[13'h17cd] = 0; assign rom[13'h17ce] = 0; assign rom[13'h17cf] = 0; assign rom[13'h17d0] = 0; assign rom[13'h17d1] = 0; assign rom[13'h17d2] = 0; assign rom[13'h17d3] = 0; assign rom[13'h17d4] = 0; assign rom[13'h17d5] = 0; assign rom[13'h17d6] = 0; assign rom[13'h17d7] = 0; assign rom[13'h17d8] = 0; assign rom[13'h17d9] = 0; assign rom[13'h17da] = 0; assign rom[13'h17db] = 0; assign rom[13'h17dc] = 0; assign rom[13'h17dd] = 0; assign rom[13'h17de] = 0; assign rom[13'h17df] = 0; assign rom[13'h17e0] = 0; assign rom[13'h17e1] = 0; assign rom[13'h17e2] = 0; assign rom[13'h17e3] = 0; assign rom[13'h17e4] = 0; assign rom[13'h17e5] = 0; assign rom[13'h17e6] = 0; assign rom[13'h17e7] = 0; assign rom[13'h17e8] = 0; assign rom[13'h17e9] = 0; assign rom[13'h17ea] = 0; assign rom[13'h17eb] = 0; assign rom[13'h17ec] = 0; assign rom[13'h17ed] = 0; assign rom[13'h17ee] = 0; assign rom[13'h17ef] = 0; assign rom[13'h17f0] = 0; assign rom[13'h17f1] = 0; assign rom[13'h17f2] = 0; assign rom[13'h17f3] = 0; assign rom[13'h17f4] = 0; assign rom[13'h17f5] = 0; assign rom[13'h17f6] = 0; assign rom[13'h17f7] = 0; assign rom[13'h17f8] = 1; assign rom[13'h17f9] = 1; assign rom[13'h17fa] = 1; assign rom[13'h17fb] = 1; assign rom[13'h17fc] = 1; assign rom[13'h17fd] = 1; assign rom[13'h17fe] = 1; assign rom[13'h17ff] = 1; assign rom[13'h1800] = 0; assign rom[13'h1801] = 0; assign rom[13'h1802] = 0; assign rom[13'h1803] = 1; assign rom[13'h1804] = 1; assign rom[13'h1805] = 0; assign rom[13'h1806] = 0; assign rom[13'h1807] = 0; assign rom[13'h1808] = 0; assign rom[13'h1809] = 0; assign rom[13'h180a] = 0; assign rom[13'h180b] = 1; assign rom[13'h180c] = 1; assign rom[13'h180d] = 0; assign rom[13'h180e] = 0; assign rom[13'h180f] = 0; assign rom[13'h1810] = 0; assign rom[13'h1811] = 0; assign rom[13'h1812] = 0; assign rom[13'h1813] = 0; assign rom[13'h1814] = 1; assign rom[13'h1815] = 1; assign rom[13'h1816] = 0; assign rom[13'h1817] = 0; assign rom[13'h1818] = 0; assign rom[13'h1819] = 0; assign rom[13'h181a] = 0; assign rom[13'h181b] = 0; assign rom[13'h181c] = 0; assign rom[13'h181d] = 0; assign rom[13'h181e] = 0; assign rom[13'h181f] = 0; assign rom[13'h1820] = 0; assign rom[13'h1821] = 0; assign rom[13'h1822] = 0; assign rom[13'h1823] = 0; assign rom[13'h1824] = 0; assign rom[13'h1825] = 0; assign rom[13'h1826] = 0; assign rom[13'h1827] = 0; assign rom[13'h1828] = 0; assign rom[13'h1829] = 0; assign rom[13'h182a] = 0; assign rom[13'h182b] = 0; assign rom[13'h182c] = 0; assign rom[13'h182d] = 0; assign rom[13'h182e] = 0; assign rom[13'h182f] = 0; assign rom[13'h1830] = 0; assign rom[13'h1831] = 0; assign rom[13'h1832] = 0; assign rom[13'h1833] = 0; assign rom[13'h1834] = 0; assign rom[13'h1835] = 0; assign rom[13'h1836] = 0; assign rom[13'h1837] = 0; assign rom[13'h1838] = 0; assign rom[13'h1839] = 0; assign rom[13'h183a] = 0; assign rom[13'h183b] = 0; assign rom[13'h183c] = 0; assign rom[13'h183d] = 0; assign rom[13'h183e] = 0; assign rom[13'h183f] = 0; assign rom[13'h1840] = 0; assign rom[13'h1841] = 0; assign rom[13'h1842] = 0; assign rom[13'h1843] = 0; assign rom[13'h1844] = 0; assign rom[13'h1845] = 0; assign rom[13'h1846] = 0; assign rom[13'h1847] = 0; assign rom[13'h1848] = 0; assign rom[13'h1849] = 0; assign rom[13'h184a] = 0; assign rom[13'h184b] = 0; assign rom[13'h184c] = 0; assign rom[13'h184d] = 0; assign rom[13'h184e] = 0; assign rom[13'h184f] = 0; assign rom[13'h1850] = 0; assign rom[13'h1851] = 0; assign rom[13'h1852] = 1; assign rom[13'h1853] = 1; assign rom[13'h1854] = 1; assign rom[13'h1855] = 1; assign rom[13'h1856] = 0; assign rom[13'h1857] = 0; assign rom[13'h1858] = 0; assign rom[13'h1859] = 0; assign rom[13'h185a] = 0; assign rom[13'h185b] = 0; assign rom[13'h185c] = 0; assign rom[13'h185d] = 1; assign rom[13'h185e] = 1; assign rom[13'h185f] = 0; assign rom[13'h1860] = 0; assign rom[13'h1861] = 0; assign rom[13'h1862] = 1; assign rom[13'h1863] = 1; assign rom[13'h1864] = 1; assign rom[13'h1865] = 1; assign rom[13'h1866] = 1; assign rom[13'h1867] = 0; assign rom[13'h1868] = 0; assign rom[13'h1869] = 1; assign rom[13'h186a] = 1; assign rom[13'h186b] = 0; assign rom[13'h186c] = 0; assign rom[13'h186d] = 1; assign rom[13'h186e] = 1; assign rom[13'h186f] = 0; assign rom[13'h1870] = 0; assign rom[13'h1871] = 0; assign rom[13'h1872] = 1; assign rom[13'h1873] = 1; assign rom[13'h1874] = 1; assign rom[13'h1875] = 0; assign rom[13'h1876] = 1; assign rom[13'h1877] = 0; assign rom[13'h1878] = 0; assign rom[13'h1879] = 0; assign rom[13'h187a] = 0; assign rom[13'h187b] = 0; assign rom[13'h187c] = 0; assign rom[13'h187d] = 0; assign rom[13'h187e] = 0; assign rom[13'h187f] = 0; assign rom[13'h1880] = 0; assign rom[13'h1881] = 1; assign rom[13'h1882] = 1; assign rom[13'h1883] = 0; assign rom[13'h1884] = 0; assign rom[13'h1885] = 0; assign rom[13'h1886] = 0; assign rom[13'h1887] = 0; assign rom[13'h1888] = 0; assign rom[13'h1889] = 1; assign rom[13'h188a] = 1; assign rom[13'h188b] = 0; assign rom[13'h188c] = 0; assign rom[13'h188d] = 0; assign rom[13'h188e] = 0; assign rom[13'h188f] = 0; assign rom[13'h1890] = 0; assign rom[13'h1891] = 1; assign rom[13'h1892] = 1; assign rom[13'h1893] = 1; assign rom[13'h1894] = 1; assign rom[13'h1895] = 1; assign rom[13'h1896] = 0; assign rom[13'h1897] = 0; assign rom[13'h1898] = 0; assign rom[13'h1899] = 1; assign rom[13'h189a] = 1; assign rom[13'h189b] = 0; assign rom[13'h189c] = 0; assign rom[13'h189d] = 1; assign rom[13'h189e] = 1; assign rom[13'h189f] = 0; assign rom[13'h18a0] = 0; assign rom[13'h18a1] = 1; assign rom[13'h18a2] = 1; assign rom[13'h18a3] = 0; assign rom[13'h18a4] = 0; assign rom[13'h18a5] = 1; assign rom[13'h18a6] = 1; assign rom[13'h18a7] = 0; assign rom[13'h18a8] = 0; assign rom[13'h18a9] = 1; assign rom[13'h18aa] = 1; assign rom[13'h18ab] = 0; assign rom[13'h18ac] = 0; assign rom[13'h18ad] = 1; assign rom[13'h18ae] = 1; assign rom[13'h18af] = 0; assign rom[13'h18b0] = 0; assign rom[13'h18b1] = 1; assign rom[13'h18b2] = 1; assign rom[13'h18b3] = 1; assign rom[13'h18b4] = 1; assign rom[13'h18b5] = 1; assign rom[13'h18b6] = 0; assign rom[13'h18b7] = 0; assign rom[13'h18b8] = 0; assign rom[13'h18b9] = 0; assign rom[13'h18ba] = 0; assign rom[13'h18bb] = 0; assign rom[13'h18bc] = 0; assign rom[13'h18bd] = 0; assign rom[13'h18be] = 0; assign rom[13'h18bf] = 0; assign rom[13'h18c0] = 0; assign rom[13'h18c1] = 0; assign rom[13'h18c2] = 0; assign rom[13'h18c3] = 0; assign rom[13'h18c4] = 0; assign rom[13'h18c5] = 0; assign rom[13'h18c6] = 0; assign rom[13'h18c7] = 0; assign rom[13'h18c8] = 0; assign rom[13'h18c9] = 0; assign rom[13'h18ca] = 0; assign rom[13'h18cb] = 0; assign rom[13'h18cc] = 0; assign rom[13'h18cd] = 0; assign rom[13'h18ce] = 0; assign rom[13'h18cf] = 0; assign rom[13'h18d0] = 0; assign rom[13'h18d1] = 0; assign rom[13'h18d2] = 1; assign rom[13'h18d3] = 1; assign rom[13'h18d4] = 1; assign rom[13'h18d5] = 1; assign rom[13'h18d6] = 0; assign rom[13'h18d7] = 0; assign rom[13'h18d8] = 0; assign rom[13'h18d9] = 1; assign rom[13'h18da] = 1; assign rom[13'h18db] = 0; assign rom[13'h18dc] = 0; assign rom[13'h18dd] = 1; assign rom[13'h18de] = 1; assign rom[13'h18df] = 0; assign rom[13'h18e0] = 0; assign rom[13'h18e1] = 1; assign rom[13'h18e2] = 1; assign rom[13'h18e3] = 0; assign rom[13'h18e4] = 0; assign rom[13'h18e5] = 0; assign rom[13'h18e6] = 0; assign rom[13'h18e7] = 0; assign rom[13'h18e8] = 0; assign rom[13'h18e9] = 1; assign rom[13'h18ea] = 1; assign rom[13'h18eb] = 0; assign rom[13'h18ec] = 0; assign rom[13'h18ed] = 1; assign rom[13'h18ee] = 1; assign rom[13'h18ef] = 0; assign rom[13'h18f0] = 0; assign rom[13'h18f1] = 0; assign rom[13'h18f2] = 1; assign rom[13'h18f3] = 1; assign rom[13'h18f4] = 1; assign rom[13'h18f5] = 1; assign rom[13'h18f6] = 0; assign rom[13'h18f7] = 0; assign rom[13'h18f8] = 0; assign rom[13'h18f9] = 0; assign rom[13'h18fa] = 0; assign rom[13'h18fb] = 0; assign rom[13'h18fc] = 0; assign rom[13'h18fd] = 0; assign rom[13'h18fe] = 0; assign rom[13'h18ff] = 0; assign rom[13'h1900] = 0; assign rom[13'h1901] = 0; assign rom[13'h1902] = 0; assign rom[13'h1903] = 0; assign rom[13'h1904] = 0; assign rom[13'h1905] = 1; assign rom[13'h1906] = 1; assign rom[13'h1907] = 0; assign rom[13'h1908] = 0; assign rom[13'h1909] = 0; assign rom[13'h190a] = 0; assign rom[13'h190b] = 0; assign rom[13'h190c] = 0; assign rom[13'h190d] = 1; assign rom[13'h190e] = 1; assign rom[13'h190f] = 0; assign rom[13'h1910] = 0; assign rom[13'h1911] = 0; assign rom[13'h1912] = 1; assign rom[13'h1913] = 1; assign rom[13'h1914] = 1; assign rom[13'h1915] = 1; assign rom[13'h1916] = 1; assign rom[13'h1917] = 0; assign rom[13'h1918] = 0; assign rom[13'h1919] = 1; assign rom[13'h191a] = 1; assign rom[13'h191b] = 0; assign rom[13'h191c] = 0; assign rom[13'h191d] = 1; assign rom[13'h191e] = 1; assign rom[13'h191f] = 0; assign rom[13'h1920] = 0; assign rom[13'h1921] = 1; assign rom[13'h1922] = 1; assign rom[13'h1923] = 0; assign rom[13'h1924] = 0; assign rom[13'h1925] = 1; assign rom[13'h1926] = 1; assign rom[13'h1927] = 0; assign rom[13'h1928] = 0; assign rom[13'h1929] = 1; assign rom[13'h192a] = 1; assign rom[13'h192b] = 0; assign rom[13'h192c] = 0; assign rom[13'h192d] = 1; assign rom[13'h192e] = 1; assign rom[13'h192f] = 0; assign rom[13'h1930] = 0; assign rom[13'h1931] = 0; assign rom[13'h1932] = 1; assign rom[13'h1933] = 1; assign rom[13'h1934] = 1; assign rom[13'h1935] = 1; assign rom[13'h1936] = 1; assign rom[13'h1937] = 0; assign rom[13'h1938] = 0; assign rom[13'h1939] = 0; assign rom[13'h193a] = 0; assign rom[13'h193b] = 0; assign rom[13'h193c] = 0; assign rom[13'h193d] = 0; assign rom[13'h193e] = 0; assign rom[13'h193f] = 0; assign rom[13'h1940] = 0; assign rom[13'h1941] = 0; assign rom[13'h1942] = 0; assign rom[13'h1943] = 0; assign rom[13'h1944] = 0; assign rom[13'h1945] = 0; assign rom[13'h1946] = 0; assign rom[13'h1947] = 0; assign rom[13'h1948] = 0; assign rom[13'h1949] = 0; assign rom[13'h194a] = 0; assign rom[13'h194b] = 0; assign rom[13'h194c] = 0; assign rom[13'h194d] = 0; assign rom[13'h194e] = 0; assign rom[13'h194f] = 0; assign rom[13'h1950] = 0; assign rom[13'h1951] = 0; assign rom[13'h1952] = 1; assign rom[13'h1953] = 1; assign rom[13'h1954] = 1; assign rom[13'h1955] = 1; assign rom[13'h1956] = 0; assign rom[13'h1957] = 0; assign rom[13'h1958] = 0; assign rom[13'h1959] = 1; assign rom[13'h195a] = 1; assign rom[13'h195b] = 0; assign rom[13'h195c] = 0; assign rom[13'h195d] = 1; assign rom[13'h195e] = 1; assign rom[13'h195f] = 0; assign rom[13'h1960] = 0; assign rom[13'h1961] = 1; assign rom[13'h1962] = 1; assign rom[13'h1963] = 1; assign rom[13'h1964] = 1; assign rom[13'h1965] = 1; assign rom[13'h1966] = 0; assign rom[13'h1967] = 0; assign rom[13'h1968] = 0; assign rom[13'h1969] = 1; assign rom[13'h196a] = 1; assign rom[13'h196b] = 0; assign rom[13'h196c] = 0; assign rom[13'h196d] = 0; assign rom[13'h196e] = 0; assign rom[13'h196f] = 0; assign rom[13'h1970] = 0; assign rom[13'h1971] = 0; assign rom[13'h1972] = 1; assign rom[13'h1973] = 1; assign rom[13'h1974] = 1; assign rom[13'h1975] = 1; assign rom[13'h1976] = 0; assign rom[13'h1977] = 0; assign rom[13'h1978] = 0; assign rom[13'h1979] = 0; assign rom[13'h197a] = 0; assign rom[13'h197b] = 0; assign rom[13'h197c] = 0; assign rom[13'h197d] = 0; assign rom[13'h197e] = 0; assign rom[13'h197f] = 0; assign rom[13'h1980] = 0; assign rom[13'h1981] = 0; assign rom[13'h1982] = 0; assign rom[13'h1983] = 0; assign rom[13'h1984] = 1; assign rom[13'h1985] = 1; assign rom[13'h1986] = 1; assign rom[13'h1987] = 0; assign rom[13'h1988] = 0; assign rom[13'h1989] = 0; assign rom[13'h198a] = 0; assign rom[13'h198b] = 1; assign rom[13'h198c] = 1; assign rom[13'h198d] = 0; assign rom[13'h198e] = 0; assign rom[13'h198f] = 0; assign rom[13'h1990] = 0; assign rom[13'h1991] = 0; assign rom[13'h1992] = 0; assign rom[13'h1993] = 1; assign rom[13'h1994] = 1; assign rom[13'h1995] = 0; assign rom[13'h1996] = 0; assign rom[13'h1997] = 0; assign rom[13'h1998] = 0; assign rom[13'h1999] = 0; assign rom[13'h199a] = 1; assign rom[13'h199b] = 1; assign rom[13'h199c] = 1; assign rom[13'h199d] = 1; assign rom[13'h199e] = 1; assign rom[13'h199f] = 0; assign rom[13'h19a0] = 0; assign rom[13'h19a1] = 0; assign rom[13'h19a2] = 0; assign rom[13'h19a3] = 1; assign rom[13'h19a4] = 1; assign rom[13'h19a5] = 0; assign rom[13'h19a6] = 0; assign rom[13'h19a7] = 0; assign rom[13'h19a8] = 0; assign rom[13'h19a9] = 0; assign rom[13'h19aa] = 0; assign rom[13'h19ab] = 1; assign rom[13'h19ac] = 1; assign rom[13'h19ad] = 0; assign rom[13'h19ae] = 0; assign rom[13'h19af] = 0; assign rom[13'h19b0] = 0; assign rom[13'h19b1] = 0; assign rom[13'h19b2] = 0; assign rom[13'h19b3] = 1; assign rom[13'h19b4] = 1; assign rom[13'h19b5] = 0; assign rom[13'h19b6] = 0; assign rom[13'h19b7] = 0; assign rom[13'h19b8] = 0; assign rom[13'h19b9] = 0; assign rom[13'h19ba] = 0; assign rom[13'h19bb] = 0; assign rom[13'h19bc] = 0; assign rom[13'h19bd] = 0; assign rom[13'h19be] = 0; assign rom[13'h19bf] = 0; assign rom[13'h19c0] = 0; assign rom[13'h19c1] = 0; assign rom[13'h19c2] = 0; assign rom[13'h19c3] = 0; assign rom[13'h19c4] = 0; assign rom[13'h19c5] = 0; assign rom[13'h19c6] = 0; assign rom[13'h19c7] = 0; assign rom[13'h19c8] = 0; assign rom[13'h19c9] = 0; assign rom[13'h19ca] = 0; assign rom[13'h19cb] = 0; assign rom[13'h19cc] = 0; assign rom[13'h19cd] = 0; assign rom[13'h19ce] = 0; assign rom[13'h19cf] = 0; assign rom[13'h19d0] = 0; assign rom[13'h19d1] = 0; assign rom[13'h19d2] = 1; assign rom[13'h19d3] = 1; assign rom[13'h19d4] = 1; assign rom[13'h19d5] = 1; assign rom[13'h19d6] = 1; assign rom[13'h19d7] = 0; assign rom[13'h19d8] = 0; assign rom[13'h19d9] = 1; assign rom[13'h19da] = 1; assign rom[13'h19db] = 0; assign rom[13'h19dc] = 0; assign rom[13'h19dd] = 1; assign rom[13'h19de] = 1; assign rom[13'h19df] = 0; assign rom[13'h19e0] = 0; assign rom[13'h19e1] = 1; assign rom[13'h19e2] = 1; assign rom[13'h19e3] = 0; assign rom[13'h19e4] = 0; assign rom[13'h19e5] = 1; assign rom[13'h19e6] = 1; assign rom[13'h19e7] = 0; assign rom[13'h19e8] = 0; assign rom[13'h19e9] = 0; assign rom[13'h19ea] = 1; assign rom[13'h19eb] = 1; assign rom[13'h19ec] = 1; assign rom[13'h19ed] = 1; assign rom[13'h19ee] = 1; assign rom[13'h19ef] = 0; assign rom[13'h19f0] = 0; assign rom[13'h19f1] = 0; assign rom[13'h19f2] = 0; assign rom[13'h19f3] = 0; assign rom[13'h19f4] = 0; assign rom[13'h19f5] = 1; assign rom[13'h19f6] = 1; assign rom[13'h19f7] = 0; assign rom[13'h19f8] = 0; assign rom[13'h19f9] = 0; assign rom[13'h19fa] = 1; assign rom[13'h19fb] = 1; assign rom[13'h19fc] = 1; assign rom[13'h19fd] = 1; assign rom[13'h19fe] = 0; assign rom[13'h19ff] = 0; assign rom[13'h1a00] = 0; assign rom[13'h1a01] = 1; assign rom[13'h1a02] = 1; assign rom[13'h1a03] = 0; assign rom[13'h1a04] = 0; assign rom[13'h1a05] = 0; assign rom[13'h1a06] = 0; assign rom[13'h1a07] = 0; assign rom[13'h1a08] = 0; assign rom[13'h1a09] = 1; assign rom[13'h1a0a] = 1; assign rom[13'h1a0b] = 0; assign rom[13'h1a0c] = 0; assign rom[13'h1a0d] = 0; assign rom[13'h1a0e] = 0; assign rom[13'h1a0f] = 0; assign rom[13'h1a10] = 0; assign rom[13'h1a11] = 1; assign rom[13'h1a12] = 1; assign rom[13'h1a13] = 1; assign rom[13'h1a14] = 1; assign rom[13'h1a15] = 1; assign rom[13'h1a16] = 0; assign rom[13'h1a17] = 0; assign rom[13'h1a18] = 0; assign rom[13'h1a19] = 1; assign rom[13'h1a1a] = 1; assign rom[13'h1a1b] = 0; assign rom[13'h1a1c] = 0; assign rom[13'h1a1d] = 1; assign rom[13'h1a1e] = 1; assign rom[13'h1a1f] = 0; assign rom[13'h1a20] = 0; assign rom[13'h1a21] = 1; assign rom[13'h1a22] = 1; assign rom[13'h1a23] = 0; assign rom[13'h1a24] = 0; assign rom[13'h1a25] = 1; assign rom[13'h1a26] = 1; assign rom[13'h1a27] = 0; assign rom[13'h1a28] = 0; assign rom[13'h1a29] = 1; assign rom[13'h1a2a] = 1; assign rom[13'h1a2b] = 0; assign rom[13'h1a2c] = 0; assign rom[13'h1a2d] = 1; assign rom[13'h1a2e] = 1; assign rom[13'h1a2f] = 0; assign rom[13'h1a30] = 0; assign rom[13'h1a31] = 1; assign rom[13'h1a32] = 1; assign rom[13'h1a33] = 0; assign rom[13'h1a34] = 0; assign rom[13'h1a35] = 1; assign rom[13'h1a36] = 1; assign rom[13'h1a37] = 0; assign rom[13'h1a38] = 0; assign rom[13'h1a39] = 0; assign rom[13'h1a3a] = 0; assign rom[13'h1a3b] = 0; assign rom[13'h1a3c] = 0; assign rom[13'h1a3d] = 0; assign rom[13'h1a3e] = 0; assign rom[13'h1a3f] = 0; assign rom[13'h1a40] = 0; assign rom[13'h1a41] = 0; assign rom[13'h1a42] = 0; assign rom[13'h1a43] = 1; assign rom[13'h1a44] = 1; assign rom[13'h1a45] = 0; assign rom[13'h1a46] = 0; assign rom[13'h1a47] = 0; assign rom[13'h1a48] = 0; assign rom[13'h1a49] = 0; assign rom[13'h1a4a] = 0; assign rom[13'h1a4b] = 0; assign rom[13'h1a4c] = 0; assign rom[13'h1a4d] = 0; assign rom[13'h1a4e] = 0; assign rom[13'h1a4f] = 0; assign rom[13'h1a50] = 0; assign rom[13'h1a51] = 0; assign rom[13'h1a52] = 0; assign rom[13'h1a53] = 1; assign rom[13'h1a54] = 1; assign rom[13'h1a55] = 0; assign rom[13'h1a56] = 0; assign rom[13'h1a57] = 0; assign rom[13'h1a58] = 0; assign rom[13'h1a59] = 0; assign rom[13'h1a5a] = 0; assign rom[13'h1a5b] = 1; assign rom[13'h1a5c] = 1; assign rom[13'h1a5d] = 0; assign rom[13'h1a5e] = 0; assign rom[13'h1a5f] = 0; assign rom[13'h1a60] = 0; assign rom[13'h1a61] = 0; assign rom[13'h1a62] = 0; assign rom[13'h1a63] = 1; assign rom[13'h1a64] = 1; assign rom[13'h1a65] = 0; assign rom[13'h1a66] = 0; assign rom[13'h1a67] = 0; assign rom[13'h1a68] = 0; assign rom[13'h1a69] = 0; assign rom[13'h1a6a] = 0; assign rom[13'h1a6b] = 1; assign rom[13'h1a6c] = 1; assign rom[13'h1a6d] = 0; assign rom[13'h1a6e] = 0; assign rom[13'h1a6f] = 0; assign rom[13'h1a70] = 0; assign rom[13'h1a71] = 0; assign rom[13'h1a72] = 0; assign rom[13'h1a73] = 1; assign rom[13'h1a74] = 1; assign rom[13'h1a75] = 0; assign rom[13'h1a76] = 0; assign rom[13'h1a77] = 0; assign rom[13'h1a78] = 0; assign rom[13'h1a79] = 0; assign rom[13'h1a7a] = 0; assign rom[13'h1a7b] = 0; assign rom[13'h1a7c] = 0; assign rom[13'h1a7d] = 0; assign rom[13'h1a7e] = 0; assign rom[13'h1a7f] = 0; assign rom[13'h1a80] = 0; assign rom[13'h1a81] = 0; assign rom[13'h1a82] = 0; assign rom[13'h1a83] = 1; assign rom[13'h1a84] = 1; assign rom[13'h1a85] = 0; assign rom[13'h1a86] = 0; assign rom[13'h1a87] = 0; assign rom[13'h1a88] = 0; assign rom[13'h1a89] = 0; assign rom[13'h1a8a] = 0; assign rom[13'h1a8b] = 0; assign rom[13'h1a8c] = 0; assign rom[13'h1a8d] = 0; assign rom[13'h1a8e] = 0; assign rom[13'h1a8f] = 0; assign rom[13'h1a90] = 0; assign rom[13'h1a91] = 0; assign rom[13'h1a92] = 0; assign rom[13'h1a93] = 1; assign rom[13'h1a94] = 1; assign rom[13'h1a95] = 0; assign rom[13'h1a96] = 0; assign rom[13'h1a97] = 0; assign rom[13'h1a98] = 0; assign rom[13'h1a99] = 0; assign rom[13'h1a9a] = 0; assign rom[13'h1a9b] = 1; assign rom[13'h1a9c] = 1; assign rom[13'h1a9d] = 0; assign rom[13'h1a9e] = 0; assign rom[13'h1a9f] = 0; assign rom[13'h1aa0] = 0; assign rom[13'h1aa1] = 0; assign rom[13'h1aa2] = 0; assign rom[13'h1aa3] = 1; assign rom[13'h1aa4] = 1; assign rom[13'h1aa5] = 0; assign rom[13'h1aa6] = 0; assign rom[13'h1aa7] = 0; assign rom[13'h1aa8] = 0; assign rom[13'h1aa9] = 0; assign rom[13'h1aaa] = 0; assign rom[13'h1aab] = 1; assign rom[13'h1aac] = 1; assign rom[13'h1aad] = 0; assign rom[13'h1aae] = 0; assign rom[13'h1aaf] = 0; assign rom[13'h1ab0] = 0; assign rom[13'h1ab1] = 0; assign rom[13'h1ab2] = 0; assign rom[13'h1ab3] = 1; assign rom[13'h1ab4] = 1; assign rom[13'h1ab5] = 0; assign rom[13'h1ab6] = 0; assign rom[13'h1ab7] = 0; assign rom[13'h1ab8] = 0; assign rom[13'h1ab9] = 1; assign rom[13'h1aba] = 1; assign rom[13'h1abb] = 1; assign rom[13'h1abc] = 0; assign rom[13'h1abd] = 0; assign rom[13'h1abe] = 0; assign rom[13'h1abf] = 0; assign rom[13'h1ac0] = 0; assign rom[13'h1ac1] = 1; assign rom[13'h1ac2] = 1; assign rom[13'h1ac3] = 0; assign rom[13'h1ac4] = 0; assign rom[13'h1ac5] = 0; assign rom[13'h1ac6] = 0; assign rom[13'h1ac7] = 0; assign rom[13'h1ac8] = 0; assign rom[13'h1ac9] = 1; assign rom[13'h1aca] = 1; assign rom[13'h1acb] = 0; assign rom[13'h1acc] = 0; assign rom[13'h1acd] = 0; assign rom[13'h1ace] = 0; assign rom[13'h1acf] = 0; assign rom[13'h1ad0] = 0; assign rom[13'h1ad1] = 1; assign rom[13'h1ad2] = 1; assign rom[13'h1ad3] = 0; assign rom[13'h1ad4] = 0; assign rom[13'h1ad5] = 1; assign rom[13'h1ad6] = 1; assign rom[13'h1ad7] = 0; assign rom[13'h1ad8] = 0; assign rom[13'h1ad9] = 1; assign rom[13'h1ada] = 1; assign rom[13'h1adb] = 0; assign rom[13'h1adc] = 1; assign rom[13'h1add] = 1; assign rom[13'h1ade] = 0; assign rom[13'h1adf] = 0; assign rom[13'h1ae0] = 0; assign rom[13'h1ae1] = 1; assign rom[13'h1ae2] = 1; assign rom[13'h1ae3] = 1; assign rom[13'h1ae4] = 1; assign rom[13'h1ae5] = 0; assign rom[13'h1ae6] = 0; assign rom[13'h1ae7] = 0; assign rom[13'h1ae8] = 0; assign rom[13'h1ae9] = 1; assign rom[13'h1aea] = 1; assign rom[13'h1aeb] = 0; assign rom[13'h1aec] = 1; assign rom[13'h1aed] = 1; assign rom[13'h1aee] = 0; assign rom[13'h1aef] = 0; assign rom[13'h1af0] = 0; assign rom[13'h1af1] = 1; assign rom[13'h1af2] = 1; assign rom[13'h1af3] = 0; assign rom[13'h1af4] = 0; assign rom[13'h1af5] = 1; assign rom[13'h1af6] = 1; assign rom[13'h1af7] = 0; assign rom[13'h1af8] = 0; assign rom[13'h1af9] = 0; assign rom[13'h1afa] = 0; assign rom[13'h1afb] = 0; assign rom[13'h1afc] = 0; assign rom[13'h1afd] = 0; assign rom[13'h1afe] = 0; assign rom[13'h1aff] = 0; assign rom[13'h1b00] = 0; assign rom[13'h1b01] = 0; assign rom[13'h1b02] = 1; assign rom[13'h1b03] = 1; assign rom[13'h1b04] = 0; assign rom[13'h1b05] = 0; assign rom[13'h1b06] = 0; assign rom[13'h1b07] = 0; assign rom[13'h1b08] = 0; assign rom[13'h1b09] = 0; assign rom[13'h1b0a] = 1; assign rom[13'h1b0b] = 1; assign rom[13'h1b0c] = 0; assign rom[13'h1b0d] = 0; assign rom[13'h1b0e] = 0; assign rom[13'h1b0f] = 0; assign rom[13'h1b10] = 0; assign rom[13'h1b11] = 0; assign rom[13'h1b12] = 1; assign rom[13'h1b13] = 1; assign rom[13'h1b14] = 0; assign rom[13'h1b15] = 0; assign rom[13'h1b16] = 0; assign rom[13'h1b17] = 0; assign rom[13'h1b18] = 0; assign rom[13'h1b19] = 0; assign rom[13'h1b1a] = 1; assign rom[13'h1b1b] = 1; assign rom[13'h1b1c] = 0; assign rom[13'h1b1d] = 0; assign rom[13'h1b1e] = 0; assign rom[13'h1b1f] = 0; assign rom[13'h1b20] = 0; assign rom[13'h1b21] = 0; assign rom[13'h1b22] = 1; assign rom[13'h1b23] = 1; assign rom[13'h1b24] = 0; assign rom[13'h1b25] = 0; assign rom[13'h1b26] = 0; assign rom[13'h1b27] = 0; assign rom[13'h1b28] = 0; assign rom[13'h1b29] = 0; assign rom[13'h1b2a] = 1; assign rom[13'h1b2b] = 1; assign rom[13'h1b2c] = 0; assign rom[13'h1b2d] = 0; assign rom[13'h1b2e] = 0; assign rom[13'h1b2f] = 0; assign rom[13'h1b30] = 0; assign rom[13'h1b31] = 0; assign rom[13'h1b32] = 0; assign rom[13'h1b33] = 1; assign rom[13'h1b34] = 1; assign rom[13'h1b35] = 1; assign rom[13'h1b36] = 0; assign rom[13'h1b37] = 0; assign rom[13'h1b38] = 0; assign rom[13'h1b39] = 0; assign rom[13'h1b3a] = 0; assign rom[13'h1b3b] = 0; assign rom[13'h1b3c] = 0; assign rom[13'h1b3d] = 0; assign rom[13'h1b3e] = 0; assign rom[13'h1b3f] = 0; assign rom[13'h1b40] = 0; assign rom[13'h1b41] = 0; assign rom[13'h1b42] = 0; assign rom[13'h1b43] = 0; assign rom[13'h1b44] = 0; assign rom[13'h1b45] = 0; assign rom[13'h1b46] = 0; assign rom[13'h1b47] = 0; assign rom[13'h1b48] = 0; assign rom[13'h1b49] = 0; assign rom[13'h1b4a] = 0; assign rom[13'h1b4b] = 0; assign rom[13'h1b4c] = 0; assign rom[13'h1b4d] = 0; assign rom[13'h1b4e] = 0; assign rom[13'h1b4f] = 0; assign rom[13'h1b50] = 1; assign rom[13'h1b51] = 1; assign rom[13'h1b52] = 0; assign rom[13'h1b53] = 0; assign rom[13'h1b54] = 1; assign rom[13'h1b55] = 1; assign rom[13'h1b56] = 0; assign rom[13'h1b57] = 0; assign rom[13'h1b58] = 1; assign rom[13'h1b59] = 1; assign rom[13'h1b5a] = 1; assign rom[13'h1b5b] = 1; assign rom[13'h1b5c] = 1; assign rom[13'h1b5d] = 1; assign rom[13'h1b5e] = 1; assign rom[13'h1b5f] = 0; assign rom[13'h1b60] = 1; assign rom[13'h1b61] = 1; assign rom[13'h1b62] = 0; assign rom[13'h1b63] = 1; assign rom[13'h1b64] = 0; assign rom[13'h1b65] = 1; assign rom[13'h1b66] = 1; assign rom[13'h1b67] = 0; assign rom[13'h1b68] = 1; assign rom[13'h1b69] = 1; assign rom[13'h1b6a] = 0; assign rom[13'h1b6b] = 0; assign rom[13'h1b6c] = 0; assign rom[13'h1b6d] = 1; assign rom[13'h1b6e] = 1; assign rom[13'h1b6f] = 0; assign rom[13'h1b70] = 1; assign rom[13'h1b71] = 1; assign rom[13'h1b72] = 0; assign rom[13'h1b73] = 0; assign rom[13'h1b74] = 0; assign rom[13'h1b75] = 1; assign rom[13'h1b76] = 1; assign rom[13'h1b77] = 0; assign rom[13'h1b78] = 0; assign rom[13'h1b79] = 0; assign rom[13'h1b7a] = 0; assign rom[13'h1b7b] = 0; assign rom[13'h1b7c] = 0; assign rom[13'h1b7d] = 0; assign rom[13'h1b7e] = 0; assign rom[13'h1b7f] = 0; assign rom[13'h1b80] = 0; assign rom[13'h1b81] = 0; assign rom[13'h1b82] = 0; assign rom[13'h1b83] = 0; assign rom[13'h1b84] = 0; assign rom[13'h1b85] = 0; assign rom[13'h1b86] = 0; assign rom[13'h1b87] = 0; assign rom[13'h1b88] = 0; assign rom[13'h1b89] = 0; assign rom[13'h1b8a] = 0; assign rom[13'h1b8b] = 0; assign rom[13'h1b8c] = 0; assign rom[13'h1b8d] = 0; assign rom[13'h1b8e] = 0; assign rom[13'h1b8f] = 0; assign rom[13'h1b90] = 0; assign rom[13'h1b91] = 1; assign rom[13'h1b92] = 1; assign rom[13'h1b93] = 1; assign rom[13'h1b94] = 1; assign rom[13'h1b95] = 1; assign rom[13'h1b96] = 0; assign rom[13'h1b97] = 0; assign rom[13'h1b98] = 0; assign rom[13'h1b99] = 1; assign rom[13'h1b9a] = 1; assign rom[13'h1b9b] = 0; assign rom[13'h1b9c] = 0; assign rom[13'h1b9d] = 1; assign rom[13'h1b9e] = 1; assign rom[13'h1b9f] = 0; assign rom[13'h1ba0] = 0; assign rom[13'h1ba1] = 1; assign rom[13'h1ba2] = 1; assign rom[13'h1ba3] = 0; assign rom[13'h1ba4] = 0; assign rom[13'h1ba5] = 1; assign rom[13'h1ba6] = 1; assign rom[13'h1ba7] = 0; assign rom[13'h1ba8] = 0; assign rom[13'h1ba9] = 1; assign rom[13'h1baa] = 1; assign rom[13'h1bab] = 0; assign rom[13'h1bac] = 0; assign rom[13'h1bad] = 1; assign rom[13'h1bae] = 1; assign rom[13'h1baf] = 0; assign rom[13'h1bb0] = 0; assign rom[13'h1bb1] = 1; assign rom[13'h1bb2] = 1; assign rom[13'h1bb3] = 0; assign rom[13'h1bb4] = 0; assign rom[13'h1bb5] = 1; assign rom[13'h1bb6] = 1; assign rom[13'h1bb7] = 0; assign rom[13'h1bb8] = 0; assign rom[13'h1bb9] = 0; assign rom[13'h1bba] = 0; assign rom[13'h1bbb] = 0; assign rom[13'h1bbc] = 0; assign rom[13'h1bbd] = 0; assign rom[13'h1bbe] = 0; assign rom[13'h1bbf] = 0; assign rom[13'h1bc0] = 0; assign rom[13'h1bc1] = 0; assign rom[13'h1bc2] = 0; assign rom[13'h1bc3] = 0; assign rom[13'h1bc4] = 0; assign rom[13'h1bc5] = 0; assign rom[13'h1bc6] = 0; assign rom[13'h1bc7] = 0; assign rom[13'h1bc8] = 0; assign rom[13'h1bc9] = 0; assign rom[13'h1bca] = 0; assign rom[13'h1bcb] = 0; assign rom[13'h1bcc] = 0; assign rom[13'h1bcd] = 0; assign rom[13'h1bce] = 0; assign rom[13'h1bcf] = 0; assign rom[13'h1bd0] = 0; assign rom[13'h1bd1] = 0; assign rom[13'h1bd2] = 1; assign rom[13'h1bd3] = 1; assign rom[13'h1bd4] = 1; assign rom[13'h1bd5] = 1; assign rom[13'h1bd6] = 0; assign rom[13'h1bd7] = 0; assign rom[13'h1bd8] = 0; assign rom[13'h1bd9] = 1; assign rom[13'h1bda] = 1; assign rom[13'h1bdb] = 0; assign rom[13'h1bdc] = 0; assign rom[13'h1bdd] = 1; assign rom[13'h1bde] = 1; assign rom[13'h1bdf] = 0; assign rom[13'h1be0] = 0; assign rom[13'h1be1] = 1; assign rom[13'h1be2] = 1; assign rom[13'h1be3] = 0; assign rom[13'h1be4] = 0; assign rom[13'h1be5] = 1; assign rom[13'h1be6] = 1; assign rom[13'h1be7] = 0; assign rom[13'h1be8] = 0; assign rom[13'h1be9] = 1; assign rom[13'h1bea] = 1; assign rom[13'h1beb] = 0; assign rom[13'h1bec] = 0; assign rom[13'h1bed] = 1; assign rom[13'h1bee] = 1; assign rom[13'h1bef] = 0; assign rom[13'h1bf0] = 0; assign rom[13'h1bf1] = 0; assign rom[13'h1bf2] = 1; assign rom[13'h1bf3] = 1; assign rom[13'h1bf4] = 1; assign rom[13'h1bf5] = 1; assign rom[13'h1bf6] = 0; assign rom[13'h1bf7] = 0; assign rom[13'h1bf8] = 0; assign rom[13'h1bf9] = 0; assign rom[13'h1bfa] = 0; assign rom[13'h1bfb] = 0; assign rom[13'h1bfc] = 0; assign rom[13'h1bfd] = 0; assign rom[13'h1bfe] = 0; assign rom[13'h1bff] = 0; assign rom[13'h1c00] = 0; assign rom[13'h1c01] = 0; assign rom[13'h1c02] = 0; assign rom[13'h1c03] = 0; assign rom[13'h1c04] = 0; assign rom[13'h1c05] = 0; assign rom[13'h1c06] = 0; assign rom[13'h1c07] = 0; assign rom[13'h1c08] = 0; assign rom[13'h1c09] = 0; assign rom[13'h1c0a] = 0; assign rom[13'h1c0b] = 0; assign rom[13'h1c0c] = 0; assign rom[13'h1c0d] = 0; assign rom[13'h1c0e] = 0; assign rom[13'h1c0f] = 0; assign rom[13'h1c10] = 0; assign rom[13'h1c11] = 1; assign rom[13'h1c12] = 1; assign rom[13'h1c13] = 1; assign rom[13'h1c14] = 1; assign rom[13'h1c15] = 1; assign rom[13'h1c16] = 0; assign rom[13'h1c17] = 0; assign rom[13'h1c18] = 0; assign rom[13'h1c19] = 1; assign rom[13'h1c1a] = 1; assign rom[13'h1c1b] = 0; assign rom[13'h1c1c] = 0; assign rom[13'h1c1d] = 1; assign rom[13'h1c1e] = 1; assign rom[13'h1c1f] = 0; assign rom[13'h1c20] = 0; assign rom[13'h1c21] = 1; assign rom[13'h1c22] = 1; assign rom[13'h1c23] = 0; assign rom[13'h1c24] = 0; assign rom[13'h1c25] = 1; assign rom[13'h1c26] = 1; assign rom[13'h1c27] = 0; assign rom[13'h1c28] = 0; assign rom[13'h1c29] = 1; assign rom[13'h1c2a] = 1; assign rom[13'h1c2b] = 1; assign rom[13'h1c2c] = 1; assign rom[13'h1c2d] = 1; assign rom[13'h1c2e] = 0; assign rom[13'h1c2f] = 0; assign rom[13'h1c30] = 0; assign rom[13'h1c31] = 1; assign rom[13'h1c32] = 1; assign rom[13'h1c33] = 0; assign rom[13'h1c34] = 0; assign rom[13'h1c35] = 0; assign rom[13'h1c36] = 0; assign rom[13'h1c37] = 0; assign rom[13'h1c38] = 0; assign rom[13'h1c39] = 1; assign rom[13'h1c3a] = 1; assign rom[13'h1c3b] = 0; assign rom[13'h1c3c] = 0; assign rom[13'h1c3d] = 0; assign rom[13'h1c3e] = 0; assign rom[13'h1c3f] = 0; assign rom[13'h1c40] = 0; assign rom[13'h1c41] = 0; assign rom[13'h1c42] = 0; assign rom[13'h1c43] = 0; assign rom[13'h1c44] = 0; assign rom[13'h1c45] = 0; assign rom[13'h1c46] = 0; assign rom[13'h1c47] = 0; assign rom[13'h1c48] = 0; assign rom[13'h1c49] = 0; assign rom[13'h1c4a] = 0; assign rom[13'h1c4b] = 0; assign rom[13'h1c4c] = 0; assign rom[13'h1c4d] = 0; assign rom[13'h1c4e] = 0; assign rom[13'h1c4f] = 0; assign rom[13'h1c50] = 0; assign rom[13'h1c51] = 0; assign rom[13'h1c52] = 1; assign rom[13'h1c53] = 1; assign rom[13'h1c54] = 1; assign rom[13'h1c55] = 1; assign rom[13'h1c56] = 1; assign rom[13'h1c57] = 0; assign rom[13'h1c58] = 0; assign rom[13'h1c59] = 1; assign rom[13'h1c5a] = 1; assign rom[13'h1c5b] = 0; assign rom[13'h1c5c] = 0; assign rom[13'h1c5d] = 1; assign rom[13'h1c5e] = 1; assign rom[13'h1c5f] = 0; assign rom[13'h1c60] = 0; assign rom[13'h1c61] = 1; assign rom[13'h1c62] = 1; assign rom[13'h1c63] = 0; assign rom[13'h1c64] = 0; assign rom[13'h1c65] = 1; assign rom[13'h1c66] = 1; assign rom[13'h1c67] = 0; assign rom[13'h1c68] = 0; assign rom[13'h1c69] = 0; assign rom[13'h1c6a] = 1; assign rom[13'h1c6b] = 1; assign rom[13'h1c6c] = 1; assign rom[13'h1c6d] = 1; assign rom[13'h1c6e] = 1; assign rom[13'h1c6f] = 0; assign rom[13'h1c70] = 0; assign rom[13'h1c71] = 0; assign rom[13'h1c72] = 0; assign rom[13'h1c73] = 0; assign rom[13'h1c74] = 0; assign rom[13'h1c75] = 1; assign rom[13'h1c76] = 1; assign rom[13'h1c77] = 0; assign rom[13'h1c78] = 0; assign rom[13'h1c79] = 0; assign rom[13'h1c7a] = 0; assign rom[13'h1c7b] = 0; assign rom[13'h1c7c] = 0; assign rom[13'h1c7d] = 1; assign rom[13'h1c7e] = 1; assign rom[13'h1c7f] = 0; assign rom[13'h1c80] = 0; assign rom[13'h1c81] = 0; assign rom[13'h1c82] = 0; assign rom[13'h1c83] = 0; assign rom[13'h1c84] = 0; assign rom[13'h1c85] = 0; assign rom[13'h1c86] = 0; assign rom[13'h1c87] = 0; assign rom[13'h1c88] = 0; assign rom[13'h1c89] = 0; assign rom[13'h1c8a] = 0; assign rom[13'h1c8b] = 0; assign rom[13'h1c8c] = 0; assign rom[13'h1c8d] = 0; assign rom[13'h1c8e] = 0; assign rom[13'h1c8f] = 0; assign rom[13'h1c90] = 0; assign rom[13'h1c91] = 0; assign rom[13'h1c92] = 1; assign rom[13'h1c93] = 1; assign rom[13'h1c94] = 0; assign rom[13'h1c95] = 1; assign rom[13'h1c96] = 1; assign rom[13'h1c97] = 0; assign rom[13'h1c98] = 0; assign rom[13'h1c99] = 0; assign rom[13'h1c9a] = 1; assign rom[13'h1c9b] = 1; assign rom[13'h1c9c] = 1; assign rom[13'h1c9d] = 0; assign rom[13'h1c9e] = 0; assign rom[13'h1c9f] = 0; assign rom[13'h1ca0] = 0; assign rom[13'h1ca1] = 0; assign rom[13'h1ca2] = 1; assign rom[13'h1ca3] = 1; assign rom[13'h1ca4] = 0; assign rom[13'h1ca5] = 0; assign rom[13'h1ca6] = 0; assign rom[13'h1ca7] = 0; assign rom[13'h1ca8] = 0; assign rom[13'h1ca9] = 0; assign rom[13'h1caa] = 1; assign rom[13'h1cab] = 1; assign rom[13'h1cac] = 0; assign rom[13'h1cad] = 0; assign rom[13'h1cae] = 0; assign rom[13'h1caf] = 0; assign rom[13'h1cb0] = 0; assign rom[13'h1cb1] = 0; assign rom[13'h1cb2] = 1; assign rom[13'h1cb3] = 1; assign rom[13'h1cb4] = 0; assign rom[13'h1cb5] = 0; assign rom[13'h1cb6] = 0; assign rom[13'h1cb7] = 0; assign rom[13'h1cb8] = 0; assign rom[13'h1cb9] = 0; assign rom[13'h1cba] = 0; assign rom[13'h1cbb] = 0; assign rom[13'h1cbc] = 0; assign rom[13'h1cbd] = 0; assign rom[13'h1cbe] = 0; assign rom[13'h1cbf] = 0; assign rom[13'h1cc0] = 0; assign rom[13'h1cc1] = 0; assign rom[13'h1cc2] = 0; assign rom[13'h1cc3] = 0; assign rom[13'h1cc4] = 0; assign rom[13'h1cc5] = 0; assign rom[13'h1cc6] = 0; assign rom[13'h1cc7] = 0; assign rom[13'h1cc8] = 0; assign rom[13'h1cc9] = 0; assign rom[13'h1cca] = 0; assign rom[13'h1ccb] = 0; assign rom[13'h1ccc] = 0; assign rom[13'h1ccd] = 0; assign rom[13'h1cce] = 0; assign rom[13'h1ccf] = 0; assign rom[13'h1cd0] = 0; assign rom[13'h1cd1] = 0; assign rom[13'h1cd2] = 1; assign rom[13'h1cd3] = 1; assign rom[13'h1cd4] = 1; assign rom[13'h1cd5] = 1; assign rom[13'h1cd6] = 1; assign rom[13'h1cd7] = 0; assign rom[13'h1cd8] = 0; assign rom[13'h1cd9] = 1; assign rom[13'h1cda] = 1; assign rom[13'h1cdb] = 0; assign rom[13'h1cdc] = 0; assign rom[13'h1cdd] = 0; assign rom[13'h1cde] = 0; assign rom[13'h1cdf] = 0; assign rom[13'h1ce0] = 0; assign rom[13'h1ce1] = 0; assign rom[13'h1ce2] = 1; assign rom[13'h1ce3] = 1; assign rom[13'h1ce4] = 1; assign rom[13'h1ce5] = 1; assign rom[13'h1ce6] = 0; assign rom[13'h1ce7] = 0; assign rom[13'h1ce8] = 0; assign rom[13'h1ce9] = 0; assign rom[13'h1cea] = 0; assign rom[13'h1ceb] = 0; assign rom[13'h1cec] = 0; assign rom[13'h1ced] = 1; assign rom[13'h1cee] = 1; assign rom[13'h1cef] = 0; assign rom[13'h1cf0] = 0; assign rom[13'h1cf1] = 1; assign rom[13'h1cf2] = 1; assign rom[13'h1cf3] = 1; assign rom[13'h1cf4] = 1; assign rom[13'h1cf5] = 1; assign rom[13'h1cf6] = 0; assign rom[13'h1cf7] = 0; assign rom[13'h1cf8] = 0; assign rom[13'h1cf9] = 0; assign rom[13'h1cfa] = 0; assign rom[13'h1cfb] = 0; assign rom[13'h1cfc] = 0; assign rom[13'h1cfd] = 0; assign rom[13'h1cfe] = 0; assign rom[13'h1cff] = 0; assign rom[13'h1d00] = 0; assign rom[13'h1d01] = 0; assign rom[13'h1d02] = 0; assign rom[13'h1d03] = 1; assign rom[13'h1d04] = 1; assign rom[13'h1d05] = 0; assign rom[13'h1d06] = 0; assign rom[13'h1d07] = 0; assign rom[13'h1d08] = 0; assign rom[13'h1d09] = 0; assign rom[13'h1d0a] = 0; assign rom[13'h1d0b] = 1; assign rom[13'h1d0c] = 1; assign rom[13'h1d0d] = 0; assign rom[13'h1d0e] = 0; assign rom[13'h1d0f] = 0; assign rom[13'h1d10] = 0; assign rom[13'h1d11] = 0; assign rom[13'h1d12] = 1; assign rom[13'h1d13] = 1; assign rom[13'h1d14] = 1; assign rom[13'h1d15] = 1; assign rom[13'h1d16] = 0; assign rom[13'h1d17] = 0; assign rom[13'h1d18] = 0; assign rom[13'h1d19] = 0; assign rom[13'h1d1a] = 0; assign rom[13'h1d1b] = 1; assign rom[13'h1d1c] = 1; assign rom[13'h1d1d] = 0; assign rom[13'h1d1e] = 0; assign rom[13'h1d1f] = 0; assign rom[13'h1d20] = 0; assign rom[13'h1d21] = 0; assign rom[13'h1d22] = 0; assign rom[13'h1d23] = 1; assign rom[13'h1d24] = 1; assign rom[13'h1d25] = 0; assign rom[13'h1d26] = 0; assign rom[13'h1d27] = 0; assign rom[13'h1d28] = 0; assign rom[13'h1d29] = 0; assign rom[13'h1d2a] = 0; assign rom[13'h1d2b] = 1; assign rom[13'h1d2c] = 1; assign rom[13'h1d2d] = 0; assign rom[13'h1d2e] = 0; assign rom[13'h1d2f] = 0; assign rom[13'h1d30] = 0; assign rom[13'h1d31] = 0; assign rom[13'h1d32] = 0; assign rom[13'h1d33] = 0; assign rom[13'h1d34] = 1; assign rom[13'h1d35] = 1; assign rom[13'h1d36] = 0; assign rom[13'h1d37] = 0; assign rom[13'h1d38] = 0; assign rom[13'h1d39] = 0; assign rom[13'h1d3a] = 0; assign rom[13'h1d3b] = 0; assign rom[13'h1d3c] = 0; assign rom[13'h1d3d] = 0; assign rom[13'h1d3e] = 0; assign rom[13'h1d3f] = 0; assign rom[13'h1d40] = 0; assign rom[13'h1d41] = 0; assign rom[13'h1d42] = 0; assign rom[13'h1d43] = 0; assign rom[13'h1d44] = 0; assign rom[13'h1d45] = 0; assign rom[13'h1d46] = 0; assign rom[13'h1d47] = 0; assign rom[13'h1d48] = 0; assign rom[13'h1d49] = 0; assign rom[13'h1d4a] = 0; assign rom[13'h1d4b] = 0; assign rom[13'h1d4c] = 0; assign rom[13'h1d4d] = 0; assign rom[13'h1d4e] = 0; assign rom[13'h1d4f] = 0; assign rom[13'h1d50] = 0; assign rom[13'h1d51] = 1; assign rom[13'h1d52] = 1; assign rom[13'h1d53] = 0; assign rom[13'h1d54] = 0; assign rom[13'h1d55] = 1; assign rom[13'h1d56] = 1; assign rom[13'h1d57] = 0; assign rom[13'h1d58] = 0; assign rom[13'h1d59] = 1; assign rom[13'h1d5a] = 1; assign rom[13'h1d5b] = 0; assign rom[13'h1d5c] = 0; assign rom[13'h1d5d] = 1; assign rom[13'h1d5e] = 1; assign rom[13'h1d5f] = 0; assign rom[13'h1d60] = 0; assign rom[13'h1d61] = 1; assign rom[13'h1d62] = 1; assign rom[13'h1d63] = 0; assign rom[13'h1d64] = 0; assign rom[13'h1d65] = 1; assign rom[13'h1d66] = 1; assign rom[13'h1d67] = 0; assign rom[13'h1d68] = 0; assign rom[13'h1d69] = 1; assign rom[13'h1d6a] = 1; assign rom[13'h1d6b] = 0; assign rom[13'h1d6c] = 0; assign rom[13'h1d6d] = 1; assign rom[13'h1d6e] = 1; assign rom[13'h1d6f] = 0; assign rom[13'h1d70] = 0; assign rom[13'h1d71] = 0; assign rom[13'h1d72] = 1; assign rom[13'h1d73] = 1; assign rom[13'h1d74] = 1; assign rom[13'h1d75] = 1; assign rom[13'h1d76] = 0; assign rom[13'h1d77] = 0; assign rom[13'h1d78] = 0; assign rom[13'h1d79] = 0; assign rom[13'h1d7a] = 0; assign rom[13'h1d7b] = 0; assign rom[13'h1d7c] = 0; assign rom[13'h1d7d] = 0; assign rom[13'h1d7e] = 0; assign rom[13'h1d7f] = 0; assign rom[13'h1d80] = 0; assign rom[13'h1d81] = 0; assign rom[13'h1d82] = 0; assign rom[13'h1d83] = 0; assign rom[13'h1d84] = 0; assign rom[13'h1d85] = 0; assign rom[13'h1d86] = 0; assign rom[13'h1d87] = 0; assign rom[13'h1d88] = 0; assign rom[13'h1d89] = 0; assign rom[13'h1d8a] = 0; assign rom[13'h1d8b] = 0; assign rom[13'h1d8c] = 0; assign rom[13'h1d8d] = 0; assign rom[13'h1d8e] = 0; assign rom[13'h1d8f] = 0; assign rom[13'h1d90] = 0; assign rom[13'h1d91] = 1; assign rom[13'h1d92] = 1; assign rom[13'h1d93] = 0; assign rom[13'h1d94] = 0; assign rom[13'h1d95] = 1; assign rom[13'h1d96] = 1; assign rom[13'h1d97] = 0; assign rom[13'h1d98] = 0; assign rom[13'h1d99] = 1; assign rom[13'h1d9a] = 1; assign rom[13'h1d9b] = 0; assign rom[13'h1d9c] = 0; assign rom[13'h1d9d] = 1; assign rom[13'h1d9e] = 1; assign rom[13'h1d9f] = 0; assign rom[13'h1da0] = 0; assign rom[13'h1da1] = 1; assign rom[13'h1da2] = 1; assign rom[13'h1da3] = 0; assign rom[13'h1da4] = 0; assign rom[13'h1da5] = 1; assign rom[13'h1da6] = 1; assign rom[13'h1da7] = 0; assign rom[13'h1da8] = 0; assign rom[13'h1da9] = 0; assign rom[13'h1daa] = 1; assign rom[13'h1dab] = 1; assign rom[13'h1dac] = 1; assign rom[13'h1dad] = 1; assign rom[13'h1dae] = 0; assign rom[13'h1daf] = 0; assign rom[13'h1db0] = 0; assign rom[13'h1db1] = 0; assign rom[13'h1db2] = 0; assign rom[13'h1db3] = 1; assign rom[13'h1db4] = 1; assign rom[13'h1db5] = 0; assign rom[13'h1db6] = 0; assign rom[13'h1db7] = 0; assign rom[13'h1db8] = 0; assign rom[13'h1db9] = 0; assign rom[13'h1dba] = 0; assign rom[13'h1dbb] = 0; assign rom[13'h1dbc] = 0; assign rom[13'h1dbd] = 0; assign rom[13'h1dbe] = 0; assign rom[13'h1dbf] = 0; assign rom[13'h1dc0] = 0; assign rom[13'h1dc1] = 0; assign rom[13'h1dc2] = 0; assign rom[13'h1dc3] = 0; assign rom[13'h1dc4] = 0; assign rom[13'h1dc5] = 0; assign rom[13'h1dc6] = 0; assign rom[13'h1dc7] = 0; assign rom[13'h1dc8] = 0; assign rom[13'h1dc9] = 0; assign rom[13'h1dca] = 0; assign rom[13'h1dcb] = 0; assign rom[13'h1dcc] = 0; assign rom[13'h1dcd] = 0; assign rom[13'h1dce] = 0; assign rom[13'h1dcf] = 0; assign rom[13'h1dd0] = 1; assign rom[13'h1dd1] = 1; assign rom[13'h1dd2] = 0; assign rom[13'h1dd3] = 0; assign rom[13'h1dd4] = 0; assign rom[13'h1dd5] = 1; assign rom[13'h1dd6] = 1; assign rom[13'h1dd7] = 0; assign rom[13'h1dd8] = 1; assign rom[13'h1dd9] = 1; assign rom[13'h1dda] = 0; assign rom[13'h1ddb] = 1; assign rom[13'h1ddc] = 0; assign rom[13'h1ddd] = 1; assign rom[13'h1dde] = 1; assign rom[13'h1ddf] = 0; assign rom[13'h1de0] = 1; assign rom[13'h1de1] = 1; assign rom[13'h1de2] = 0; assign rom[13'h1de3] = 1; assign rom[13'h1de4] = 0; assign rom[13'h1de5] = 1; assign rom[13'h1de6] = 1; assign rom[13'h1de7] = 0; assign rom[13'h1de8] = 0; assign rom[13'h1de9] = 1; assign rom[13'h1dea] = 1; assign rom[13'h1deb] = 1; assign rom[13'h1dec] = 1; assign rom[13'h1ded] = 1; assign rom[13'h1dee] = 0; assign rom[13'h1def] = 0; assign rom[13'h1df0] = 0; assign rom[13'h1df1] = 0; assign rom[13'h1df2] = 1; assign rom[13'h1df3] = 0; assign rom[13'h1df4] = 1; assign rom[13'h1df5] = 0; assign rom[13'h1df6] = 0; assign rom[13'h1df7] = 0; assign rom[13'h1df8] = 0; assign rom[13'h1df9] = 0; assign rom[13'h1dfa] = 0; assign rom[13'h1dfb] = 0; assign rom[13'h1dfc] = 0; assign rom[13'h1dfd] = 0; assign rom[13'h1dfe] = 0; assign rom[13'h1dff] = 0; assign rom[13'h1e00] = 0; assign rom[13'h1e01] = 0; assign rom[13'h1e02] = 0; assign rom[13'h1e03] = 0; assign rom[13'h1e04] = 0; assign rom[13'h1e05] = 0; assign rom[13'h1e06] = 0; assign rom[13'h1e07] = 0; assign rom[13'h1e08] = 0; assign rom[13'h1e09] = 0; assign rom[13'h1e0a] = 0; assign rom[13'h1e0b] = 0; assign rom[13'h1e0c] = 0; assign rom[13'h1e0d] = 0; assign rom[13'h1e0e] = 0; assign rom[13'h1e0f] = 0; assign rom[13'h1e10] = 0; assign rom[13'h1e11] = 1; assign rom[13'h1e12] = 1; assign rom[13'h1e13] = 0; assign rom[13'h1e14] = 0; assign rom[13'h1e15] = 1; assign rom[13'h1e16] = 1; assign rom[13'h1e17] = 0; assign rom[13'h1e18] = 0; assign rom[13'h1e19] = 0; assign rom[13'h1e1a] = 1; assign rom[13'h1e1b] = 1; assign rom[13'h1e1c] = 1; assign rom[13'h1e1d] = 1; assign rom[13'h1e1e] = 0; assign rom[13'h1e1f] = 0; assign rom[13'h1e20] = 0; assign rom[13'h1e21] = 0; assign rom[13'h1e22] = 0; assign rom[13'h1e23] = 1; assign rom[13'h1e24] = 1; assign rom[13'h1e25] = 0; assign rom[13'h1e26] = 0; assign rom[13'h1e27] = 0; assign rom[13'h1e28] = 0; assign rom[13'h1e29] = 0; assign rom[13'h1e2a] = 1; assign rom[13'h1e2b] = 1; assign rom[13'h1e2c] = 1; assign rom[13'h1e2d] = 1; assign rom[13'h1e2e] = 0; assign rom[13'h1e2f] = 0; assign rom[13'h1e30] = 0; assign rom[13'h1e31] = 1; assign rom[13'h1e32] = 1; assign rom[13'h1e33] = 0; assign rom[13'h1e34] = 0; assign rom[13'h1e35] = 1; assign rom[13'h1e36] = 1; assign rom[13'h1e37] = 0; assign rom[13'h1e38] = 0; assign rom[13'h1e39] = 0; assign rom[13'h1e3a] = 0; assign rom[13'h1e3b] = 0; assign rom[13'h1e3c] = 0; assign rom[13'h1e3d] = 0; assign rom[13'h1e3e] = 0; assign rom[13'h1e3f] = 0; assign rom[13'h1e40] = 0; assign rom[13'h1e41] = 0; assign rom[13'h1e42] = 0; assign rom[13'h1e43] = 0; assign rom[13'h1e44] = 0; assign rom[13'h1e45] = 0; assign rom[13'h1e46] = 0; assign rom[13'h1e47] = 0; assign rom[13'h1e48] = 0; assign rom[13'h1e49] = 0; assign rom[13'h1e4a] = 0; assign rom[13'h1e4b] = 0; assign rom[13'h1e4c] = 0; assign rom[13'h1e4d] = 0; assign rom[13'h1e4e] = 0; assign rom[13'h1e4f] = 0; assign rom[13'h1e50] = 0; assign rom[13'h1e51] = 1; assign rom[13'h1e52] = 1; assign rom[13'h1e53] = 0; assign rom[13'h1e54] = 0; assign rom[13'h1e55] = 1; assign rom[13'h1e56] = 1; assign rom[13'h1e57] = 0; assign rom[13'h1e58] = 0; assign rom[13'h1e59] = 1; assign rom[13'h1e5a] = 1; assign rom[13'h1e5b] = 0; assign rom[13'h1e5c] = 0; assign rom[13'h1e5d] = 1; assign rom[13'h1e5e] = 1; assign rom[13'h1e5f] = 0; assign rom[13'h1e60] = 0; assign rom[13'h1e61] = 1; assign rom[13'h1e62] = 1; assign rom[13'h1e63] = 0; assign rom[13'h1e64] = 0; assign rom[13'h1e65] = 1; assign rom[13'h1e66] = 1; assign rom[13'h1e67] = 0; assign rom[13'h1e68] = 0; assign rom[13'h1e69] = 0; assign rom[13'h1e6a] = 1; assign rom[13'h1e6b] = 1; assign rom[13'h1e6c] = 1; assign rom[13'h1e6d] = 1; assign rom[13'h1e6e] = 1; assign rom[13'h1e6f] = 0; assign rom[13'h1e70] = 0; assign rom[13'h1e71] = 0; assign rom[13'h1e72] = 0; assign rom[13'h1e73] = 0; assign rom[13'h1e74] = 0; assign rom[13'h1e75] = 1; assign rom[13'h1e76] = 1; assign rom[13'h1e77] = 0; assign rom[13'h1e78] = 0; assign rom[13'h1e79] = 1; assign rom[13'h1e7a] = 1; assign rom[13'h1e7b] = 1; assign rom[13'h1e7c] = 1; assign rom[13'h1e7d] = 1; assign rom[13'h1e7e] = 0; assign rom[13'h1e7f] = 0; assign rom[13'h1e80] = 0; assign rom[13'h1e81] = 0; assign rom[13'h1e82] = 0; assign rom[13'h1e83] = 0; assign rom[13'h1e84] = 0; assign rom[13'h1e85] = 0; assign rom[13'h1e86] = 0; assign rom[13'h1e87] = 0; assign rom[13'h1e88] = 0; assign rom[13'h1e89] = 0; assign rom[13'h1e8a] = 0; assign rom[13'h1e8b] = 0; assign rom[13'h1e8c] = 0; assign rom[13'h1e8d] = 0; assign rom[13'h1e8e] = 0; assign rom[13'h1e8f] = 0; assign rom[13'h1e90] = 0; assign rom[13'h1e91] = 1; assign rom[13'h1e92] = 1; assign rom[13'h1e93] = 1; assign rom[13'h1e94] = 1; assign rom[13'h1e95] = 1; assign rom[13'h1e96] = 1; assign rom[13'h1e97] = 0; assign rom[13'h1e98] = 0; assign rom[13'h1e99] = 0; assign rom[13'h1e9a] = 0; assign rom[13'h1e9b] = 0; assign rom[13'h1e9c] = 1; assign rom[13'h1e9d] = 1; assign rom[13'h1e9e] = 0; assign rom[13'h1e9f] = 0; assign rom[13'h1ea0] = 0; assign rom[13'h1ea1] = 0; assign rom[13'h1ea2] = 0; assign rom[13'h1ea3] = 1; assign rom[13'h1ea4] = 1; assign rom[13'h1ea5] = 0; assign rom[13'h1ea6] = 0; assign rom[13'h1ea7] = 0; assign rom[13'h1ea8] = 0; assign rom[13'h1ea9] = 0; assign rom[13'h1eaa] = 1; assign rom[13'h1eab] = 1; assign rom[13'h1eac] = 0; assign rom[13'h1ead] = 0; assign rom[13'h1eae] = 0; assign rom[13'h1eaf] = 0; assign rom[13'h1eb0] = 0; assign rom[13'h1eb1] = 1; assign rom[13'h1eb2] = 1; assign rom[13'h1eb3] = 1; assign rom[13'h1eb4] = 1; assign rom[13'h1eb5] = 1; assign rom[13'h1eb6] = 1; assign rom[13'h1eb7] = 0; assign rom[13'h1eb8] = 0; assign rom[13'h1eb9] = 0; assign rom[13'h1eba] = 0; assign rom[13'h1ebb] = 0; assign rom[13'h1ebc] = 0; assign rom[13'h1ebd] = 0; assign rom[13'h1ebe] = 0; assign rom[13'h1ebf] = 0; assign rom[13'h1ec0] = 0; assign rom[13'h1ec1] = 0; assign rom[13'h1ec2] = 0; assign rom[13'h1ec3] = 1; assign rom[13'h1ec4] = 1; assign rom[13'h1ec5] = 1; assign rom[13'h1ec6] = 0; assign rom[13'h1ec7] = 0; assign rom[13'h1ec8] = 0; assign rom[13'h1ec9] = 0; assign rom[13'h1eca] = 1; assign rom[13'h1ecb] = 1; assign rom[13'h1ecc] = 0; assign rom[13'h1ecd] = 0; assign rom[13'h1ece] = 0; assign rom[13'h1ecf] = 0; assign rom[13'h1ed0] = 0; assign rom[13'h1ed1] = 0; assign rom[13'h1ed2] = 1; assign rom[13'h1ed3] = 1; assign rom[13'h1ed4] = 0; assign rom[13'h1ed5] = 0; assign rom[13'h1ed6] = 0; assign rom[13'h1ed7] = 0; assign rom[13'h1ed8] = 0; assign rom[13'h1ed9] = 1; assign rom[13'h1eda] = 1; assign rom[13'h1edb] = 0; assign rom[13'h1edc] = 0; assign rom[13'h1edd] = 0; assign rom[13'h1ede] = 0; assign rom[13'h1edf] = 0; assign rom[13'h1ee0] = 0; assign rom[13'h1ee1] = 0; assign rom[13'h1ee2] = 1; assign rom[13'h1ee3] = 1; assign rom[13'h1ee4] = 0; assign rom[13'h1ee5] = 0; assign rom[13'h1ee6] = 0; assign rom[13'h1ee7] = 0; assign rom[13'h1ee8] = 0; assign rom[13'h1ee9] = 0; assign rom[13'h1eea] = 1; assign rom[13'h1eeb] = 1; assign rom[13'h1eec] = 0; assign rom[13'h1eed] = 0; assign rom[13'h1eee] = 0; assign rom[13'h1eef] = 0; assign rom[13'h1ef0] = 0; assign rom[13'h1ef1] = 0; assign rom[13'h1ef2] = 0; assign rom[13'h1ef3] = 1; assign rom[13'h1ef4] = 1; assign rom[13'h1ef5] = 1; assign rom[13'h1ef6] = 0; assign rom[13'h1ef7] = 0; assign rom[13'h1ef8] = 0; assign rom[13'h1ef9] = 0; assign rom[13'h1efa] = 0; assign rom[13'h1efb] = 0; assign rom[13'h1efc] = 0; assign rom[13'h1efd] = 0; assign rom[13'h1efe] = 0; assign rom[13'h1eff] = 0; assign rom[13'h1f00] = 0; assign rom[13'h1f01] = 0; assign rom[13'h1f02] = 0; assign rom[13'h1f03] = 1; assign rom[13'h1f04] = 1; assign rom[13'h1f05] = 0; assign rom[13'h1f06] = 0; assign rom[13'h1f07] = 0; assign rom[13'h1f08] = 0; assign rom[13'h1f09] = 0; assign rom[13'h1f0a] = 0; assign rom[13'h1f0b] = 1; assign rom[13'h1f0c] = 1; assign rom[13'h1f0d] = 0; assign rom[13'h1f0e] = 0; assign rom[13'h1f0f] = 0; assign rom[13'h1f10] = 0; assign rom[13'h1f11] = 0; assign rom[13'h1f12] = 0; assign rom[13'h1f13] = 1; assign rom[13'h1f14] = 1; assign rom[13'h1f15] = 0; assign rom[13'h1f16] = 0; assign rom[13'h1f17] = 0; assign rom[13'h1f18] = 0; assign rom[13'h1f19] = 0; assign rom[13'h1f1a] = 0; assign rom[13'h1f1b] = 1; assign rom[13'h1f1c] = 1; assign rom[13'h1f1d] = 0; assign rom[13'h1f1e] = 0; assign rom[13'h1f1f] = 0; assign rom[13'h1f20] = 0; assign rom[13'h1f21] = 0; assign rom[13'h1f22] = 0; assign rom[13'h1f23] = 1; assign rom[13'h1f24] = 1; assign rom[13'h1f25] = 0; assign rom[13'h1f26] = 0; assign rom[13'h1f27] = 0; assign rom[13'h1f28] = 0; assign rom[13'h1f29] = 0; assign rom[13'h1f2a] = 0; assign rom[13'h1f2b] = 1; assign rom[13'h1f2c] = 1; assign rom[13'h1f2d] = 0; assign rom[13'h1f2e] = 0; assign rom[13'h1f2f] = 0; assign rom[13'h1f30] = 0; assign rom[13'h1f31] = 0; assign rom[13'h1f32] = 0; assign rom[13'h1f33] = 1; assign rom[13'h1f34] = 1; assign rom[13'h1f35] = 0; assign rom[13'h1f36] = 0; assign rom[13'h1f37] = 0; assign rom[13'h1f38] = 0; assign rom[13'h1f39] = 0; assign rom[13'h1f3a] = 0; assign rom[13'h1f3b] = 0; assign rom[13'h1f3c] = 0; assign rom[13'h1f3d] = 0; assign rom[13'h1f3e] = 0; assign rom[13'h1f3f] = 0; assign rom[13'h1f40] = 0; assign rom[13'h1f41] = 0; assign rom[13'h1f42] = 1; assign rom[13'h1f43] = 1; assign rom[13'h1f44] = 1; assign rom[13'h1f45] = 0; assign rom[13'h1f46] = 0; assign rom[13'h1f47] = 0; assign rom[13'h1f48] = 0; assign rom[13'h1f49] = 0; assign rom[13'h1f4a] = 0; assign rom[13'h1f4b] = 0; assign rom[13'h1f4c] = 1; assign rom[13'h1f4d] = 1; assign rom[13'h1f4e] = 0; assign rom[13'h1f4f] = 0; assign rom[13'h1f50] = 0; assign rom[13'h1f51] = 0; assign rom[13'h1f52] = 0; assign rom[13'h1f53] = 0; assign rom[13'h1f54] = 1; assign rom[13'h1f55] = 1; assign rom[13'h1f56] = 0; assign rom[13'h1f57] = 0; assign rom[13'h1f58] = 0; assign rom[13'h1f59] = 0; assign rom[13'h1f5a] = 0; assign rom[13'h1f5b] = 0; assign rom[13'h1f5c] = 0; assign rom[13'h1f5d] = 1; assign rom[13'h1f5e] = 1; assign rom[13'h1f5f] = 0; assign rom[13'h1f60] = 0; assign rom[13'h1f61] = 0; assign rom[13'h1f62] = 0; assign rom[13'h1f63] = 0; assign rom[13'h1f64] = 1; assign rom[13'h1f65] = 1; assign rom[13'h1f66] = 0; assign rom[13'h1f67] = 0; assign rom[13'h1f68] = 0; assign rom[13'h1f69] = 0; assign rom[13'h1f6a] = 0; assign rom[13'h1f6b] = 0; assign rom[13'h1f6c] = 1; assign rom[13'h1f6d] = 1; assign rom[13'h1f6e] = 0; assign rom[13'h1f6f] = 0; assign rom[13'h1f70] = 0; assign rom[13'h1f71] = 0; assign rom[13'h1f72] = 1; assign rom[13'h1f73] = 1; assign rom[13'h1f74] = 1; assign rom[13'h1f75] = 0; assign rom[13'h1f76] = 0; assign rom[13'h1f77] = 0; assign rom[13'h1f78] = 0; assign rom[13'h1f79] = 0; assign rom[13'h1f7a] = 0; assign rom[13'h1f7b] = 0; assign rom[13'h1f7c] = 0; assign rom[13'h1f7d] = 0; assign rom[13'h1f7e] = 0; assign rom[13'h1f7f] = 0; assign rom[13'h1f80] = 0; assign rom[13'h1f81] = 0; assign rom[13'h1f82] = 0; assign rom[13'h1f83] = 0; assign rom[13'h1f84] = 0; assign rom[13'h1f85] = 0; assign rom[13'h1f86] = 0; assign rom[13'h1f87] = 0; assign rom[13'h1f88] = 0; assign rom[13'h1f89] = 0; assign rom[13'h1f8a] = 1; assign rom[13'h1f8b] = 1; assign rom[13'h1f8c] = 0; assign rom[13'h1f8d] = 0; assign rom[13'h1f8e] = 1; assign rom[13'h1f8f] = 0; assign rom[13'h1f90] = 0; assign rom[13'h1f91] = 1; assign rom[13'h1f92] = 0; assign rom[13'h1f93] = 0; assign rom[13'h1f94] = 1; assign rom[13'h1f95] = 1; assign rom[13'h1f96] = 0; assign rom[13'h1f97] = 0; assign rom[13'h1f98] = 0; assign rom[13'h1f99] = 0; assign rom[13'h1f9a] = 0; assign rom[13'h1f9b] = 0; assign rom[13'h1f9c] = 0; assign rom[13'h1f9d] = 0; assign rom[13'h1f9e] = 0; assign rom[13'h1f9f] = 0; assign rom[13'h1fa0] = 0; assign rom[13'h1fa1] = 0; assign rom[13'h1fa2] = 0; assign rom[13'h1fa3] = 0; assign rom[13'h1fa4] = 0; assign rom[13'h1fa5] = 0; assign rom[13'h1fa6] = 0; assign rom[13'h1fa7] = 0; assign rom[13'h1fa8] = 0; assign rom[13'h1fa9] = 0; assign rom[13'h1faa] = 0; assign rom[13'h1fab] = 0; assign rom[13'h1fac] = 0; assign rom[13'h1fad] = 0; assign rom[13'h1fae] = 0; assign rom[13'h1faf] = 0; assign rom[13'h1fb0] = 0; assign rom[13'h1fb1] = 0; assign rom[13'h1fb2] = 0; assign rom[13'h1fb3] = 0; assign rom[13'h1fb4] = 0; assign rom[13'h1fb5] = 0; assign rom[13'h1fb6] = 0; assign rom[13'h1fb7] = 0; assign rom[13'h1fb8] = 0; assign rom[13'h1fb9] = 0; assign rom[13'h1fba] = 0; assign rom[13'h1fbb] = 0; assign rom[13'h1fbc] = 0; assign rom[13'h1fbd] = 0; assign rom[13'h1fbe] = 0; assign rom[13'h1fbf] = 0; assign rom[13'h1fc0] = 1; assign rom[13'h1fc1] = 1; assign rom[13'h1fc2] = 1; assign rom[13'h1fc3] = 1; assign rom[13'h1fc4] = 1; assign rom[13'h1fc5] = 1; assign rom[13'h1fc6] = 1; assign rom[13'h1fc7] = 1; assign rom[13'h1fc8] = 1; assign rom[13'h1fc9] = 1; assign rom[13'h1fca] = 1; assign rom[13'h1fcb] = 1; assign rom[13'h1fcc] = 1; assign rom[13'h1fcd] = 1; assign rom[13'h1fce] = 1; assign rom[13'h1fcf] = 1; assign rom[13'h1fd0] = 1; assign rom[13'h1fd1] = 1; assign rom[13'h1fd2] = 1; assign rom[13'h1fd3] = 1; assign rom[13'h1fd4] = 1; assign rom[13'h1fd5] = 1; assign rom[13'h1fd6] = 1; assign rom[13'h1fd7] = 1; assign rom[13'h1fd8] = 1; assign rom[13'h1fd9] = 1; assign rom[13'h1fda] = 1; assign rom[13'h1fdb] = 1; assign rom[13'h1fdc] = 1; assign rom[13'h1fdd] = 1; assign rom[13'h1fde] = 1; assign rom[13'h1fdf] = 1; assign rom[13'h1fe0] = 1; assign rom[13'h1fe1] = 1; assign rom[13'h1fe2] = 1; assign rom[13'h1fe3] = 1; assign rom[13'h1fe4] = 1; assign rom[13'h1fe5] = 1; assign rom[13'h1fe6] = 1; assign rom[13'h1fe7] = 1; assign rom[13'h1fe8] = 1; assign rom[13'h1fe9] = 1; assign rom[13'h1fea] = 1; assign rom[13'h1feb] = 1; assign rom[13'h1fec] = 1; assign rom[13'h1fed] = 1; assign rom[13'h1fee] = 1; assign rom[13'h1fef] = 1; assign rom[13'h1ff0] = 1; assign rom[13'h1ff1] = 1; assign rom[13'h1ff2] = 1; assign rom[13'h1ff3] = 1; assign rom[13'h1ff4] = 1; assign rom[13'h1ff5] = 1; assign rom[13'h1ff6] = 1; assign rom[13'h1ff7] = 1; assign rom[13'h1ff8] = 1; assign rom[13'h1ff9] = 1; assign rom[13'h1ffa] = 1; assign rom[13'h1ffb] = 1; assign rom[13'h1ffc] = 1; assign rom[13'h1ffd] = 1; assign rom[13'h1ffe] = 1; assign rom[13'h1fff] = 1; endmodule
source_codes/v/fpu.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module fpu (a,b,fc,wf,fd,ein1,clk,clrn,ed,wd,wn,ww,st_ds,e1n,e1w, // fpu e2n,e2w,e3n,e3w, e1c,e2c,e3c,count_div,count_sqrt,e,ein2); input clk, clrn; // clock and reset input [31:0] a, b; // 32-bit fp numbers input [4:0] fd; // fp dest reg number input [2:0] fc; // fp control input wf; // write fp regfile input ein1; // no_cache_stall input ein2; // for canceling E1 inst output [31:0] ed,wd; // wd: fp result output [4:0] count_div,count_sqrt; // for testing output [4:0] e1n,e2n,e3n,wn; // reg numbers output [1:0] e1c,e2c,e3c; // for testing output e1w,e2w,e3w,ww; // write fp regfile output st_ds; // stall caused by fdiv or fsqrt output e; // ein1 & ~st_ds reg [31:0] wd; reg [31:0] efa,efb; reg [4:0] e1n,e2n,e3n,wn; reg [1:0] e1c,e2c,e3c; reg e1w0,e2w,e3w,ww,sub; wire [31:0] s_add,s_mul,s_div,s_sqrt; wire [25:0] reg_x_div,reg_x_sqrt; wire busy_div,stall_div,busy_sqrt,stall_sqrt; wire fdiv = fc[2] & ~fc[1]; wire fsqrt = fc[2] & fc[1]; assign e1w = e1w0 & ein2; assign e = ein1 & ~st_ds; pipelined_fadder f_add (efa,efb,sub,2'b0,s_add,clk,clrn,e); pipelined_fmul f_mul (efa,efb,2'b0,s_mul,clk,clrn,e); fdiv_newton f_div (a,b,2'b0,fdiv, e,clk,clrn,s_div, busy_div, stall_div, count_div, reg_x_div ); fsqrt_newton f_sqrt (a,2'b0,fsqrt,e,clk,clrn,s_sqrt,busy_sqrt, stall_sqrt,count_sqrt,reg_x_sqrt); assign st_ds = stall_div | stall_sqrt; mux4x32 fsel (s_add,s_mul,s_div,s_sqrt,e3c,ed); always @ (negedge clrn or posedge clk) if (!clrn) begin // pipeline registers sub <= 0; efa <= 0; efb <= 0; e1c <= 0; e1w0 <= 0; e1n <= 0; e2c <= 0; e2w <= 0; e2n <= 0; e3c <= 0; e3w <= 0; e3n <= 0; wd <= 0; ww <= 0; wn <= 0; end else if (e) begin sub <= fc[0]; efa <= a; efb <= b; e1c <= fc[2:1]; e1w0 <= wf; e1n <= fd; e2c <= e1c; e2w <= e1w; e2n <= e1n; e3c <= e2c; e3w <= e2w; e3n <= e2n; wd <= ed; ww <= e3w; wn <= e3n; end endmodule
source_codes/v/fpu_1_iu.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ // pipelined cpu with fpu, instruction memory, and data memory module fpu_1_iu (clk,memclk,clrn,pc,inst,ealu,malu,walu,wn,wd,ww,stl_lw, stl_fp,stl_lwc1,stl_swc1,stl,cnt_div,cnt_sqrt, e1n,e2n,e3n,e3d,e); input clk, memclk, clrn; // clocks and reset output [31:0] pc, inst, ealu, malu, walu; output [31:0] e3d, wd; output [4:0] e1n, e2n, e3n, wn; output ww, stl_lw, stl_fp, stl_lwc1, stl_swc1, stl; output e; // for multithreading CPU, not used here output [4:0] cnt_div, cnt_sqrt; // for testing wire [31:0] qfa,qfb,fa,fb,dfa,dfb,mmo,wmo; // for iu wire [4:0] fs,ft,fd,wrn; wire [2:0] fc; wire [1:0] e1c,e2c,e3c; // for fpu wire fwdla,fwdlb,fwdfa,fwdfb,wf,fasmds,e1w,e2w,e3w,wwfpr; iu i_u (e1n,e2n,e3n, e1w,e2w,e3w,stl,1'b0, // st = 0 dfb,e3d, clk,memclk,clrn, fs,ft,wmo,wrn,wwfpr,mmo,fwdla,fwdlb,fwdfa,fwdfb,fd,fc,wf,fasmds, pc,inst,ealu,malu,walu, // for testing stl_lw,stl_fp,stl_lwc1,stl_swc1); // for testing regfile2w fpr (fs,ft,wd,wn,ww,wmo,wrn,wwfpr,~clk,clrn,qfa,qfb); mux2x32 fwd_f_load_a (qfa,mmo,fwdla,fa); // forward lwc1 to fp a mux2x32 fwd_f_load_b (qfb,mmo,fwdlb,fb); // forward lwc1 to fp b mux2x32 fwd_f_res_a (fa,e3d,fwdfa,dfa); // forward fp res to fp a mux2x32 fwd_f_res_b (fb,e3d,fwdfb,dfb); // forward fp res to fp b fpu fp_unit (dfa,dfb,fc,wf,fd,1'b1,clk,clrn,e3d,wd,wn,ww, stl,e1n,e1w,e2n,e2w,e3n,e3w, e1c,e2c,e3c,cnt_div,cnt_sqrt,e,1'b1); endmodule
source_codes/v/fpu_1_iu_tb.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ `timescale 1ns/1ns module fpu_1_iu_tb; reg clk,memclk,clrn; wire [31:0] pc,inst,ealu,malu,walu; wire [31:0] e3d,wd; wire [4:0] e1n,e2n,e3n,wn; wire ww,stl_lw,stl_fp,stl_lwc1,stl_swc1,stl; wire e; wire [4:0] cnt_div,cnt_sqrt; fpu_1_iu cpu (clk,memclk,clrn,pc,inst,ealu,malu,walu,wn, wd,ww,stl_lw,stl_fp,stl_lwc1,stl_swc1, stl,cnt_div,cnt_sqrt,e1n,e2n,e3n,e3d,e); initial begin clrn = 0; memclk = 0; clk = 1; #1 clrn = 1; end always #1 memclk = !memclk; always #2 clk = !clk; endmodule /* 24 - 52.001 ns 48 - 76.001 ns 128 - 412.000 ns */
source_codes/v/fpu_2_iu.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ // two-thread cpu with fpu, instruction memory, and data memory module fpu_2_iu (clrn,memclk,clk,pc0,inst0,ealu0,malu0,walu0,ww0,stl_lw0, stl_lwc10,stl_swc10,stl_fp0,stall0,st0,pc1,inst1,ealu1, malu1,walu1,ww1,stl_lw1,stl_lwc11,stl_swc11,stl_fp1,stall1, st1,wn,wd,cnt_div,cnt_sqrt,e1n,e2n,e3n,e3d,e); input clk, memclk, clrn; // clocks and reset output [31:0] pc0, inst0, ealu0, malu0, walu0; output [31:0] pc1, inst1, ealu1, malu1, walu1; output [31:0] e3d, wd; output [4:0] e1n, e2n, e3n, wn; output ww0, stl_lw0, stl_lwc10, stl_swc10, stl_fp0, stall0, st0; output ww1, stl_lw1, stl_lwc11, stl_swc11, stl_fp1, stall1, st1; output e; // for multithreading CPU, not used here output [4:0] cnt_div,cnt_sqrt; wire [31:0] qfa0,qfb0,fa0,fb0,dfa0,dfb0,mmo0,wmo0; wire [31:0] qfa1,qfb1,fa1,fb1,dfa1,dfb1,mmo1,wmo1; wire [4:0] fs0,ft0,fd0,wrn0; wire [4:0] fs1,ft1,fd1,wrn1; wire [2:0] fc0; wire [2:0] fc1; wire fwdla0,fwdlb0,fwdfa0,fwdfb0,wf0,fasmds0; wire fwdla1,fwdlb1,fwdfa1,fwdfb1,wf1,fasmds1; wire [31:0] dfa,dfb; // fp inputs a and b wire [4:0] fd; // fp dest reg # wire [2:0] fc; // fp operation code wire [1:0] e1c,e2c,e3c; wire wf; // fp regfile we wire stall0,e1w0,e2w0,e3w0,ww0; wire stall1,e1w1,e2w1,e3w1,ww1; wire dt; reg cnt,e1t,e2t,e3t,wt; // thread 0 iu th0 (e1n,e2n,e3n, e1w0,e2w0,e3w0, stall0,st0, dfb0,e3d, clk,memclk,clrn, fs0,ft0,wmo0,wrn0,wwfpr0,mmo0,fwdla0,fwdlb0,fwdfa0,fwdfb0, fd0,fc0,wf0,fasmds0,pc0,inst0,ealu0,malu0,walu0, stl_lw0,stl_fp0,stl_lwc10,stl_swc10); regfile2w fpr0 (fs0,ft0,wd,wn,ww0,wmo0,wrn0,wwfpr0, ~clk,clrn,qfa0,qfb0); mux2x32 fwd_f_load_a0 (qfa0,mmo0,fwdla0,fa0); // forward lwc1 to fp a mux2x32 fwd_f_load_b0 (qfb0,mmo0,fwdlb0,fb0); // forward lwc1 to fp b mux2x32 fwd_f_res_a0 (fa0,e3d,fwdfa0,dfa0); // forward fp res to fp a mux2x32 fwd_f_res_b0 (fb0,e3d,fwdfb0,dfb0); // forward fp res to fp b // thread 1 iu th1 (e1n,e2n,e3n, e1w1,e2w1,e3w1, stall1,st1, dfb1,e3d, clk,memclk,clrn, fs1,ft1,wmo1,wrn1,wwfpr1,mmo1,fwdla1,fwdlb1,fwdfa1,fwdfb1, fd1,fc1,wf1,fasmds1,pc1,inst1,ealu1,malu1,walu1, stl_lw1,stl_fp1,stl_lwc11,stl_swc11); regfile2w fpr1 (fs1,ft1,wd,wn,ww1,wmo1,wrn1,wwfpr1, ~clk,clrn,qfa1,qfb1); mux2x32 fwd_f_load_a1 (qfa1,mmo1,fwdla1,fa1); // forward lwc1 to fp a mux2x32 fwd_f_load_b1 (qfb1,mmo1,fwdlb1,fb1); // forward lwc1 to fp b mux2x32 fwd_f_res_a1 (fa1,e3d,fwdfa1,dfa1); // forward fp res to fp a mux2x32 fwd_f_res_b1 (fb1,e3d,fwdfb1,dfb1); // forward fp res to fp b // fpu wire [31:0] s_sqrt; // fp output wire [25:0] sqrt_x; // x_i fpu fp_unit (dfa,dfb,fc,wf,fd,1'b1,clk,clrn, e3d,wd,wn,ww,stall,e1n,e1w,e2n, e2w,e3n,e3w,e1c,e2c,e3c,cnt_div, cnt_sqrt,e,1'b1); // no dtlb, hit = 1 // mux: fpu selects thread 0 or thread 1 assign dfa = dt? dfa1 : dfa0; assign dfb = dt? dfb1 : dfb0; assign fd = dt? fd1 : fd0; assign wf = dt? wf1 : wf0; assign fc = dt? fc1 : fc0; // demux: for thread 0; for thread 1 assign stall0 = stall & ~dt; assign stall1 = stall & dt; // ID stage assign e1w0 = e1w & ~e1t; assign e1w1 = e1w & e1t; // E1 stage assign e2w0 = e2w & ~e2t; assign e2w1 = e2w & e2t; // E2 stage assign e3w0 = e3w & ~e3t; assign e3w1 = e3w & e3t; // E3 stage assign ww0 = ww & ~wt; assign ww1 = ww & wt; // WB stage // thread selection assign dt = ~fasmds0 & fasmds1 | cnt & fasmds1; // selected thread assign st0 = cnt & fasmds0 & fasmds1; // stall thread 0 assign st1 = ~cnt & fasmds0 & fasmds1; // stall thread 1 // count for thread selection always @(negedge clrn or posedge clk) begin if (!clrn) begin cnt <= 0; end else if (e) begin cnt <= ~cnt; end end // pipelined thread info always @(negedge clrn or posedge clk) begin if (!clrn) begin e1t <= 0; e2t <= 0; e3t <= 0; wt <= 0; end else if (e) begin e1t <= dt; e2t <= e1t; e3t <= e2t; wt <= e3t; end end endmodule
source_codes/v/fpu_2_iu_tb.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ `timescale 1ns/1ns module fpu_2_iu_tb; reg clk,memclk,clrn; wire [31:0] pc0,inst0,ealu0,malu0,walu0; wire [31:0] pc1,inst1,ealu1,malu1,walu1; wire ww0,stl_lw0,stl_lwc10,stl_swc10,stl_fp0,stall0,st0; wire ww1,stl_lw1,stl_lwc11,stl_swc11,stl_fp1,stall1,st1; wire e; wire [31:0] e3d,wd; wire [4:0] e1n,e2n,e3n,wn; wire [4:0] cnt_div,cnt_sqrt; fpu_2_iu cpu (clrn,memclk,clk, pc0,inst0,ealu0,malu0,walu0,ww0, stl_lw0,stl_lwc10,stl_swc10,stl_fp0,stall0,st0, pc1,inst1,ealu1,malu1,walu1,ww1, stl_lw1,stl_lwc11,stl_swc11,stl_fp1,stall1,st1, wn,wd,cnt_div,cnt_sqrt,e1n,e2n,e3n,e3d,e); initial begin clrn = 0; memclk = 0; clk = 1; #1 clrn = 1; end always #1 memclk = !memclk; always #2 clk = !clk; endmodule /* 24 - 53 ns 144 - 646 ns */
source_codes/v/fsqrt_newton.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module fsqrt_newton (d,rm,fsqrt,ena,clk,clrn, s,busy,stall,count,reg_x); input clk, clrn; // clock and reset input [31:0] d; // fp s = root(d) input [1:0] rm; // round mode input fsqrt; // ID stage: fsqrt = i_fsqrt input ena; // enable output [31:0] s; // fp output output [25:0] reg_x; // x_i output [4:0] count; // for iteration control output busy; // for generating stall output stall; // for pipeline stall parameter ZERO = 32'h00000000; parameter INF = 32'h7f800000; parameter NaN = 32'h7fc00000; wire d_expo_is_00 = ~|d[30:23]; // d_expo = 00 wire d_expo_is_ff = &d[30:23]; // d_expo = ff wire d_frac_is_00 = ~|d[22:0]; // d_frac = 00 wire sign = d[31]; // e_q = (e_d >> 1) + 63 + (e_d % 2) wire [7:0] exp_8 = {1'b0,d[30:24]} + 8'd63 + d[23]; // normalized // = 0 + 63 + 0 = 63 // denormalized // d_f24 = denormalized? .f_d,0 : .1,f_d // shifted 1 bit wire [23:0] d_f24 = d_expo_is_00? {d[22:0],1'b0} : {1'b1,d[22:0]}; // tmp = e_d is odd? shift one more bit : 1 bit, no change wire [23:0] d_temp24 = d[23]? {1'b0,d_f24[23:1]} : d_f24; wire [23:0] d_frac24; // .1xx...x or .01x...x for denormalized number wire [4:0] shamt_d; // shift amount, even number shift_even_bits shift_d (d_temp24,d_frac24,shamt_d); // denormalized: e_q = 63 - shamt_d / 2 // normalized: e_q = exp_8 - 0 wire [7:0] exp0 = exp_8 - {4'h0,shamt_d[4:1]}; reg e1_sign,e1_e00,e1_eff,e1_f00; reg e2_sign,e2_e00,e2_eff,e2_f00; reg e3_sign,e3_e00,e3_eff,e3_f00; reg [1:0] e1_rm,e2_rm,e3_rm; reg [7:0] e1_exp,e2_exp,e3_exp; always @ (negedge clrn or posedge clk) if (!clrn) begin // 3 pipeline registers: reg_e1, reg_e2, and reg_e3 // reg_e1 reg_e2 reg_e3 e1_sign <= 0; e2_sign <= 0; e3_sign <= 0; e1_rm <= 0; e2_rm <= 0; e3_rm <= 0; e1_exp <= 0; e2_exp <= 0; e3_exp <= 0; e1_e00 <= 0; e2_e00 <= 0; e3_e00 <= 0; e1_eff <= 0; e2_eff <= 0; e3_eff <= 0; e1_f00 <= 0; e2_f00 <= 0; e3_f00 <= 0; end else if (ena) begin e1_sign <= sign; e2_sign <= e1_sign; e3_sign <= e2_sign; e1_rm <= rm; e2_rm <= e1_rm; e3_rm <= e2_rm; e1_exp <= exp0; e2_exp <= e1_exp; e3_exp <= e2_exp; e1_e00 <= d_expo_is_00; e2_e00 <= e1_e00; e3_e00 <= e2_e00; e1_eff <= d_expo_is_ff; e2_eff <= e1_eff; e3_eff <= e2_eff; e1_f00 <= d_frac_is_00; e2_f00 <= e1_f00; e3_f00 <= e2_f00; end wire [31:0] frac0; // root = 1.xxxx...x root_newton24 frac_newton (d_frac24,fsqrt,ena,clk,clrn, frac0,busy,count,reg_x,stall); wire [26:0] frac = {frac0[31:6],|frac0[5:0]}; // sticky wire frac_plus_1 = ~e3_rm[1] & ~e3_rm[0] & frac[3] & frac[2] & ~frac[1] & ~frac[0] | ~e3_rm[1] & ~e3_rm[0] & frac[2] & (frac[1] | frac[0]) | ~e3_rm[1] & e3_rm[0] & (frac[2] | frac[1] | frac[0]) & e3_sign | e3_rm[1] & ~e3_rm[0] & (frac[2] | frac[1] | frac[0]) & ~e3_sign; wire [24:0] frac_rnd = {1'b0,frac[26:3]} + frac_plus_1; wire [7:0] expo_new = frac_rnd[24]? e3_exp + 8'h1 : e3_exp; wire [22:0] frac_new = frac_rnd[24]? frac_rnd[23:1]: frac_rnd[22:0]; assign s = final_result(e3_sign,e3_e00,e3_eff,e3_f00, {e3_sign,expo_new,frac_new}); function [31:0] final_result; input d_sign,d_e00,d_eff,d_f00; input [31:0] calc; casex ({d_sign,d_e00,d_eff,d_f00}) 4'b1xxx : final_result = NaN; // - 4'b000x : final_result = calc; // nor 4'b0100 : final_result = calc; // den 4'b0010 : final_result = NaN; // nan 4'b0011 : final_result = INF; // inf default : final_result = ZERO; // 0 endcase endfunction endmodule
source_codes/v/fsqrt_newton_tb.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ `timescale 1ns/1ns module fsqrt_newton_tb; reg [31:0] d; reg [1:0] rm; reg fsqrt; reg ena; reg clk,clrn; wire [31:0] s; wire busy; wire stall; wire [4:0] count; wire [25:0] reg_x; fsqrt_newton fsn (d,rm,fsqrt,ena,clk,clrn,s,busy,stall,count,reg_x); initial begin clk = 1; clrn = 0; rm = 0; ena = 1; fsqrt = 0; d = 32'h41100000; #2 clrn = 1; #13 fsqrt = 1; #214 fsqrt = 0; #71 d = 32'h00003200; #15 fsqrt = 1; #214 fsqrt = 0; end always #5 clk = !clk; endmodule
source_codes/v/gates7_dataflow.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module gates7_dataflow (a,b,f_and,f_or,f_not,f_nand,f_nor,f_xor,f_xnor); input a, b; // inputs output f_and, f_or, f_not, f_nand, f_nor, f_xor, f_xnor; // outputs assign f_and = a & b; // and assign f_or = a | b; // or assign f_not = ~ a; // not assign f_nand = ~(a & b); // nand = not(a and b) assign f_nor = ~(a | b); // nor = not(a or b) assign f_xor = a ^ b; // xor assign f_xnor = ~(a ^ b); // xnor = not(a xor b) endmodule
source_codes/v/gates7_dataflow_tb.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ `timescale 1ns/1ns module gates7_dataflow_tb; reg a,b; wire f_and,f_or,f_not,f_nand,f_nor,f_xor,f_xnor; gates7_dataflow g7 (a,b,f_and,f_or,f_not,f_nand,f_nor,f_xor,f_xnor); initial begin $display("time\ta\tb\tand\tor\tnot\tnand\tnor\txor\txnor"); a = 0; b = 0; #5 $finish; end initial begin $monitor ("%2d:\t%b\t%b\t%b\t%b\t%b\t%b\t%b\t%b\t%b", $time,a,b,f_and,f_or,f_not,f_nand,f_nor,f_xor,f_xnor); end always #1 a = !a; always #2 b = !b; endmodule
source_codes/v/gates7_structural.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module gates7_structural (a,b,f_and,f_or,f_not,f_nand,f_nor,f_xor,f_xnor); input a, b; // inputs output f_and, f_or, f_not, f_nand, f_nor, f_xor, f_xnor; // outputs and i1 (f_and, a, b); // and (out, in1, in2) or i2 (f_or, a, b); // or (out, in2, in2) not i3 (f_not, a); // not (out, in) nand i4 (f_nand, a, b); // nand (out, in1, in2) nor i5 (f_nor, a, b); // nor (out, in1, in2) xor i6 (f_xor, a, b); // xor (out, in1, in2) xnor i7 (f_xnor, a, b); // xnor (out, in1, in2) endmodule
source_codes/v/gates7_structural_tb.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ `timescale 1ns/1ns module gates7_structural_tb; reg a,b; wire f_and,f_or,f_not,f_nand,f_nor,f_xor,f_xnor; gates7_structural g (a,b,f_and,f_or,f_not,f_nand,f_nor,f_xor,f_xnor); initial begin a = 0; b = 0; #1 $display (" a=%b",a," b=%b",b," f_and=%b",f_and, " f_or=%b",f_or," f_not=%b",f_not, " f_nand=%b",f_nand," f_nor=%b",f_nor, " f_xor=%b",f_xor," f_xnor=%b",f_xnor); #1 a = 1; b = 0; #1 $display (" a=%b",a," b=%b",b," f_and=%b",f_and, " f_or=%b",f_or," f_not=%b",f_not, " f_nand=%b",f_nand," f_nor=%b",f_nor, " f_xor=%b",f_xor," f_xnor=%b",f_xnor); #1 a = 0; b = 1; #1 $display (" a=%b",a," b=%b",b," f_and=%b",f_and, " f_or=%b",f_or," f_not=%b",f_not, " f_nand=%b",f_nand," f_nor=%b",f_nor, " f_xor=%b",f_xor," f_xnor=%b",f_xnor); #1 a = 1; b = 1; #1 $display (" a=%b",a," b=%b",b," f_and=%b",f_and, " f_or=%b",f_or," f_not=%b",f_not, " f_nand=%b",f_nand," f_nor=%b",f_nor, " f_xor=%b",f_xor," f_xnor=%b",f_xnor); #1 a = 0; b = 0; #1 $finish; end initial begin $dumpfile("gates7_structural.vcd"); $dumpvars; end endmodule
source_codes/v/goldschmidt.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module goldschmidt (a,b,start,clk,clrn,q,busy,ready,count,yn); input [31:0] a; // dividend: .1xxx...x input [31:0] b; // divisor: .1xxx...x input start; // start input clk, clrn; // clock and reset output [31:0] q; // quotient: x.xxx...x output reg busy; // busy output reg ready; // ready output [2:0] count; // counter output [31:0] yn; // .11111...1 reg [63:0] reg_a; // x.xxxx...x reg [63:0] reg_b; // 0.xxxx...x reg [2:0] count; wire [63:0] two_minus_yi = ~reg_b + 1'b1; // 1.xxxx...x (2 - yi) wire [127:0] xi = reg_a * two_minus_yi; // 0x.xxx...x wire [127:0] yi = reg_b * two_minus_yi; // 0x.xxx...x assign q = reg_a[63:32] + |reg_a[31:29]; // rounding up assign yn = reg_b[62:31]; always @ (posedge clk or negedge clrn) begin if (!clrn) begin busy <= 0; ready <= 0; end else begin if (start) begin reg_a <= {1'b0,a,31'b0}; // 0.1x...x0...0 reg_b <= {1'b0,b,31'b0}; // 0.1x...x0...0 busy <= 1; ready <= 0; count <= 0; end else begin reg_a <= xi[126:63]; // x.xxx...x reg_b <= yi[126:63]; // 0.xxx...x count <= count + 3'b1; // count++ if (count == 3'h4) begin // finish busy <= 0; ready <= 1; // q is ready end end end end endmodule
source_codes/v/goldschmidt_tb.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ `timescale 1ns/1ns module goldschmidt_tb; reg [31:0] a; reg [31:0] b; reg start; reg clk,clrn; wire [31:0] q; wire busy; wire ready; wire [2:0] count; wire [31:0] yn; goldschmidt div (a,b,start,clk,clrn,q,busy,ready,count,yn); initial begin clrn = 0; start = 0; clk = 1; a = 32'hc0000000; b = 32'h80000000; #25 clrn = 1; start = 1; #50 start = 0; end always #25 clk = !clk; endmodule
source_codes/v/gp.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module gp (g,p,c_in,g_out,p_out,c_out); // carry generator, carry propagator input [1:0] g, p; // lower level 2-set of g, p input c_in; // lower level carry_in output g_out,p_out,c_out; // higher level g, p, carry_out assign g_out = g[1] | p[1] & g[0]; // higher level carry generator assign p_out = p[1] & p[0]; // higher level carry propagator assign c_out = g[0] | p[0] & c_in; // higher level carry_out endmodule
source_codes/v/high_z_buf.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module high_z_buf (in1,in2,in3,out1); // same as high_z_oc.v input in1, in2, in3; // three input signals output out1; // one output signal // bufif1 (out, in, ctl); bufif1 i1 (out1, 0, in1); // tri-state buffer: bufif1 i2 (out1, 0, in2); // ctl==1: out=in bufif1 i3 (out1, 0, in3); // ctl==0: out=high_z endmodule
source_codes/v/high_z_buf_tb.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ `timescale 1ns/1ns module high_z_buf_tb; reg in1, in2, in3; wire out1; high_z_buf hz (in1,in2,in3,out1); initial begin #0 in1 = 0; in2 = 0; in3 = 0; #1 in1 = 1; in2 = 0; in3 = 0; #1 in1 = 0; in2 = 1; in3 = 0; #1 in1 = 1; in2 = 1; in3 = 0; #1 in1 = 0; in2 = 0; in3 = 1; #1 in1 = 1; in2 = 0; in3 = 1; #1 in1 = 0; in2 = 1; in3 = 1; #1 in1 = 1; in2 = 1; in3 = 1; #1 in1 = 0; in2 = 0; in3 = 0; #1 $finish; end endmodule
source_codes/v/high_z_nor.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module high_z_nor (in1,in2,in3,out1); // same as high_z_oc.v input in1, in2, in3; // three input signals output out1; // one output signal assign out1 = (in1 | in2 | in3) ? 0 : 1'bz; // z: high-impedance endmodule
source_codes/v/high_z_nor_tb.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ `timescale 1ns/1ns module high_z_nor_tb; reg in1, in2, in3; wire out1; high_z_nor hz (in1,in2,in3,out1); initial begin #0 in1 = 0; in2 = 0; in3 = 0; #1 in1 = 1; in2 = 0; in3 = 0; #1 in1 = 0; in2 = 1; in3 = 0; #1 in1 = 1; in2 = 1; in3 = 0; #1 in1 = 0; in2 = 0; in3 = 1; #1 in1 = 1; in2 = 0; in3 = 1; #1 in1 = 0; in2 = 1; in3 = 1; #1 in1 = 1; in2 = 1; in3 = 1; #1 in1 = 0; in2 = 0; in3 = 0; #1 $finish; end endmodule
source_codes/v/high_z_oc.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module high_z_oc (in1,in2,in3,out1); // test open drain buffer input in1, in2, in3; // three input signals output out1; // one output signal wire not_out1, not_out2, not_out3; not not1 (not_out1, in1); // regular not gate not not2 (not_out2, in2); not not3 (not_out3, in3); opndrn oc1 (.in(not_out1), .out(out1)); // opndrn is an opndrn oc2 (.in(not_out2), .out(out1)); // open-drain opndrn oc3 (.in(not_out3), .out(out1)); // buffer endmodule
source_codes/v/high_z_oc_tb.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ `timescale 1ns/1ns module high_z_oc_tb; reg in1, in2, in3; wire out1; high_z_oc oc (in1,in2,in3,out1); initial begin #0 in1 = 0; in2 = 0; in3 = 0; #1 in1 = 1; in2 = 0; in3 = 0; #1 in1 = 0; in2 = 1; in3 = 0; #1 in1 = 1; in2 = 1; in3 = 0; #1 in1 = 0; in2 = 0; in3 = 1; #1 in1 = 1; in2 = 0; in3 = 1; #1 in1 = 0; in2 = 1; in3 = 1; #1 in1 = 1; in2 = 1; in3 = 1; #1 in1 = 0; in2 = 0; in3 = 0; #1 $finish; end endmodule
source_codes/v/high_z_tri.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module high_z_tri (in1,in2,in3,out1); // same as high_z_oc.v input in1, in2, in3; // three input signals output out1; // one output signal tri out1; // tri assign out1 = in1 ? 0 : 1'bz; // tri-state signal assign out1 = in2 ? 0 : 1'bz; // can be assigned assign out1 = in3 ? 0 : 1'bz; // multiple times endmodule
source_codes/v/high_z_tri_tb.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ `timescale 1ns/1ns module high_z_tri_tb; reg in1, in2, in3; wire out1; high_z_tri hz (in1,in2,in3,out1); initial begin #0 in1 = 0; in2 = 0; in3 = 0; #1 in1 = 1; in2 = 0; in3 = 0; #1 in1 = 0; in2 = 1; in3 = 0; #1 in1 = 1; in2 = 1; in3 = 0; #1 in1 = 0; in2 = 0; in3 = 1; #1 in1 = 1; in2 = 0; in3 = 1; #1 in1 = 0; in2 = 1; in3 = 1; #1 in1 = 1; in2 = 1; in3 = 1; #1 in1 = 0; in2 = 0; in3 = 0; #1 $finish; end endmodule
source_codes/v/i_cache.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module i_cache ( // direct mapping, 2^6 blocks, 1 word/block input [31:0] p_a, // cpu address output [31:0] p_din, // cpu data from mem input p_strobe, // cpu strobe input uncached, // uncached output p_ready, // ready (to cpu) output cache_miss, // cache miss input clk, clrn, // clock and reset output [31:0] m_a, // mem address input [31:0] m_dout, // mem data out to cpu output m_strobe, // mem strobe input m_ready // mem ready ); reg d_valid [0:63]; // 1-bit valid reg [23:0] d_tags [0:63]; // 24-bit tag reg [31:0] d_data [0:63]; // 32-bit data wire [5:0] index = p_a[7:2]; // block index wire [23:0] tag = p_a[31:8]; // address tag wire c_write; // cache write wire [31:0] c_din; // data to cache integer i; always @ (posedge clk or negedge clrn) if (!clrn) begin for (i=0; i<64; i=i+1) d_valid[i] <= 0; // cleat valid end else if (c_write) d_valid[index] <= 1; // write valid always @ (posedge clk) if (c_write) begin d_tags[index] <= tag; // write address tag d_data[index] <= c_din; // write data end wire valid = d_valid[index]; // read cache valid wire [23:0] tagout = d_tags[index]; // read cache tag wire [31:0] c_dout = d_data[index]; // read cache data wire cache_hit = p_strobe & valid & (tagout == tag); // cache hit assign cache_miss = p_strobe & (!valid | (tagout != tag)); // cache miss assign m_a = p_a; // mem <-- cpu address assign m_strobe = cache_miss ; // read on miss assign p_ready = cache_hit | cache_miss & m_ready; // data ready assign c_write = cache_miss & ~uncached & m_ready; // write cache assign c_din = m_dout; // data from mem assign p_din = cache_hit? c_dout : m_dout; // data from cache or mem endmodule
source_codes/v/i2c.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ `define IDLE 0 // i2c master controller `define START 1 // define states `define TX 2 `define RX 3 `define STOP 4 `define WAIT 5 module i2c (clk,clrn,csn,addr,wrn,d_in,rdn,d_out,i2c_sda,i2c_scl); input clk, clrn; // system clock, 50MHz input csn; // chip select input [1:0] addr; // address input wrn; // write, active low input [7:0] d_in; // data to be sent input rdn; // read, active low output [7:0] d_out; // received data or status inout i2c_sda; // i2c sda, input/output inout i2c_scl; // i2c scl, input/output reg [2:0] prev_state = `IDLE; // previous state reg [2:0] curr_state = `IDLE; // current state reg [2:0] next_state = `IDLE; // next state reg [2:0] pulse_count = 0; // counting i2c_clk cycles reg [3:0] bit_count = 0; // counting number of bits reg [7:0] in_buf; // data to be sent reg tx_ack; // ack sent be master reg [7:0] out_buf; // data received reg rx_ack; // ack received reg txd; // bit to be sent reg scl_h; // high impedance reg sda_h; // high impedance reg started; // = 0 if stop issued // i2c clock reg [4:0] clk_count = 0; // clk / 25 = 2MHz reg i2c_clk = 1; // 2MHz always @(posedge clk or negedge clrn) begin if (!clrn) begin clk_count <= 0; end else begin if (clk_count == 24) clk_count <= 0; else clk_count <= clk_count + 5'd1; if (clk_count <= 12) i2c_clk <= 1; else i2c_clk <= 0; end end // pulse_count and bit_count always @(posedge i2c_clk) begin prev_state <= curr_state; if (pulse_count == 4) pulse_count <= 0; // pulse_count else if ((curr_state != `WAIT) || i2c_scl) pulse_count <= pulse_count + 3'd1; if ((bit_count == 8) && (pulse_count == 4)) bit_count <= 0; // bit_count else if ((curr_state == `TX) || (curr_state == `RX)) begin if (pulse_count == 4) bit_count <= bit_count + 4'd1; end else bit_count <= 0; end // next state and data inputs always @(posedge clk or negedge clrn) begin if (!clrn) begin started <= 0; end else begin case (curr_state) `IDLE: begin if ((!csn) && (!wrn)) begin case (addr) 2'd0: begin next_state <= `START; end 2'd1: begin next_state <= `TX; in_buf <= d_in; end 2'd2: begin next_state <= `RX; tx_ack <= d_in[0]; end 2'd3: begin next_state <= `STOP; end endcase end if (prev_state == `START) started <= 1; end `START: begin if (prev_state == `START) begin case (pulse_count) 3'd3: if (i2c_scl == 0) next_state <= `WAIT; 3'd4: if (i2c_scl == 0) next_state <= `WAIT; else next_state <= `IDLE; default: ; endcase end end `TX: begin if ((bit_count == 8) && (prev_state == `TX)) begin case (pulse_count) 3'd3: if (i2c_scl == 0) next_state <= `WAIT; 3'd4: if (i2c_scl == 0) next_state <= `WAIT; else next_state <= `IDLE; default: ; endcase end end `RX: begin if ((bit_count == 8) && (prev_state == `RX)) begin case (pulse_count) 3'd3: if (i2c_scl == 0) next_state <= `WAIT; 3'd4: if (i2c_scl == 0) next_state <= `WAIT; else next_state <= `IDLE; default: ; endcase end end `STOP: begin if ((pulse_count == 4) && (prev_state == `STOP)) next_state <= `IDLE; started <= 0; end `WAIT: begin if (i2c_scl != 0) next_state <= `IDLE; end endcase end end // current state always @(posedge i2c_clk) begin if (pulse_count == 4) curr_state <= next_state; end // transfer data via i2c bus assign i2c_scl = scl_h ? 1'bz : 1'b0; assign i2c_sda = sda_h ? 1'bz : 1'b0; always @(posedge i2c_clk) begin case (curr_state) `IDLE: begin if (started) begin // started sda_h <= 0; scl_h <= 0; end else begin // stopped sda_h <= 1; scl_h <= 1; end end `START: begin // send start bit if (started) begin // send re-start bit case (pulse_count) 3'd0: begin scl_h <= 1; sda_h <= 0; end 3'd1: begin scl_h <= 1; sda_h <= 1; end 3'd2: begin scl_h <= 1; sda_h <= 1; end 3'd3: begin scl_h <= 1; sda_h <= 1; end 3'd4: begin scl_h <= 1; sda_h <= 0; end endcase end else begin // send start bit case (pulse_count) 3'd0: begin scl_h <= 1; sda_h <= 1; end 3'd1: begin scl_h <= 1; sda_h <= 0; end 3'd2: begin scl_h <= 1; sda_h <= 0; end 3'd3: begin scl_h <= 1; sda_h <= 0; end 3'd4: begin scl_h <= 1; sda_h <= 0; end endcase end end `TX: begin if (bit_count == 8) begin // receive ack/nack case (pulse_count) 3'd0: begin scl_h <= 0; sda_h <= 1; end 3'd1: begin scl_h <= 0; sda_h <= 1; end 3'd2: begin scl_h <= 1; sda_h <= 1; end 3'd3: begin scl_h <= 1; sda_h <= 1; rx_ack <= i2c_sda; end 3'd4: begin scl_h <= 0; sda_h <= 1; end endcase end else begin // send data bit rx_ack <= 1; // no ack case (pulse_count) 3'd0: begin scl_h <= 0; sda_h <= in_buf[7-bit_count]; end 3'd1: begin scl_h <= 0; sda_h <= in_buf[7-bit_count]; end 3'd2: begin scl_h <= 1; sda_h <= in_buf[7-bit_count]; end 3'd3: begin scl_h <= 1; sda_h <= in_buf[7-bit_count]; end 3'd4: begin scl_h <= 0; sda_h <= in_buf[7-bit_count]; end endcase end end `RX: begin if (bit_count == 8) begin // send ack/nack case (pulse_count) 3'd0: begin scl_h <= 0; sda_h <= tx_ack; end 3'd1: begin scl_h <= 0; sda_h <= tx_ack; end 3'd2: begin scl_h <= 1; sda_h <= tx_ack; end 3'd3: begin scl_h <= 1; sda_h <= tx_ack; end 3'd4: begin scl_h <= 0; sda_h <= tx_ack; end endcase end else begin // receive data bit case (pulse_count) 3'd0: begin scl_h <= 0; sda_h <= 1; end 3'd1: begin scl_h <= 0; sda_h <= 1; end 3'd2: begin scl_h <= 1; sda_h <= 1; end 3'd3: begin scl_h <= 1; sda_h <= 1; out_buf[7-bit_count] <= i2c_sda; end 3'd4: begin scl_h <= 0; sda_h <= 1; end endcase end end `STOP: begin // send stop bit case (pulse_count) 3'd0: begin scl_h <= 1; sda_h <= 0; end 3'd1: begin scl_h <= 1; sda_h <= 0; end 3'd2: begin scl_h <= 1; sda_h <= 1; end 3'd3: begin scl_h <= 1; sda_h <= 1; end 3'd4: begin scl_h <= 1; sda_h <= 1; end endcase end `WAIT: begin scl_h <= 1; sda_h <= 1; end endcase end // read from host wire ready = (curr_state == `IDLE) && (next_state == `IDLE); wire [7:0] status = {2'd0,ready,1'b0,rx_ack,curr_state}; assign d_out = (addr == 0) ? out_buf : status; endmodule
source_codes/v/i2c_tb.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ // see display_i2c_eeprom_tb.v
source_codes/v/i2f.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module i2f (d,a,p_lost); // convert integer to float input [31:0] d; // integer output [31:0] a; // float output p_lost; // precision lost wire sign = d[31]; // sign wire [31:0] f5 = sign? -d : d; // absolute wire [31:0] f4,f3,f2,f1,f0; wire [4:0] sa; // shift amount (to 1.f) assign sa[4] = ~|f5[31:16]; // 16-bit 0 assign f4 = sa[4]? {f5[15:0],16'b0} : f5; assign sa[3] = ~|f4[31:24]; // 8-bit 0 assign f3 = sa[3]? {f4[23:0], 8'b0} : f4; assign sa[2] = ~|f3[31:28]; // 4-bit 0 assign f2 = sa[2]? {f3[27:0], 4'b0} : f3; assign sa[1] = ~|f2[31:30]; // 2-bit 0 assign f1 = sa[1]? {f2[29:0], 2'b0} : f2; assign sa[0] = ~f1[31]; // 1-bit 0 assign f0 = sa[0]? {f1[30:0], 1'b0} : f1; assign p_lost = |f0[7:0]; // not 0 wire [22:0] fraction = f0[30:8]; // f0[31] = 1, hidden bit wire [7:0] exponent = 8'h9e - {3'h0,sa}; // 0x9e = 158 = 127 + 31 assign a = (d == 0)? 0 : {sign,exponent,fraction}; endmodule
source_codes/v/i2f_tb.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ `timescale 1ns/1ns module i2f_tb; reg [31:0] d; wire [31:0] a; wire p_lost; i2f i_f (d,a,p_lost); initial begin #00 d = 32'h1fffffff; #10 d = 32'h00000001; #10 d = 32'h7fffff80; #10 d = 32'h7fffffc0; #10 d = 32'h80000000; #10 d = 32'h80000040; #10 d = 32'hffffffff; #10 d = 32'h00000000; end endmodule
source_codes/v/inst_mem.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module inst_mem (a,inst); input [31:0] a; output [31:0] inst; lpm_rom rom (.address(a[7:2]),.q(inst), .inclock(),.outclock(),.memenab()); defparam rom.lpm_width = 32, rom.lpm_widthad = 6, rom.lpm_file = "inst_mem.hex", rom.lpm_outdata = "UNREGISTERED", rom.lpm_address_control = "UNREGISTERED"; endmodule
source_codes/v/iu.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ // pipelined cpu with instruction memory, data memory, and interface to fpu module iu (e1n,e2n,e3n, e1w,e2w,e3w, stall,st,dfb,e3d, clk,memclk,clrn, fs,ft,wmo,wrn,wwfpr,mmo,fwdla,fwdlb,fwdfa,fwdfb,fd,fc,wf,fasmds, pc,inst,ealu,malu,walu,stall_lw,stall_fp,stall_lwc1,stall_swc1); input [31:0] dfb, e3d; input [4:0] e1n, e2n, e3n; input e1w, e2w, e3w, stall, st; input clk, memclk, clrn; // clocks, reset output [31:0] pc, inst, ealu, malu, walu; output [31:0] mmo, wmo; output [4:0] fs, ft, fd, wrn; output [2:0] fc; output wwfpr, fwdla, fwdlb, fwdfa, fwdfb, wf, fasmds; output stall_lw, stall_fp, stall_lwc1, stall_swc1; wire [31:0] bpc,jpc,npc,pc4,ins,dpc4,inst,qa,qb,da,db,dimm,dc,dd; wire [31:0] simm,epc8,alua,alub,ealu0,ealu,sa,eb,mmo,wdi; wire [5:0] op,func; wire [4:0] rs,rt,rd,drn,ern; wire [3:0] aluc; wire [1:0] pcsrc,fwda,fwdb; wire wpcir,wreg,m2reg,wmem,aluimm,shift,jal,z; reg ewfpr,ewreg,em2reg,ewmem,ejal,efwdfe,ealuimm,eshift; reg mwfpr,mwreg,mm2reg,mwmem; reg wwfpr,wwreg,wm2reg; reg [31:0] epc4,ea,ed,eimm,malu,mb,wmo,walu; reg [4:0] ern0,mrn,wrn; reg [3:0] ealuc; dffe32 program_counter (npc,clk,clrn,wpcir,pc); // pc cla32 pc_plus4 (pc,32'h4,1'b0,pc4); // pc+4 mux4x32 next_pc (pc4,bpc,da,jpc,pcsrc,npc); // next pc inst_mem i_mem (pc,ins); // inst memory dffe32 pc_4_r (pc4,clk,clrn,wpcir,dpc4); // pc+4 reg dffe32 inst_r (ins,clk,clrn,wpcir,inst); // ir wire swfp,regrt,sext,fwdf,fwdfe,wfpr; assign op = inst[31:26]; assign rs = inst[25:21]; assign rt = inst[20:16]; assign rd = inst[15:11]; assign ft = inst[20:16]; assign fs = inst[15:11]; assign fd = inst[10:6]; assign func = inst[5:0]; assign simm = {{16{sext&inst[15]}},inst[15:0]}; assign jpc = {dpc4[31:28],inst[25:0],2'b00}; // jump target cla32 br_addr (dpc4,{simm[29:0],2'b00},1'b0,bpc); // branch target regfile rf (rs,rt,wdi,wrn,wwreg,~clk,clrn,qa,qb); // reg file mux4x32 alu_a (qa,ealu,malu,mmo,fwda,da); // forward A mux4x32 alu_b (qb,ealu,malu,mmo,fwdb,db); // forward B mux2x32 store_f (db,dfb,swfp,dc); // swc1 mux2x32 fwd_f_d (dc,e3d,fwdf,dd); // forward wire rsrtequ = ~|(da^db); // (da == db) mux2x5 des_reg_no (rd,rt,regrt,drn); // dest reg iu_control cu (op,func,rs,rt,fs,ft,rsrtequ,ewfpr,ewreg, // control unit em2reg,ern,mwfpr,mwreg,mm2reg,mrn,e1w, e1n,e2w,e2n,e3w,e3n,stall,st,pcsrc,wpcir, wreg,m2reg,wmem,jal,aluc,aluimm,shift, sext,regrt,fwda,fwdb,swfp,fwdf,fwdfe,wfpr, fwdla,fwdlb,fwdfa,fwdfb,fc,wf,fasmds, stall_lw,stall_fp,stall_lwc1,stall_swc1); always @(negedge clrn or posedge clk) // ID/EXE regs if (!clrn) begin ewfpr <= 0; ewreg <= 0; em2reg <= 0; ewmem <= 0; ejal <= 0; ealuimm <= 0; efwdfe <= 0; ealuc <= 0; eshift <= 0; epc4 <= 0; ea <= 0; ed <= 0; eimm <= 0; ern0 <= 0; end else begin ewfpr <= wfpr; ewreg <= wreg; em2reg <= m2reg; ewmem <= wmem; ejal <= jal; ealuimm <= aluimm; efwdfe <= fwdfe; ealuc <= aluc; eshift <= shift; epc4 <= dpc4; ea <= da; ed <= dd; eimm <= simm; ern0 <= drn; end cla32 ret_addr (epc4,32'h4,1'b0,epc8); // pc+8 assign sa = {eimm[5:0],eimm[31:6]}; // shift amount mux2x32 alu_ina (ea,sa,eshift,alua); // alu input a mux2x32 alu_inb (ed,eimm,ealuimm,alub); // alu input b mux2x32 save_pc8 (ealu0,epc8,ejal,ealu); // pc+8 if jal alu al_unit (alua,alub,ealuc,ealu0,z); // alu assign ern = ern0 | {5{ejal}}; // $31 for jal mux2x32 fwd_f_e (ed,e3d,efwdfe,eb); // forward always @(negedge clrn or posedge clk) // EXE/MEM regs if (!clrn) begin mwfpr <= 0; mwreg <= 0; mm2reg <= 0; mwmem <= 0; malu <= 0; mb <= 0; mrn <= 0; end else begin mwfpr <= ewfpr; mwreg <= ewreg; mm2reg <= em2reg; mwmem <= ewmem; malu <= ealu; mb <= eb; mrn <= ern; end data_mem d_mem (mwmem,malu,mb,memclk,mmo); // data memory always @(negedge clrn or posedge clk) // MEM/WB regs if (!clrn) begin wwfpr <= 0; wwreg <= 0; wm2reg <= 0; wmo <= 0; walu <= 0; wrn <= 0; end else begin wwfpr <= mwfpr; wwreg <= mwreg; wm2reg <= mm2reg; wmo <= mmo; walu <= malu; wrn <= mrn; end mux2x32 wb_sel (walu,wmo,wm2reg,wdi); endmodule
source_codes/v/iu_cache_tlb.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module iu_cache_tlb (e1n,e2n,e3n, e1w,e2w,e3w, stall,st,dfb,e3d,clk, memclk,clrn,no_cache_stall,dtlb,fs,ft,wmo,wrn,wwfpr, mmo,fwdla,fwdlb,fwdfa,fwdfb,fd,fc,wf,fasmds,v_pc,pc, inst,ealu,malu,wdi,stall_lw,stall_fp,stall_lwc1, stall_swc1,mem_a,mem_data,mem_st_data,mem_access, mem_write,mem_ready,io); // iu + cache + tlb input clk, memclk, clrn; // clocks and reset input [31:0] mem_data; // main mem data read input [31:0] dfb; // fpu b in id stage input [31:0] e3d; // fpu data in e3 stage input [4:0] e1n, e2n, e3n; // fp reg numbers input e1w, e2w, e3w; // fp reg write enables input stall; // stall by div and sqrt input st; // not used input mem_ready; // main mem ready output [31:0] v_pc; // virtual pc output [31:0] pc; // real pc output [31:0] inst; // inst output [31:0] ealu; // alu output in exe stage output [31:0] malu; // alu output in mem stage output [31:0] wdi; // data to iu reg file output [31:0] mmo; // main mem out in mem stage output [31:0] wmo; // main mem out in wb stage output [31:0] mem_a; // main mem address output [31:0] mem_st_data; // main mem data write output [4:0] fs, ft, fd; // fpu fs, ft, fd output [4:0] wrn; // regfile2w write # for lwc1 output [2:0] fc; // fpu op output mem_access; // main mem access output mem_write; // main mem write enable output wwfpr; // regfile2w we for lwc1 output fwdla; // forward lwc1 data to a output fwdlb; // forward lwc1 data to b output fwdfa; // forward fp data to b output fwdfb; // forward fp data to b output wf; // write fp regfile, id stage output fasmds; // is fp calc, id stage output stall_lw; // stall by lw output stall_fp; // stall by fp data depend. output stall_lwc1; // stall by lwc1 output stall_swc1; // stall by swc1 output no_cache_stall; // no cache stall output dtlb; // dtlb hit output io; // inst rom or data i/o parameter exc_base = 32'h80000008; // int/exc handler entry wire [31:0] bpc,jpc,npc,pc4,ins,dpc4,inst,qa,qb,da,db,dc,dd; wire [31:0] simm,epc8,alua,alub,ealu0,ealu1,ealu,sa,eb; wire [5:0] op,func; wire [4:0] rs,rt,rd,fs,ft,fd,drn,ern; wire [3:0] aluc; wire [1:0] pcsrc,fwda,fwdb; wire wpcir,wreg,m2reg,wmem,aluimm,shift,jal; wire [4:0] e1n,e2n,e3n; reg ewfpr,ewreg,em2reg,ewmem,ejal,efwdfe,ealuimm,eshift; reg mwfpr,mwreg,mm2reg,mwmem; reg wwfpr,wwreg,wm2reg; reg [31:0] epc4,ea,ed,eimm,malu,mb,wmo,walu; reg [4:0] ern0,mrn,wrn; reg [3:0] ealuc; wire [23:0] ipte_out; wire itlb_hit; wire [31:0] pcd; wire [31:0] index; // cp0 reg 0: index wire [31:0] entlo; // cp0 reg 2: entry lo reg [31:0] contx; // cp0 reg 4: context wire [31:0] enthi; // cp0 reg 9: entry hi wire windex,wentlo,wcontx,wenthi; // write enables wire rc0,wc0; // read,write c0 res wire [1:0] c0rn; // c0 reg # for mux wire swfp,regrt,sext,fwdf,fwdfe,wfpr; wire i_ready,i_cache_miss; wire tlbwi,tlbwr; wire wepc,wcau,wsta,isbr,cancel,exce,ldst; wire [1:0] sepc,selpc; wire [31:0] sta,cau,epc,sta_in,cau_in,epc_in; wire [31:0] stalr,epcin,cause,c0reg,next_pc; reg [31:0] pce; reg [1:0] ec0rn; reg erc0,ecancel,eisbr,eldst; reg [31:0] pcm; reg misbr,mldst; wire [23:0] dpte_out; wire dtlb_hit; reg [31:0] pcw; reg wisbr; wire m_fetch,m_ld_st,m_st; wire [31:0] m_i_a,m_d_a; wire itlb_exc, dtlb_exc; wire itlb_exce,dtlb_exce; wire m_i_ready; wire m_d_ready; // IF stage vpc v_p_c (next_pc,clk,clrn,wpcir&no_cache_stall,v_pc); // vpc cla32 pc_plus4 (v_pc,32'h4,1'b0,pc4); // vpc+4 mux4x32 nextpc (pc4,bpc,da,jpc,pcsrc,npc); // next pc wire itlbwi = tlbwi & ~index[30]; // itlb write wire itlbwr = tlbwr & ~index[30]; wire dtlbwi = tlbwi & index[30]; // dtlb write wire dtlbwr = tlbwr & index[30]; wire [19:0] ipattern = (itlbwi | itlbwr)? enthi[19:0] : v_pc[31:12]; wire pc_unmapped = v_pc[31] & ~v_pc[30]; // 10xx...xx wire pc_uncached = pc_unmapped & v_pc[29]; // 101x...xx assign pc = pc_unmapped?{3'b0,v_pc[28:0]} : {ipte_out[19:0],v_pc[11:0]}; tlb_8_entry itlb (entlo[23:0],itlbwi,itlbwr,index[2:0],ipattern, // itlb clk,clrn,ipte_out,itlb_hit); assign itlb_exc = ~itlb_hit & ~pc_unmapped; i_cache icache (pc,ins,1'b1,pc_uncached,i_ready,i_cache_miss, // icache clk,clrn,m_i_a,mem_data,m_fetch,m_i_ready); // IF/ID pipeline registers dffe32 pc_4_r (pc4, clk,clrn,wpcir&no_cache_stall,dpc4); // pc4 dffe32 inst_r (ins, clk,clrn,wpcir&no_cache_stall,inst); // ir dffe32 pcd_r (v_pc,clk,clrn,wpcir&no_cache_stall,pcd); // pcd // ID stage assign op = inst[31:26]; assign rs = inst[25:21]; assign rt = inst[20:16]; assign rd = inst[15:11]; assign ft = inst[20:16]; assign fs = inst[15:11]; assign fd = inst[10:6]; assign func = inst[5:0]; assign simm = {{16{sext&inst[15]}},inst[15:0]}; assign jpc = {dpc4[31:28],inst[25:0],2'b00}; // jump target cla32 br_addr (dpc4,{simm[29:0],2'b00},1'b0,bpc); // branch target regfile rf (rs,rt,wdi,wrn,wwreg,~clk,clrn,qa,qb); // reg file mux4x32 alu_a(qa,ealu,malu,mmo,fwda,da); // forward A mux4x32 alu_b(qb,ealu,malu,mmo,fwdb,db); // forward B mux2x32 store_f (db,dfb,swfp,dc); // swc1 mux2x32 fwd_f_d (dc,e3d,fwdf,dd); // forward fp result wire rsrtequ = ~|(da^db); // (da == db) mux2x5 des_reg_no (rd,rt,regrt,drn); // destination reg iu_cache_tlb_cu cu (op,func,rs,rt,rd,fs,ft,rsrtequ, // control unit ewfpr,ewreg,em2reg,ern,mwfpr,mwreg,mm2reg,mrn,e1w,e1n,e2w, e2n,e3w,e3n,stall,st,pcsrc,wpcir,wreg,m2reg,wmem,jal,aluc, sta,aluimm,shift,sext,regrt,fwda,fwdb,swfp,fwdf,fwdfe, wfpr,fwdla,fwdlb,fwdfa,fwdfb,fc,wf,fasmds,stall_lw, stall_fp,stall_lwc1,stall_swc1,windex,wentlo,wcontx, wenthi,rc0,wc0,tlbwi,tlbwr,c0rn,wepc,wcau,wsta,isbr,sepc, cancel,cause,exce,selpc,ldst,wisbr,ecancel,itlb_exc, dtlb_exc,itlb_exce,dtlb_exce); assign dtlb = ~dtlb_exce; // dtlb hit dffe32 c0_Index (db,clk,clrn,windex&no_cache_stall,index); // index dffe32 c0_Entlo (db,clk,clrn,wentlo&no_cache_stall,entlo); // entlo dffe32 c0_Enthi (db,clk,clrn,wenthi&no_cache_stall,enthi); // enthi always @(negedge clrn or posedge clk) // contx if (!clrn) begin contx <= 0; end else begin if (wcontx) contx[31:22] <= db[31:22]; // PTEBase if (itlb_exce) contx[21:0] <= {v_pc[31:12],2'b00}; // BadVPN else if (dtlb_exce) contx[21:0] <= {malu[31:12],2'b00}; end dffe32 c0_status (sta_in,clk,clrn,wsta&no_cache_stall,sta); // sta dffe32 c0_cause (cau_in,clk,clrn,wcau&no_cache_stall,cau); // cau dffe32 c0_epc (epc_in,clk,clrn,wepc&no_cache_stall,epc); // epc mux2x32 sta_mx (stalr,db,wc0,sta_in); // mux for status reg mux2x32 cau_mx (cause,db,wc0,cau_in); // mux for cause reg mux2x32 epc_mx (epcin,db,wc0,epc_in); // mux for epc reg mux2x32 sta_lr ({8'h0,sta[31:8]},{sta[23:0],8'h0},exce,stalr); mux4x32 epc_04 (v_pc,pcd,pcm,pcw,sepc,epcin); // epc source mux4x32 irq_pc (npc,epc,exc_base,32'h0,selpc,next_pc); // for pc mux4x32 fromc0 (contx,sta,cau,epc,ec0rn,c0reg); // for mfc0 // ID/EXE pipeline registers always @(negedge clrn or posedge clk) begin if (!clrn) begin ewfpr <= 0; ewreg <= 0; eldst <= 0; ewmem <= 0; ejal <= 0; ealuimm <= 0; efwdfe <= 0; ealuc <= 0; eshift <= 0; epc4 <= 0; ea <= 0; ed <= 0; eimm <= 0; ern0 <= 0; erc0 <= 0; ec0rn <= 0; ecancel <= 0; eisbr <= 0; pce <= 0; em2reg <= 0; end else if (no_cache_stall) begin ewfpr <= wfpr; ewreg <= wreg; ewmem <= wmem; eldst <= ldst; ejal <= jal; ealuimm <= aluimm; efwdfe <= fwdfe; ealuc <= aluc; eshift <= shift; epc4 <= dpc4; ea <= da; ed <= dd; eimm <= simm; ern0 <= drn; erc0 <= rc0; ec0rn <= c0rn; ecancel <= cancel; eisbr <= isbr; pce <= pcd; em2reg <= m2reg; end end // EXE stage cla32 ret_addr (epc4,32'h4,1'b0,epc8); // pc+8 assign sa = {eimm[5:0],eimm[31:6]}; // shift amount mux2x32 alu_ina (ea,sa,eshift,alua); // alu input A mux2x32 alu_inb (eb,eimm,ealuimm,alub); // alu input B mux2x32 save_pc8 (ealu0,epc8,ejal,ealu1); // pc+8 if jal mux2x32 read_cr0 (ealu1,c0reg,erc0,ealu); // read c0 regs wire z; alu al_unit (alua,alub,ealuc,ealu0,z); // alu assign ern = ern0 | {5{ejal}}; // $31 for jal mux2x32 fwd_f_e (ed,e3d,efwdfe,eb); // forward fp result // EXE/MEM pipeline registers always @(negedge clrn or posedge clk) begin if (!clrn) begin mwfpr <= 0; mwreg <= 0; mldst <= 0; mwmem <= 0; malu <= 0; mb <= 0; mrn <= 0; misbr <= 0; pcm <= 0; mm2reg <= 0; end else if (no_cache_stall) begin mwfpr <= ewfpr & ~dtlb_exce; // cancel exe mwreg <= ewreg & ~dtlb_exce; // cancel exe mwmem <= ewmem & ~dtlb_exce; // cancel exe mldst <= eldst & ~dtlb_exce; // cancel exe malu <= ealu; mb <= eb; mrn <= ern; misbr <= eisbr; pcm <= pce; mm2reg <= em2reg; end end // MEM stage wire [19:0] dpattern = (dtlbwi | dtlbwr) ? enthi[19:0] : malu[31:12]; wire ma_unmapped = malu[31] & ~malu[30]; // 10xx...xx wire ma_uncached = ma_unmapped & malu[29]; // 101x...xx wire [31:0] m_addr = ma_unmapped? {3'b0,malu[28:0]} : {dpte_out[19:0],malu[11:0]}; tlb_8_entry d_tlb (entlo[23:0],dtlbwi,dtlbwr,index[2:0], // dtlb dpattern,clk,clrn,dpte_out,dtlb_hit); assign dtlb_exc = ~dtlb_hit & ~ma_unmapped & mldst; wire d_ready; wire w_mem = mwmem & ~dtlb_exce; // cancel mem (sw/swc1) d_cache dcache (m_addr,mb,mmo,mldst,w_mem,ma_uncached,d_ready, // dcache clk,clrn,m_d_a,mem_data,mem_st_data,m_ld_st, m_st,m_d_ready); assign io = pc_uncached | ma_uncached; // 101x...xx // MEM/WB pipeline registers always @(negedge clrn or posedge clk) begin if (!clrn) begin wwfpr <= 0; wwreg <= 0; wm2reg <= 0; wmo <= 0; walu <= 0; wrn <= 0; pcw <= 0; wisbr <= 0; end else if (no_cache_stall) begin wwfpr <= mwfpr & ~dtlb_exce; // cancel mem wwreg <= mwreg & ~dtlb_exce; // cancel mem wm2reg <= mm2reg; wmo <= mmo; walu <= malu; wrn <= mrn; pcw <= pcm; wisbr <= misbr; end end // WB stage mux2x32 wb_sel (walu,wmo,wm2reg,wdi); // mux, i_cache has higher priority than d_cache wire sel_i = i_cache_miss; // fetch inst first assign mem_a = sel_i ? m_i_a : m_d_a; // mem address assign mem_access = sel_i ? m_fetch : m_ld_st; // mem access assign mem_write = sel_i ? 1'b0 : m_st; // mem write enable // demux the main mem ready assign m_i_ready = mem_ready & sel_i; // ready for inst assign m_d_ready = mem_ready & ~sel_i; // ready for mem data assign no_cache_stall = ~(~i_ready & ~itlb_exce | // no itlb miss exce mldst & ~d_ready & ~dtlb_exce); // no dtlb miss exce endmodule
source_codes/v/iu_cache_tlb_cu.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module iu_cache_tlb_cu (op,func,rs,rt,rd,fs,ft,rsrtequ,ewfpr,ewreg,em2reg, ern,mwfpr,mwreg,mm2reg,mrn,e1w,e1n,e2w,e2n,e3w,e3n, stall_div_sqrt,st,pcsrc,wpcir,wreg,m2reg,wmem,jal,aluc, sta,aluimm,shift,sext,regrt,fwda,fwdb,swfp,fwdf,fwdfe, wfpr,fwdla,fwdlb,fwdfa,fwdfb,fc,wf,fasmds,stall_lw, stall_fp,stall_lwc1,stall_swc1,windex,wentlo,wcontx, wenthi,rc0,wc0,tlbwi,tlbwr,c0rn,wepc,wcau,wsta,isbr,sepc, cancel,cause,exce,selpc,ldst,wisbr,ecancel,itlb_exc, dtlb_exc,itlb_exce,dtlb_exce); // control unit input rsrtequ, ewreg,em2reg,ewfpr, mwreg,mm2reg,mwfpr; input e1w,e2w,e3w,stall_div_sqrt,st; input [5:0] op,func; input [4:0] rs,rt,rd,fs,ft,ern,mrn,e1n,e2n,e3n; input [31:0] sta; // IM[7:0] : x,x,dtlb_exc,itlb_exc,ov,unimpl,sys,int output wpcir,wreg,m2reg,wmem,jal,aluimm,shift,sext,regrt; output swfp,fwdf,fwdfe; output fwdla,fwdlb,fwdfa,fwdfb; output wfpr,wf,fasmds; output [1:0] pcsrc,fwda,fwdb; output [3:0] aluc; output [2:0] fc; // fp op output stall_lw,stall_fp,stall_lwc1,stall_swc1; // stalls output rc0; // read c0 regs, mfc0 output wc0; // write c0 regs, mtc0 output tlbwi; // write tlb by index output tlbwr; // write tlb by random output [1:0] c0rn,sepc,selpc; // mux select signals output windex; // cp0 index write enable output wentlo; // cp0 entrylo write enable output wcontx; // cp0 context write enable output wenthi; // cp0 entryhi write enable output wepc; // cp0 epc write enable output wcau; // cp0 cause write enable output wsta; // cp0 status write enable output isbr; // inst in id stage is a jump or branch output cancel; // cancel in id stage output exce; // itlb_exce | dtlb_exce, masked output ldst; // inst in id stage is a load or store output [31:0] cause; // cp0 cause reg input wisbr; // inst in wb stage is a jump or branch input ecancel; // cancel in exe stage input itlb_exc; // itlb miss exception input dtlb_exc; // dtlb miss exception output itlb_exce; // itlb miss exception & its enable output dtlb_exce; // dtlb miss exception & its enable wire stall_others; wire rtype,i_add,i_sub,i_and,i_or,i_xor,i_sll,i_srl,i_sra,i_jr; wire i_addi,i_andi,i_ori,i_xori,i_beq,i_bne,i_lw,i_sw,i_j; wire i_jal,i_eret,i_mtc0,i_mfc0; wire ftype,i_lwc1,i_swc1,i_fadd,i_fsub,i_fmul,i_fdiv,i_fsqrt; assign itlb_exce = itlb_exc & sta[4]; // & exc enable assign dtlb_exce = dtlb_exc & sta[5]; // & exc enable wire no_dtlb_exce = ~dtlb_exce; assign ldst = (i_lw | i_sw | i_lwc1 | i_swc1) & ~ecancel & no_dtlb_exce; assign isbr = i_beq | i_bne | i_j | i_jal; // itlb_exce dtlb_exce isbr wisbr EPC sepc[1:0] // 1 x 0 x V_PC 0 0 // 1 x 1 x PCD 0 1 // 0 1 x 0 PCM 1 0 // 0 1 x 1 PCW 1 1 assign sepc[1]= ~itlb_exce & dtlb_exce; assign sepc[0]= itlb_exce & isbr | ~itlb_exce & dtlb_exce & wisbr; assign exce = itlb_exce | dtlb_exce; assign cancel = exce; // selpc: 0 0 : npc // 0 1 : epc // 1 0 : exc_base // 1 1 : x assign selpc[1] = exce; // go to handler assign selpc[0] = i_eret; // epc return // op rs rt rd func // 010000 00100 xxxxx xxxxx 00000 000000 mtc0 rt, rd; c0[rd] <- gpr[rt] // 010000 00000 xxxxx xxxxx 00000 000000 mfc0 rt, rd; gpr[rt] <- c0[rd] // 010000 10000 00000 00000 00000 000010 tlbwi // 010000 10000 00000 00000 00000 000110 tlbwr // 010000 10000 00000 00000 00000 011000 eret assign i_mtc0 = (op==6'h10) & (rs==5'h04) & (func==6'h00)& no_dtlb_exce; assign i_mfc0 = (op==6'h10) & (rs==5'h00) & (func==6'h00); assign i_eret = (op==6'h10) & (rs==5'h10) & (func==6'h18); assign tlbwi = (op==6'h10) & (rs==5'h10) & (func==6'h02); assign tlbwr = (op==6'h10) & (rs==5'h10) & (func==6'h06); assign windex = i_mtc0 & (rd==5'h00); // write index assign wentlo = i_mtc0 & (rd==5'h02); // write entry_lo assign wcontx = i_mtc0 & (rd==5'h04); // write context assign wenthi = i_mtc0 & (rd==5'h09); // write entry_hi assign wsta = i_mtc0 & (rd==5'h0c) | exce | i_eret; // write status assign wcau = i_mtc0 & (rd==5'h0d) | exce; // write cause assign wepc = i_mtc0 & (rd==5'h0e) | exce; // write epc //wire rcontx = i_mfc0 & (rd==5'h04); // read context wire rstatus = i_mfc0 & (rd==5'h0c); // read status wire rcause = i_mfc0 & (rd==5'h0d); // read cause wire repc = i_mfc0 & (rd==5'h0e); // read epc assign c0rn[1]= rcause | repc; // c0rn: 00 01 10 11 assign c0rn[0]= rstatus | repc; // contx sta cau epc assign rc0 = i_mfc0; // read c0 regs assign wc0 = i_mtc0; // write c0 regs wire [2:0] exccode; // test itlb_exc and dtlb_exc // 000 interrupt // not test here // 001 syscall // not test here // 010 unimpl. inst. // not test here // 011 overflow // not test here // 100 itlb_exc // test here // 101 dtlb_exc // test here assign exccode[2] = itlb_exc | dtlb_exc; assign exccode[1] = 0; assign exccode[0] = dtlb_exc; assign cause = {27'h0,exccode,2'b00}; and(rtype,~op[5],~op[4],~op[3],~op[2],~op[1],~op[0]); // r format and(i_add,rtype, func[5],~func[4],~func[3],~func[2],~func[1],~func[0]); and(i_sub,rtype, func[5],~func[4],~func[3],~func[2], func[1],~func[0]); and(i_and,rtype, func[5],~func[4],~func[3], func[2],~func[1],~func[0]); and(i_or, rtype, func[5],~func[4],~func[3], func[2],~func[1], func[0]); and(i_xor,rtype, func[5],~func[4],~func[3], func[2], func[1],~func[0]); and(i_sll,rtype,~func[5],~func[4],~func[3],~func[2],~func[1],~func[0]); and(i_srl,rtype,~func[5],~func[4],~func[3],~func[2], func[1],~func[0]); and(i_sra,rtype,~func[5],~func[4],~func[3],~func[2], func[1], func[0]); and(i_jr, rtype,~func[5],~func[4], func[3],~func[2],~func[1],~func[0]); and(i_addi,~op[5],~op[4], op[3],~op[2],~op[1],~op[0]); // i format and(i_andi,~op[5],~op[4], op[3], op[2],~op[1],~op[0]); and(i_ori, ~op[5],~op[4], op[3], op[2],~op[1], op[0]); and(i_xori,~op[5],~op[4], op[3], op[2], op[1],~op[0]); and(i_lw, op[5],~op[4],~op[3],~op[2], op[1], op[0]); and(i_sw, op[5],~op[4], op[3],~op[2], op[1], op[0]); and(i_beq, ~op[5],~op[4],~op[3], op[2],~op[1],~op[0]); and(i_bne, ~op[5],~op[4],~op[3], op[2],~op[1], op[0]); and(i_lui, ~op[5],~op[4], op[3], op[2], op[1], op[0]); and(i_j, ~op[5],~op[4],~op[3],~op[2], op[1],~op[0]); // j format and(i_jal, ~op[5],~op[4],~op[3],~op[2], op[1], op[0]); and(ftype, ~op[5], op[4],~op[3],~op[2],~op[1], op[0]); // f format and(i_lwc1, op[5], op[4],~op[3],~op[2],~op[1], op[0]); and(i_swc1, op[5], op[4], op[3],~op[2],~op[1], op[0]); and(i_fadd,ftype,~func[5],~func[4],~func[3],~func[2],~func[1],~func[0]); and(i_fsub,ftype,~func[5],~func[4],~func[3],~func[2],~func[1], func[0]); and(i_fmul,ftype,~func[5],~func[4],~func[3],~func[2], func[1],~func[0]); and(i_fdiv,ftype,~func[5],~func[4],~func[3],~func[2], func[1], func[0]); and(i_fsqrt,ftype,~func[5],~func[4],~func[3],func[2],~func[1],~func[0]); wire i_rs = i_add | i_sub | i_and | i_or | i_xor | i_jr | i_addi | i_andi | i_ori | i_xori | i_lw | i_sw | i_beq | i_bne | i_lwc1 | i_swc1; wire i_rt = i_add | i_sub | i_and | i_or | i_xor | i_sll | i_srl | i_sra | i_sw | i_beq | i_bne | i_mtc0; assign stall_lw = ewreg & em2reg & (ern != 0) & (i_rs & (ern == rs) | i_rt & (ern == rt)); reg [1:0] fwda, fwdb; always @ (ewreg or mwreg or ern or mrn or em2reg or mm2reg or rs or rt) begin fwda = 2'b00; // default: no hazards if (ewreg & (ern != 0) & (ern == rs) & ~em2reg) begin fwda = 2'b01; // select exe_alu end else begin if (mwreg & (mrn != 0) & (mrn == rs) & ~mm2reg) begin fwda = 2'b10; // select mem_alu end else begin if (mwreg & (mrn != 0) & (mrn == rs) & mm2reg) begin fwda = 2'b11; // select mem_lw end end end fwdb = 2'b00; // default: no hazards if (ewreg & (ern != 0) & (ern == rt) & ~em2reg) begin fwdb = 2'b01; // select exe_alu end else begin if (mwreg & (mrn != 0) & (mrn == rt) & ~mm2reg) begin fwdb = 2'b10; // select mem_alu end else begin if (mwreg & (mrn != 0) & (mrn == rt) & mm2reg) begin fwdb = 2'b11; // select mem_lw end end end end assign wreg =(i_add | i_sub | i_and | i_or | i_xor | i_sll | i_srl | i_sra | i_addi | i_andi | i_ori | i_xori | i_lw | i_lui | i_jal | i_mfc0) & wpcir & ~ecancel & no_dtlb_exce; assign regrt = i_addi | i_andi | i_ori | i_xori | i_lw | i_lui | i_lwc1 | i_mfc0; assign jal = i_jal; assign m2reg = i_lw; assign shift = i_sll | i_srl | i_sra; assign aluimm = i_addi | i_andi | i_ori | i_xori | i_lw | i_lui | i_sw | i_lwc1 | i_swc1; assign sext = i_addi | i_lw | i_sw | i_beq | i_bne | i_lwc1 | i_swc1; assign aluc[3] = i_sra; assign aluc[2] = i_sub | i_or | i_srl | i_sra | i_ori | i_lui; assign aluc[1] = i_xor | i_sll | i_srl | i_sra | i_xori | i_beq | i_bne | i_lui; assign aluc[0] = i_and | i_or | i_sll | i_srl | i_sra | i_andi | i_ori; assign wmem = (i_sw | i_swc1) & wpcir & ~ecancel & no_dtlb_exce; assign pcsrc[1] = i_jr | i_j | i_jal; assign pcsrc[0] = i_beq & rsrtequ | i_bne & ~rsrtequ | i_j | i_jal; // fop: 000: fadd 001: fsub 01x: fmul 10x: fdiv 11x: fsqrt wire [2:0] fop; assign fop[0] = i_fsub; // fpu operation control code assign fop[1] = i_fmul | i_fsqrt; assign fop[2] = i_fdiv | i_fsqrt; // stall caused by fp data harzards wire i_fs = i_fadd | i_fsub | i_fmul | i_fdiv | i_fsqrt; // use fs wire i_ft = i_fadd | i_fsub | i_fmul | i_fdiv; // use ft assign stall_fp = (e1w & (i_fs & (e1n == fs) | i_ft & (e1n == ft))) | (e2w & (i_fs & (e2n == fs) | i_ft & (e2n == ft))); assign fwdfa = e3w & (e3n == fs); // forward fpu e3d to fp a assign fwdfb = e3w & (e3n == ft); // forward fpu e3d to fp b assign wfpr = i_lwc1 & wpcir & ~ecancel & no_dtlb_exce; // write fp reg assign fwdla = mwfpr & (mrn == fs); // forward mmo to fp a assign fwdlb = mwfpr & (mrn == ft); // forward mmo to fp b assign stall_lwc1 = ewfpr & (i_fs & (ern == fs) | i_ft & (ern == ft)); assign swfp = i_swc1; // select signal assign fwdf = swfp & e3w & (ft == e3n); // forward to id stage assign fwdfe = swfp & e2w & (ft == e2n); // forward to exe stage assign stall_swc1 = swfp & e1w & (ft == e1n); // stall assign wpcir = ~(stall_div_sqrt | stall_others); assign stall_others = stall_lw | stall_fp | stall_lwc1 | stall_swc1 |st; assign fc = fop & {3{~stall_others}}; // fp operation control assign wf = i_fs & wpcir & ~ecancel & no_dtlb_exce; // write fp reg assign fasmds = i_fs; endmodule
source_codes/v/iu_control.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ // control unit of pipelined cpu with memories and interface to fpu module iu_control (op,func,rs,rt,fs,ft,rsrtequ,ewfpr,ewreg,em2reg,ern,mwfpr, mwreg,mm2reg,mrn,e1w,e1n,e2w,e2n,e3w,e3n,stall_div_sqrt, st,pcsrc,wpcir,wreg,m2reg,wmem,jal,aluc,aluimm,shift, sext,regrt,fwda,fwdb,swfp,fwdf,fwdfe,wfpr,fwdla,fwdlb, fwdfa,fwdfb,fc,wf,fasmds,stall_lw,stall_fp,stall_lwc1, stall_swc1); input rsrtequ, ewreg,em2reg,ewfpr, mwreg,mm2reg,mwfpr; input e1w,e2w,e3w,stall_div_sqrt,st; input [5:0] op,func; input [4:0] rs,rt,fs,ft,ern,mrn,e1n,e2n,e3n; output wpcir,wreg,m2reg,wmem,jal,aluimm,shift,sext,regrt; output swfp,fwdf,fwdfe; output fwdla,fwdlb,fwdfa,fwdfb; output wfpr,wf,fasmds; output [3:0] aluc; output [2:0] fc; output [1:0] pcsrc,fwda,fwdb; output stall_lw,stall_fp,stall_lwc1,stall_swc1; wire rtype,i_add,i_sub,i_and,i_or,i_xor,i_sll,i_srl,i_sra; wire i_jr,i_j,i_jal; wire i_addi,i_andi,i_ori,i_xori,i_lw,i_sw,i_beq,i_bne,i_lui; wire ftype,i_lwc1,i_swc1,i_fadd,i_fsub,i_fmul,i_fdiv,i_fsqrt; and(rtype,~op[5],~op[4],~op[3],~op[2],~op[1],~op[0]); // r format and(i_add,rtype, func[5],~func[4],~func[3],~func[2],~func[1],~func[0]); and(i_sub,rtype, func[5],~func[4],~func[3],~func[2], func[1],~func[0]); and(i_and,rtype, func[5],~func[4],~func[3], func[2],~func[1],~func[0]); and(i_or, rtype, func[5],~func[4],~func[3], func[2],~func[1], func[0]); and(i_xor,rtype, func[5],~func[4],~func[3], func[2], func[1],~func[0]); and(i_sll,rtype,~func[5],~func[4],~func[3],~func[2],~func[1],~func[0]); and(i_srl,rtype,~func[5],~func[4],~func[3],~func[2], func[1],~func[0]); and(i_sra,rtype,~func[5],~func[4],~func[3],~func[2], func[1], func[0]); and(i_jr, rtype,~func[5],~func[4], func[3],~func[2],~func[1],~func[0]); and(i_addi,~op[5],~op[4], op[3],~op[2],~op[1],~op[0]); // i format and(i_andi,~op[5],~op[4], op[3], op[2],~op[1],~op[0]); and(i_ori, ~op[5],~op[4], op[3], op[2],~op[1], op[0]); and(i_xori,~op[5],~op[4], op[3], op[2], op[1],~op[0]); and(i_lw, op[5],~op[4],~op[3],~op[2], op[1], op[0]); and(i_sw, op[5],~op[4], op[3],~op[2], op[1], op[0]); and(i_beq, ~op[5],~op[4],~op[3], op[2],~op[1],~op[0]); and(i_bne, ~op[5],~op[4],~op[3], op[2],~op[1], op[0]); and(i_lui, ~op[5],~op[4], op[3], op[2], op[1], op[0]); and(i_j, ~op[5],~op[4],~op[3],~op[2], op[1],~op[0]); // j format and(i_jal, ~op[5],~op[4],~op[3],~op[2], op[1], op[0]); and(ftype,~op[5], op[4],~op[3],~op[2],~op[1], op[0]); // f format and(i_lwc1, op[5], op[4],~op[3],~op[2],~op[1], op[0]); and(i_swc1, op[5], op[4], op[3],~op[2],~op[1], op[0]); and(i_fadd,ftype,~func[5],~func[4],~func[3],~func[2],~func[1],~func[0]); and(i_fsub,ftype,~func[5],~func[4],~func[3],~func[2],~func[1], func[0]); and(i_fmul,ftype,~func[5],~func[4],~func[3],~func[2], func[1],~func[0]); and(i_fdiv,ftype,~func[5],~func[4],~func[3],~func[2], func[1], func[0]); and(i_fsqrt,ftype,~func[5],~func[4],~func[3],func[2],~func[1],~func[0]); wire i_rs = i_add | i_sub | i_and | i_or | i_xor | i_jr | i_addi | i_andi | i_ori | i_xori | i_lw | i_sw | i_beq | i_bne | i_lwc1 | i_swc1; wire i_rt = i_add | i_sub | i_and | i_or | i_xor | i_sll | i_srl | i_sra | i_sw | i_beq | i_bne; assign stall_lw = ewreg & em2reg & (ern != 0) & (i_rs & (ern == rs) | i_rt & (ern == rt)); reg [1:0] fwda, fwdb; always @ (ewreg or mwreg or ern or mrn or em2reg or mm2reg or rs or rt) begin fwda = 2'b00; // default: no hazards if (ewreg & (ern != 0) & (ern == rs) & ~em2reg) begin fwda = 2'b01; // select exe_alu end else begin if (mwreg & (mrn != 0) & (mrn == rs) & ~mm2reg) begin fwda = 2'b10; // select mem_alu end else begin if (mwreg & (mrn != 0) & (mrn == rs) & mm2reg) begin fwda = 2'b11; // select mem_lw end end end fwdb = 2'b00; // default: no hazards if (ewreg & (ern != 0) & (ern == rt) & ~em2reg) begin fwdb = 2'b01; // select exe_alu end else begin if (mwreg & (mrn != 0) & (mrn == rt) & ~mm2reg) begin fwdb = 2'b10; // select mem_alu end else begin if (mwreg & (mrn != 0) & (mrn == rt) & mm2reg) begin fwdb = 2'b11; // select mem_lw end end end end assign wreg =(i_add | i_sub | i_and | i_or | i_xor | i_sll | i_srl | i_sra | i_addi | i_andi | i_ori | i_xori | i_lw | i_lui | i_jal) & wpcir; assign regrt = i_addi | i_andi | i_ori | i_xori | i_lw | i_lui | i_lwc1; assign jal = i_jal; assign m2reg = i_lw; assign shift = i_sll | i_srl | i_sra; assign aluimm= i_addi | i_andi | i_ori | i_xori | i_lw | i_lui | i_sw | i_lwc1 | i_swc1; assign sext = i_addi | i_lw | i_sw | i_beq | i_bne | i_lwc1 | i_swc1; assign aluc[3] = i_sra; assign aluc[2] = i_sub | i_or | i_srl | i_sra | i_ori | i_lui; assign aluc[1] = i_xor | i_sll | i_srl | i_sra | i_xori | i_beq | i_bne | i_lui; assign aluc[0] = i_and | i_or | i_sll | i_srl | i_sra | i_andi | i_ori; assign wmem = (i_sw | i_swc1) & wpcir; assign pcsrc[1] = i_jr | i_j | i_jal; assign pcsrc[0] = i_beq & rsrtequ | i_bne & ~rsrtequ | i_j | i_jal; // fop: 000: fadd 001: fsub 01x: fmul 10x: fdiv 11x: fsqrt wire [2:0] fop; assign fop[0] = i_fsub; // fpu control code assign fop[1] = i_fmul | i_fsqrt; assign fop[2] = i_fdiv | i_fsqrt; // stall caused by fp data harzards wire i_fs = i_fadd | i_fsub | i_fmul | i_fdiv | i_fsqrt; // use fs wire i_ft = i_fadd | i_fsub | i_fmul | i_fdiv; // use ft assign stall_fp = (e1w & (i_fs & (e1n == fs) | i_ft & (e1n == ft))) | (e2w & (i_fs & (e2n == fs) | i_ft & (e2n == ft))); assign fwdfa = e3w & (e3n == fs); // forward fpu e3d to fp a assign fwdfb = e3w & (e3n == ft); // forward fpu e3d to fp b assign wfpr = i_lwc1 & wpcir; // fp rf y write enable assign fwdla = mwfpr & (mrn == fs); // forward mmo to fp a assign fwdlb = mwfpr & (mrn == ft); // forward mmo to fp b assign stall_lwc1 = ewfpr & (i_fs & (ern == fs) | i_ft & (ern == ft)); assign swfp = i_swc1; // select signal assign fwdf = swfp & e3w & (ft == e3n); // forward to id stage assign fwdfe = swfp & e2w & (ft == e2n); // forward to exe stage assign stall_swc1 = swfp & e1w & (ft == e1n); // stall wire stall_others = stall_lw | stall_fp | stall_lwc1 | stall_swc1 | st; assign wpcir = ~(stall_div_sqrt | stall_others); assign fc = fop & {3{~stall_others}}; assign wf = i_fs & wpcir; // fp rf x write enable assign fasmds = i_fs; endmodule
source_codes/v/jkff.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module jkff (j,k,clk,clrn,q); // jkff with asynchronous reset input j, k, clk, clrn; // inputs j, k, clock, reset output reg q; // output q, register type always @ (posedge clk or negedge clrn) begin // always block, "or" if (!clrn) q <= 0; // if clrn is active, reset jkff else q <= j & ~q | ~k & q; // else update jkff end endmodule
source_codes/v/jkff_tb.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ `timescale 1ns/1ns module jkff_tb; reg j, k, clk, clrn; wire q; jkff jk_ff (j,k,clk,clrn,q); initial begin clk = 1; clrn = 0; j = 0; k = 0; #1 clrn = 1; k = 1; #2 k = 0; j = 1; #2 j = 0; #2 k = 1; j = 1; #8 k = 0; j = 0; #2 $finish; end always #1 clk = !clk; endmodule
source_codes/v/mccomp.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module mccomp (clk,clrn,q,a,b,alu,adr,tom,fromm,pc,ir,memclk); input clk, clrn; // clock and reset input memclk; // memory clk for sync ram output [31:0] a; // alu input a output [31:0] b; // alu input b output [31:0] alu; // alu result output [31:0] adr; // memory address output [31:0] tom; // data to memory output [31:0] fromm; // data from memory output [31:0] pc; // program counter output [31:0] ir; // instruction register output [2:0] q; // state wire wmem; // memory write enable mccpu mc_cpu (clk,clrn,fromm,pc,ir,a,b,alu,wmem,adr,tom,q); // cpu mcmem memory (fromm,tom,adr,wmem,memclk); // memory endmodule
source_codes/v/mccomp_tb.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ `timescale 1ns/1ns module mccomp_tb; reg clk,clrn,memclk; wire [31:0] a,b,alu,adr,tom,fromm,pc,ir; wire [2:0] q; mccomp cpu (clk,clrn,q,a,b,alu,adr,tom,fromm,pc,ir,memclk); initial begin clrn = 0; memclk = 0; clk = 1; #1 clrn = 1; #1099 $finish; end always #1 memclk = !memclk; always #2 clk = !clk; endmodule /* 0 - 28 40 - 68 68 - 96 408 - 436 */
source_codes/v/mccpu.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module mccpu (clk,clrn,frommem,pc,inst,alua,alub,alu,wmem,madr,tomem,state); input [31:0] frommem; // data from memory input clk, clrn; // clock and reset output [31:0] pc; // program counter output [31:0] inst; // instruction output [31:0] alua; // alu input a output [31:0] alub; // alu input b output [31:0] alu; // alu result output [31:0] madr; // memory address output [31:0] tomem; // data to memory output [2:0] state; // state output wmem; // memory write enable // instruction fields wire [5:0] op = inst[31:26]; // op wire [4:0] rs = inst[25:21]; // rs wire [4:0] rt = inst[20:16]; // rt wire [4:0] rd = inst[15:11]; // rd wire [5:0] func = inst[05:00]; // func wire [15:0] imm = inst[15:00]; // immediate wire [25:0] addr = inst[25:00]; // address // control signals wire [3:0] aluc; // alu operation control wire [1:0] pcsrc; // select pc source wire wreg; // write regfile wire regrt; // dest reg number is rt wire m2reg; // instruction is an lw wire shift; // instruction is a shift wire [1:0] alusrcb; // alu input b selection wire jal; // instruction is a jal wire sext; // is sign extension wire wpc; // write pc wire wir; // write ir wire iord; // select memory address wire selpc; // select pc // datapath wires wire [31:0] bpc; // branch target address wire [31:0] npc; // next pc wire [31:0] qa; // regfile output port a wire [31:0] qb; // regfile output port b wire [31:0] alua; // alu input a wire [31:0] alub; // alu input b wire [31:0] wd; // regfile write port data wire [31:0] r; // alu out or mem wire [31:0] sa = {27'b0,inst[10:6]}; // shift amount wire [15:0] s16 = {16{sext & inst[15]}}; // 16-bit signs wire [31:0] i32 = {s16,imm}; // 32-bit immediate wire [31:0] dis = {s16[13:0],imm,2'b00}; // word distance wire [31:0] jpc = {pc[31:28],addr,2'b00}; // jump target address wire [4:0] reg_dest; // rs or rt wire [4:0] wn = reg_dest | {5{jal}}; // regfile write reg # wire z; // alu, zero tag wire [31:0] rega; // register a wire [31:0] regb; // register b wire [31:0] regc; // register c wire [31:0] data; // output of dr wire [31:0] opa; // sa or output of reg a // datapath mccu control_unit (op,func,z,clk,clrn, // control unit wpc,wir,wmem,wreg, iord,regrt,m2reg,aluc, shift,selpc,alusrcb, pcsrc,jal,sext,state); dffe32 ip (npc,clk,clrn,wpc,pc); // pc register dffe32 ir (frommem,clk,clrn,wir,inst); // instruction register dff32 dr (frommem,clk,clrn,data); // data register dff32 reg_a (qa, clk,clrn,rega); // register a dff32 reg_b (qb, clk,clrn,regb); // register b dff32 reg_c (alu,clk,clrn,regc); // register c mux2x32 aorsa (rega,sa,shift,opa); // sa or output of reg a mux2x32 alu_a (opa,pc,selpc,alua); // alu input a mux4x32 alu_b (regb,32'h4,i32,dis,alusrcb,alub); // alu input b mux2x32 alu_m (regc,data,m2reg,r); // alu out or mem data mux2x32 mem_a (pc,regc,iord,madr); // memory address mux2x32 link (r,pc,jal,wd); // r or pc mux2x5 reg_wn (rd,rt,regrt,reg_dest); // rs or rt mux4x32 nextpc(alu,regc,qa,jpc,pcsrc,npc); // next pc regfile rf (rs,rt,wd,wn,wreg,clk,clrn,qa,qb); // register file alu alunit (alua,alub,aluc,alu,z); // alu assign tomem = regb; // output of reg b endmodule
source_codes/v/mccu.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module mccu (op,func,z,clk,clrn,wpc,wir,wmem,wreg,iord,regrt,m2reg,aluc, shift,alusrca,alusrcb,pcsrc,jal,sext,state); // control unit input [5:0] op, func; // op, func input clk, clrn; // clock and reset input z; // alu zero flag output reg wpc; // write pc output reg wir; // write ir output reg wmem; // memory write enable output reg wreg; // write regfile output reg iord; // select memory address output reg regrt; // dest reg number is rt output reg m2reg; // instruction is an lw output reg shift; // instruction is a shift output reg alusrca; // select pc output reg jal; // instruction is a jal output reg sext; // is sign extension output reg [3:0] aluc; // alu operation control output reg [1:0] alusrcb; // alu input b selection output reg [1:0] pcsrc; // select pc source output reg [2:0] state; // state reg [2:0] next_state; // next state parameter [2:0] sif = 3'b000, // IF state sid = 3'b001, // ID state sexe = 3'b010, // EXE state smem = 3'b011, // MEM state swb = 3'b100; // WB state wire rtype,i_add,i_sub,i_and,i_or,i_xor,i_sll,i_srl,i_sra,i_jr; wire i_addi,i_andi,i_ori,i_xori,i_lw,i_sw,i_beq,i_bne,i_lui,i_j,i_jal; // and (out, in1, in2, ...); // instruction decode and (rtype,~op[5],~op[4],~op[3],~op[2],~op[1],~op[0]); and (i_add,rtype, func[5],~func[4],~func[3],~func[2],~func[1],~func[0]); and (i_sub,rtype, func[5],~func[4],~func[3],~func[2], func[1],~func[0]); and (i_and,rtype, func[5],~func[4],~func[3], func[2],~func[1],~func[0]); and (i_or, rtype, func[5],~func[4],~func[3], func[2],~func[1], func[0]); and (i_xor,rtype, func[5],~func[4],~func[3], func[2], func[1],~func[0]); and (i_sll,rtype,~func[5],~func[4],~func[3],~func[2],~func[1],~func[0]); and (i_srl,rtype,~func[5],~func[4],~func[3],~func[2], func[1],~func[0]); and (i_sra,rtype,~func[5],~func[4],~func[3],~func[2], func[1], func[0]); and (i_jr, rtype,~func[5],~func[4], func[3],~func[2],~func[1],~func[0]); and (i_addi,~op[5],~op[4], op[3],~op[2],~op[1],~op[0]); and (i_andi,~op[5],~op[4], op[3], op[2],~op[1],~op[0]); and (i_ori, ~op[5],~op[4], op[3], op[2],~op[1], op[0]); and (i_xori,~op[5],~op[4], op[3], op[2], op[1],~op[0]); and (i_lw, op[5],~op[4],~op[3],~op[2], op[1], op[0]); and (i_sw, op[5],~op[4], op[3],~op[2], op[1], op[0]); and (i_beq, ~op[5],~op[4],~op[3], op[2],~op[1],~op[0]); and (i_bne, ~op[5],~op[4],~op[3], op[2],~op[1], op[0]); and (i_lui, ~op[5],~op[4], op[3], op[2], op[1], op[0]); and (i_j, ~op[5],~op[4],~op[3],~op[2], op[1],~op[0]); and (i_jal, ~op[5],~op[4],~op[3],~op[2], op[1], op[0]); wire i_shift = i_sll | i_srl | i_sra; always @* begin // default outputs: wpc = 0; // do not write pc wir = 0; // do not write ir wmem = 0; // do not write memory wreg = 0; // do not write regfile iord = 0; // select pc as address aluc = 4'bx000; // alu operation: add alusrca = 0; // alu a: reg a or sa alusrcb = 2'h0; // alu input b: reg b regrt = 0; // reg dest no: rd m2reg = 0; // select reg c shift = 0; // select reg a pcsrc = 2'h0; // select alu output jal = 0; // not a jal sext = 1; // sign extend case (state) //------------------------------------------------- IF: sif: begin // IF state wpc = 1; // write PC wir = 1; // write IR alusrca = 1; // PC alusrcb = 2'h1; // 4 next_state = sid; // next state: ID end //------------------------------------------------------ ID: sid: begin // ID state if (i_j) begin // j instruction pcsrc = 2'h3; // jump address wpc = 1; // write PC next_state = sif; // next state: IF end else if (i_jal) begin // jal instruction pcsrc = 2'h3; // jump address wpc = 1; // write PC jal = 1; // reg no = 31 wreg = 1; // save PC+4 next_state = sif; // next state: IF end else if (i_jr) begin // jr instruction pcsrc = 2'h2; // jump register wpc = 1; // write PC next_state = sif; // next state: IF end else begin // other instructions aluc = 4'bx000; // add alusrca = 1; // PC alusrcb = 2'h3; // branch offset next_state = sexe; // next state: EXE end end //----------------------------------------------------- EXE: // add sub and or xor sll srl sra lw sw beq bne addi andi ori xori lui // aluc[3] X X X X X 0 0 1 X X X X X X X X X // aluc[2] 0 1 0 1 0 0 1 1 0 0 0 0 0 0 1 0 1 // aluc[1] 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 1 1 // aluc[0] 0 0 1 1 0 1 1 1 0 0 0 0 0 1 1 0 0 sexe: begin // EXE state aluc[3] = i_sra; aluc[2] = i_sub | i_or | i_srl | i_sra | i_ori | i_lui; aluc[1] = i_xor | i_sll | i_srl | i_sra | i_xori | i_beq | i_bne | i_lui; aluc[0] = i_and | i_or | i_sll | i_srl | i_sra | i_andi | i_ori; if (i_beq || i_bne) begin // beq or bne inst pcsrc = 2'h1; // branch address wpc = i_beq & z | i_bne & ~z; // write PC next_state = sif; // next state: IF end else begin // other instruction if (i_lw || i_sw) begin // lw or sw inst alusrcb = 2'h2; // select offset next_state = smem; // next state: MEM end else begin // other instruction if (i_shift) shift = 1; // shift instruction if (i_addi || i_andi || i_ori || i_xori || i_lui) alusrcb = 2'h2; // select immediate if (i_andi || i_ori || i_xori) sext=0; // 0 extend next_state = swb; // next state: WB end end end //----------------------------------------------------- MEM: smem: begin // MEM state iord = 1; // memory address = C if (i_lw) begin // load next_state = swb; // next state: WB end else begin // store wmem = 1; // write memory next_state = sif; // next state: IF end end //------------------------------------------------------ WB: swb: begin // WB state if (i_lw) m2reg = 1; // select memory data if (i_lw || i_addi || i_andi || i_ori || i_xori || i_lui) regrt = 1; // reg dest no: rt wreg = 1; // write register file next_state = sif; // next state: IF end //------------------------------------------------------ END default: begin next_state = sif; // default state: IF end endcase end always @ (posedge clk or negedge clrn) begin if (!clrn) begin state <= sif; // reset state to IF end else begin state <= next_state; // state transition end end endmodule
source_codes/v/mcmem.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module mcmem (dataout,datain,addr,we,memclk); // memory (sram) input [31:0] datain; // mem data input input [31:0] addr; // mem address input we; // write enable input memclk; // sync ram clock output [31:0] dataout; // mem data output lpm_ram_dq ram (.data(datain), // data in .address(addr[7:2]), // word address .we(we), // write enable .inclock(memclk), // in reg clock .outclock(memclk), // out reg clock .q(dataout)); // mem data out defparam ram.lpm_width = 32; // data: 32 bits defparam ram.lpm_widthad = 6; // 2^6 = 64 words defparam ram.lpm_file = "mcmem.hex"; // mem init file defparam ram.lpm_indata = "REGISTERED"; // in reg (data) defparam ram.lpm_outdata = "REGISTERED"; // out reg (data) defparam ram.lpm_address_control = "REGISTERED"; // in reg (a, we) endmodule
source_codes/v/minute_second.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module minute_second (clk,m1,m0,s1,s0,dots); // what's this? input clk; // 50MHz output [6:0] m1, m0; output [6:0] s1, s0; output [3:0] dots; reg sec_clk = 1; reg [24:0] clk_cnt = 0; always @ (posedge clk) begin if (clk_cnt == 25'd24999999) begin clk_cnt <= 0; sec_clk <= ~sec_clk; end else begin clk_cnt <= clk_cnt + 1; end end reg [2:0] min1 = 0, sec1 = 0; reg [3:0] min0 = 0, sec0 = 0; always @ (posedge sec_clk) begin if (sec0 == 4'd9) begin sec0 <= 0; if (sec1 == 3'd5) begin sec1 <= 0; if (min0 == 4'd9) begin min0 <= 0; if (min1 == 3'd5) begin min1 <= 0; end else begin min1 <= min1 + 1; end end else begin min0 <= min0 + 1; end end else begin sec1 <= sec1 + 1; end end else begin sec0 <= sec0 + 1; end end assign m1 = seg7({1'b0,min1}); assign s1 = seg7({1'b0,sec1}); assign m0 = seg7(min0); assign s0 = seg7(sec0); assign dots = {1'b1,sec_clk,2'b11}; // 0 // 5 1 // 6 // 4 2 // 3 function [6:0] seg7; input [3:0] q; case (q) 4'd0 : seg7 = 7'b1000000; 4'd1 : seg7 = 7'b1111001; 4'd2 : seg7 = 7'b0100100; 4'd3 : seg7 = 7'b0110000; 4'd4 : seg7 = 7'b0011001; 4'd5 : seg7 = 7'b0010010; 4'd6 : seg7 = 7'b0000010; 4'd7 : seg7 = 7'b1111000; 4'd8 : seg7 = 7'b0000000; 4'd9 : seg7 = 7'b0010000; default: seg7 = 7'b1111111; endcase endfunction endmodule
source_codes/v/mul_signed.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module mul_signed (a,b,z); // 8x8 signed multiplier input [7:0] a, b; // a, b output [15:0] z; // z = a * b wire [7:0] ab0 = a & {8{b[0]}}; // a or 0 for b[0] wire [7:0] ab1 = a & {8{b[1]}}; // a or 0 for b[1] wire [7:0] ab2 = a & {8{b[2]}}; // a or 0 for b[2] wire [7:0] ab3 = a & {8{b[3]}}; // a or 0 for b[3] wire [7:0] ab4 = a & {8{b[4]}}; // a or 0 for b[4] wire [7:0] ab5 = a & {8{b[5]}}; // a or 0 for b[5] wire [7:0] ab6 = a & {8{b[6]}}; // a or 0 for b[6] wire [7:0] ab7 = a & {8{b[7]}}; // a or 0 for b[7] assign z = (({8'b1,~ab0[7], ab0[6:0]} + // << 0, + 1 in bit 8 {7'b0,~ab1[7], ab1[6:0],1'b0}) + // << 1 ({6'b0,~ab2[7], ab2[6:0],2'b0} + // << 2 {5'b0,~ab3[7], ab3[6:0],3'b0})) + // << 3 (({4'b0,~ab4[7], ab4[6:0],4'b0} + // << 4 {3'b0,~ab5[7], ab5[6:0],5'b0}) + // << 5 ({2'b0,~ab6[7], ab6[6:0],6'b0} + // << 6 {1'b1, ab7[7],~ab7[6:0],7'b0})); // << 7, + 1 in bit 15 endmodule
source_codes/v/mul_signed_tb.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ `timescale 1ns/1ns module mul_signed_tb; reg [7:0] a,b; wire [15:0] z; mul_signed m (a,b,z); initial begin a = 8'hff; b = 8'hff; #5 a = 8'h7f; b = 8'h7f; #5 a = 8'h81; b = 8'h81; #5 a = 8'h7e; b = 8'h7e; #5 a = 8'h82; b = 8'h82; #5 a = 8'h7d; b = 8'h7d; #5 a = 8'h83; b = 8'h83; #5 a = 8'h7e; b = 8'h81; #5 a = 8'h82; b = 8'h7d; #5 a = 8'h00; b = 8'h00; #5 a = 8'h01; b = 8'h01; #5 a = 8'h02; b = 8'h02; #5 a = 8'h03; b = 8'h03; end endmodule
source_codes/v/mul_signed_v2.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module mul_signed_v2 (a,b,z); // 8x8 signed multiplier input [7:0] a, b; // a, b output [15:0] z; // z = a * b reg [7:0] abi[7:0]; // a[i] & b[j] integer i, j; always @* begin for (i = 0; i < 7; i = i + 1) for (j = 0; j < 7; j = j + 1) abi[i][j] = a[i] & b[j]; // a[i] & b[j] for (i = 0; i < 7; i = i + 1) abi[i][7] = ~(a[i] & b[7]); // ~(a[i] & b[7]) for (j = 0; j < 7; j = j + 1) abi[7][j] = ~(a[7] & b[j]); // ~(a[7] & b[j]) abi[7][7] = a[7] & b[7]; end assign z = (({8'b1,abi[0][7:0]} + // << 0, + 1 in bit 8 {7'b0,abi[1][7:0],1'b0}) + // << 1 ({6'b0,abi[2][7:0],2'b0} + // << 2 {5'b0,abi[3][7:0],3'b0})) + // << 3 (({4'b0,abi[4][7:0],4'b0} + // << 4 {3'b0,abi[5][7:0],5'b0}) + // << 5 ({2'b0,abi[6][7:0],6'b0} + // << 6 {1'b1,abi[7][7:0],7'b0})); // << 7, + 1 in bit 15 endmodule
source_codes/v/mul_signed_v2_tb.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ `timescale 1ns/1ns module mul_signed_v2_tb; reg [7:0] a,b; wire [15:0] z; mul_signed_v2 m (a,b,z); initial begin a = 8'hff; b = 8'hff; #5 a = 8'h7f; b = 8'h7f; #5 a = 8'h81; b = 8'h81; #5 a = 8'h7e; b = 8'h7e; #5 a = 8'h82; b = 8'h82; #5 a = 8'h7d; b = 8'h7d; #5 a = 8'h83; b = 8'h83; #5 a = 8'h7e; b = 8'h81; #5 a = 8'h82; b = 8'h7d; #5 a = 8'h00; b = 8'h00; #5 a = 8'h01; b = 8'h01; #5 a = 8'h02; b = 8'h02; #5 a = 8'h03; b = 8'h03; end endmodule
source_codes/v/mux2x1_3s.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module mux2x1_3s (a0, a1, s, y); // multiplexer using tri-state gates input s, a0, a1; // inputs output y; // output // bufif0 (out, in, ctl); // tri-state buffer: ctl==0: out=in; bufif0 b0 (y, a0, s); // ctl == 1: out = high-impedance; // bufif1 (out, in, ctl); // tri-state buffer: ctl==1: out=in; bufif1 b1 (y, a1, s); // ctl == 0: out = high-impedance; endmodule
source_codes/v/mux2x1_3s_tb.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ `timescale 1ns/1ns module mux2x1_3s_tb; reg s,a0,a1; wire y; mux2x1_3s mux2x1 (a0,a1,s,y); initial begin a0 = 0; a1 = 0; s = 0; $display("time\ts\ta1\ta0\ty"); $monitor("%2d:\t%b\t%b\t%b\t%b",$time,s,a1,a0,y); #8 $finish; end always #1 a0 = !a0; always #2 a1 = !a1; always #4 s = !s; endmodule
source_codes/v/mux2x1_behavioral_case_all.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module mux2x1_behavioral_case_all (a0,a1,s,y); // multiplexer, all cases input s, a0, a1; // inputs output y; // output reg y; // y cannot be a wire always @ (s or a0 or a1) begin // always block case (s) // cases: 1'b0: y = a0; // if (s == 0) y = a0; 1'b1: y = a1; // if (s == 1) y = a1; endcase end endmodule
source_codes/v/mux2x1_behavioral_case_default.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module mux2x1_behavioral_case_default (a0,a1,s,y); // multiplexer, default input s, a0, a1; // inputs output y; // output reg y; // y cannot be a wire always @ (s or a0 or a1) begin // always block case (s) // cases: 1'b1: y = a1; // if (s == 1) y = a1; default: y = a0; // other cases y = a0; endcase end endmodule
source_codes/v/mux2x1_behavioral_function_case_all.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module mux2x1_behavioral_function_case_all (a0,a1,s,y); // multiplexer, input s, a0, a1; // inputs // function output y; // output // all cases assign y = sel (a0,a1,s); // call a function with parameters function sel; // function name (= return value) input a,b,c; // notice the order of the input arguments case (c) // cases: 1'b0: sel = a; // if (c==0) return value = a 1'b1: sel = b; // if (c==1) return value = b endcase endfunction endmodule
source_codes/v/mux2x1_behavioral_function_if_else.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module mux2x1_behavioral_function_if_else (a0,a1,s,y); // multiplexer, input s, a0, a1; // inputs // function output y; // output // if else assign y = sel (a0,a1,s); // call a function with parameters function sel; // function name (= return value) input a,b,c; // notice the order of the input arguments if (c) sel = b; // if (c==1) return value = b else sel = a; // if (c==0) return value = a endfunction endmodule
source_codes/v/mux2x1_behavioral_if.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module mux2x1_behavioral_if (a0,a1,s,y); // multiplexer, default first input s, a0, a1; // inputs output y; // output reg y; // y cannot be a wire always @ (s or a0 or a1) begin // always block y = a0; // y = a0; if (s) begin // if (s == 1) y = a1; // y = a1; end end endmodule
source_codes/v/mux2x1_behavioral_if_else.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module mux2x1_behavioral_if_else (a0,a1,s,y); // multiplexer, if else input s, a0, a1; // inputs output y; // output reg y; // y cannot be a wire always @ (s or a0 or a1) begin // always block if (s) begin // if (s == 1) y = a1; // y = a1; end else begin // if (s == 0) y = a0; // y = a0; end end endmodule
source_codes/v/mux2x1_cmos.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module mux2x1_cmos (a0, a1, s, y); // multiplexer using cmos transistors input s, a0, a1; // inputs output y; // output wire sn; // internal wire, output of cmosnot // cmosnot (f, a); // a cmos invert: (out, in) cmosnot inv (sn, s); // cmoscmos (drain, source, n_gate, p_gate); cmoscmos c0 (y, a0, sn, s); cmoscmos c1 (y, a1, s, sn); endmodule
source_codes/v/mux2x1_cmos_tb.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ `timescale 1ns/1ns module mux2x1_cmos_tb; reg s,a0,a1; wire y; mux2x1_cmos mux2x1 (a0,a1,s,y); initial begin a0 = 0; a1 = 0; s = 0; $display("time\ts\ta1\ta0\ty"); $monitor("%2d:\t%b\t%b\t%b\t%b",$time,s,a1,a0,y); #8 $finish; end always #1 a0 = !a0; always #2 a1 = !a1; always #4 s = !s; endmodule
source_codes/v/mux2x1_dataflow1.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module mux2x1_dataflow1 (a0, a1, s, y); // multiplexer, dataflow style input s, a0, a1; // inputs output y; // output assign y = ~s & a0 | s & a1; // logic expression endmodule
source_codes/v/mux2x1_dataflow1_tb.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ `timescale 1ns/1ns module mux2x1_dataflow1_tb; reg s,a0,a1; wire y; mux2x1_dataflow1 mux2x1 (a0,a1,s,y); initial begin a0 = 0; a1 = 0; s = 0; $display("time\ts\ta1\ta0\ty"); $monitor("%2d:\t%b\t%b\t%b\t%b",$time,s,a1,a0,y); #8 $finish; end always #1 a0 = !a0; always #2 a1 = !a1; always #4 s = !s; endmodule
source_codes/v/mux2x1_dataflow2.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module mux2x1_dataflow2 (a0, a1, s, y); // multiplexer, dataflow style input s, a0, a1; // inputs output y; // output assign y = s ? a1 : a0; // if (s==1) y=a1; else y=a0; endmodule
source_codes/v/mux2x1_dataflow2_tb.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ `timescale 1ns/1ns module mux2x1_dataflow2_tb; reg s,a0,a1; wire y; mux2x1_dataflow2 mux2x1 (a0,a1,s,y); initial begin a0 = 0; a1 = 0; s = 0; $display("time\ts\ta1\ta0\ty"); $monitor("%2d:\t%b\t%b\t%b\t%b",$time,s,a1,a0,y); #8 $finish; end always #1 a0 = !a0; always #2 a1 = !a1; always #4 s = !s; endmodule
source_codes/v/mux2x1_gate.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module mux2x1_gate (a0, a1, s, y); // multiplexer using ordinary gates input s, a0, a1; // inputs output y; // output wire sn, a0_sn, a1_s; // internal wires not i0 (sn, s); // not (out, in); and i1 (a0_sn, a0, sn); // and (out, in1, in2); and i2 (a1_s, a1, s ); // and (out, in1, in2); or i3 (y, a0_sn, a1_s); // or (out, in1, in2); endmodule
source_codes/v/mux2x1_gate_tb.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ `timescale 1ns/1ns module mux2x1_gate_tb; reg s,a0,a1; wire y; mux2x1_gate mux2x1 (a0,a1,s,y); initial begin a0 = 0; a1 = 0; s = 0; $display("time\ts\ta1\ta0\ty"); $monitor("%2d:\t%b\t%b\t%b\t%b",$time,s,a1,a0,y); #8 $finish; end always #1 a0 = !a0; always #2 a1 = !a1; always #4 s = !s; endmodule
source_codes/v/mux2x3.v
/************************************************ The Verilog HDL code example is from the book Computer Principles and Design in Verilog HDL by Yamin Li, published by A JOHN WILEY & SONS ************************************************/ module mux2x3 (a0,a1,s,y); input [2:0] a0,a1; input s; output [2:0] y; assign y = (s)? a1 : a0; endmodule