Engineering Writing

SEMICONDUCTOR MANUFACTURING -- The Past and the Future

Dr. Craig R. Barrett Intel Corporation

Chandler. AZ

Extended Abstract

The t r e n d s d o m i n a t i n g t h e s e m i c o n d u c t o r industry show no signs of diminishing. Lithography dimensions continue to decrease a n d chip sizes continue to increase, resulting in functional density increases t h a t predict 50- 100 million transistors per chip in the 1990's. The sophistication of clean r o o m e n v i r o n m e n t a l c o n t r o l s a n d p r o c e s s equipment specifications are rapidly escalating the cost of entering the manufacturing business. With this backdrop, it is significant that the selling price for today's complicated circuits, like 1 M b DRAMs, a r e almost identical to t h e initial 1 K DRAMs produced in t h e early 1970's. Will t h i s trend continue? What requirements will be placed on the materials suppliers, the equipment manufacturers, a n d the VLSI producers to continue this relentless march? This paper examines several of these fundamental questions with the backdrop of a n industry beset by periodic economic cycles and a tendency toward international overcapacity.

OUTLINE:

Technology Trends in VLSI Process and Manufacturing Technology

Requirements Capital Intensity of V L S I Manufacturing Process Equipment Requirements What Will We Have to do Differently

Where is the Manufacturing Leverage? What are the Next Generation Problems?

in the 199O's?

1988 CONFIRMATION OF MOORE'S LAW

10M

n 0 a W n

E 100K W z 0 n z

1M

10K

A MEMORY '

I

1970 1974 1978 1982 1986 1 9 9 0

CH2699 7/89/0000 0001 $1 .OO &! 1989 I E E E

1

5

a

n

U ) K

J

6

PROCESS EQUIPMENT COSTS 5 0 0 0 1 1

0 0 0

t- v) 0 0 t- z W

!E

E 3

2 0 0 0 1 SUBMICRON STEPPER t 1000

5 0 0

2 0 0

100

5 0

2 0

-

150 MM WAFER STEPPER

3- CONTACT

I l 1 1 1 1 1 1 1 i

1972 1976 1980 1984 1988

CAPITAL EQUIPMENT DOLLARS/ WAFER START

20 :: ;I 18

16

14

12

10

8

6

4

2

0

FACTO R Y 0 UTP UT THEORETICAL 100%

OUTPUT

ASSUMES:

50% EQUIPMENT UTILIZATION 90% WAFER LINE YIELD 7 5 % PROBE YIELD

50% -+ 90% ASSEMBLY/TEST YIELD 4 5 1 - w ACTUAL OUTPUT

3 4 % + 31% -+

ACTUAL OUTPUT

lntematio~l Semiconductor Manufactuting Science Symposium '89 1