Digital Circuit Project

1 | P a g e M. McNeal Project 1 ECE 171

ECE 171

Project 1

November 13, 2014

Meghan McNeal

Problem Description

Problem

 A circuit must be designed that converts a BCD digit into a Braille symbol using Texas Instruments 74HTC components.

Requirements

 The circuit input must be a 4 bit BCD digit  The circuit output must indicate whether each dot in the Braille symbol is raised (1) or not

(0). These dots should be labeled B1 thru B6.  Boolean equations and circuit logic should be in SOP form.  Assumed propagation delay must be based off of Texas Instruments 74HTC components

that could be used to build said circuit.  Circuit will be described using a Verilog behavioral dataflow description.  Design will have a Verilog structural description using logic gates in the 74HTC family.  Circuit will be tested a vigorously as possible using the Verilog testbench.

Project Deliverables

Project report

 Circuit black box  Circuit truth tables  K-maps for circuit logic  Boolean equations for circuit logic in SOP form  Verilog behavioral dataflow description of the circuit  Verilog structural description of the circuit  Verilog test bench for the circuit  Timing diagram generated by Verilog for the circuit  Schematic of the circuit  Bill of materials for the circuit  Analysis of worst case scenario propagation delay

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Approach/Methodology

1. Determine the inputs and outputs needed for the circuit and draw a black box. 2. Make a truth table using the desired input and output values. 3. Use the truth table to create k-maps for the logic of each of the outputs in reference to the

inputs 4. Use the k-maps to determine the Boolean equations for each of the outputs in reference to the

inputs 5. Write a Verilog behavior dataflow description code for the proposed circuit 6. Write a Verilog test bench code for the proposed circuit to test the behavioral dataflow code. 7. Test the Verilog behavioral dataflow and test bench code 8. Compare timing diagrams to expected output 9. Make alterations to assumptions, logic, and code as needed 10. Repeat steps 8 thru 10 as needed 11. Determine the desired chips for the circuit and their specifications 12. Write/alter a Verilog structural description code for the proposed circuit 13. Test the Verilog structural description code using the test bench code 14. Make alterations to the structural description code as needed 15. Repeat steps 11 thru 14 as needed 16. Create a schematic and bill of materials 17. Write project report

Design Work

Image 1: Black box diagram of the proposed circuit showing inputs, outputs, and module name

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D3 D2 D1 D0 B1 B2 B3 B4 B5 B6

0 0 0 0 0 0 1 0 1 1 0

1 0 0 0 1 1 0 0 0 0 0

2 0 0 1 0 1 1 0 0 0 0

3 0 0 1 1 1 0 0 1 0 0

4 0 1 0 0 1 0 0 1 1 0

5 0 1 0 1 1 0 0 0 1 0

6 0 1 1 0 1 1 0 1 0 0

7 0 1 1 1 1 1 0 1 1 0

8 1 0 0 0 1 1 0 0 1 0

9 1 0 0 1 0 1 0 1 0 0

- 1 0 1 0 - - - - - -

- 1 0 1 1 - - - - - -

- 1 1 0 0 - - - - - -

- 1 1 0 1 - - - - - -

- 1 1 1 0 - - - - - -

- 1 1 1 1 - - - - - -

Inputs Outputs

Decimal # B.C.D. # Braille #

Table 1: Truth table for proposed circuit showing decimal numbers, relevant BCD digit inputs, and braille dot outputs for each input

00 01 11 10

00 0 1 1 1

01 1 1 1 1

11 - - - -

10 1 0 - -

B1

D1, D0

D3, D2

00 01 11 10

00 1 0 0 1

01 0 0 1 1

11 - - - -

10 1 1 - -

B2

D1, D0

D3, D2

00 01 11 10

00 0 0 0 0

01 0 0 0 0

11 - - - -

10 0 0 - -

B3

D1, D0

D3, D2

Table 2 Table 3 Table 4

00 01 11 10

00 1 0 1 0

01 1 0 1 1

11 - - - -

10 0 1 - -

B4

D1, D0

D3, D2

00 01 11 10

00 1 0 0 0

01 1 1 1 0

11 - - - -

10 1 0 - -

B5

D1, D0

D3, D2

00 01 11 10

00 0 0 0 0

01 0 0 0 0

11 - - - -

10 0 0 - -

B6

D1, D0

D3, D2

Table 5 Table 6 Table 7

Table 2 – Table 7: K-maps for braille dot outputs as related to BCD digit inputs with markings for Boolean equation logic for behavior dataflow description

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Reduced SOP Equations for Braille Dot Outputs as Related to BCD Digit Inputs for Behavioral

Dataflow Description

𝐵1 = 𝐷3 ∙ 𝐷0̅̅ ̅̅ + 𝐷3̅̅ ̅̅ ∙ 𝐷2 + 𝐷3̅̅ ̅̅ ∙ 𝐷0 + 𝐷1

𝐵2 = 𝐷2̅̅ ̅̅ ∙ 𝐷0̅̅ ̅̅ + 𝐷3 ∙ 𝐷2̅̅ ̅̅ + 𝐷2 ∙ 𝐷1 + 𝐷1 ∙ 𝐷0̅̅ ̅̅

𝐵3 = 𝑛𝑜𝑛 = 0

B4 = 𝐷3̅̅ ̅̅ ∙ 𝐷1̅̅ ̅̅ ∙ 𝐷0̅̅ ̅̅ + 𝐷3 ∙ 𝐷0 + 𝐷1 ∙ 𝐷0 + 𝐷2 ∙ 𝐷1

𝐵5 = 𝐷2 ∙ 𝐷0 + 𝐷1̅̅ ̅̅ ∙ 𝐷0̅̅ ̅̅

B6 = 𝑛𝑜𝑛 = 0

Translation of SOP Equations for use in Structural Description using NAND Gates instead of AND or OR Gates

As seen in the Lecture 6 on Digital Circuits by Professor Mark G. Faust in ECE 171, Fall 2014, a Boolean equation that expresses AND and OR gates can be expressed using only NAND gates as well. This is more easily expressed pictorially, but in the interest of time it can also be expressed mathematically as follows:

Output Gate

Dataflow Equation AND to NAND OR to NAND Structural Equation

B1 𝐷3 ∙ 𝐷0̅̅ ̅̅ + 𝐷3̅̅ ̅̅ ∙ 𝐷2 + 𝐷3̅̅ ̅̅ ∙ 𝐷0 + 𝐷1 𝐷3 ∙ 𝐷0̅̅ ̅̅̅̅ ̅̅ ̅̅ ̅̅ ̅̅ + 𝐷3̅̅ ̅̅ ∙ 𝐷2̅̅ ̅̅ ̅̅ ̅̅ ̅̅

+ 𝐷3̅̅ ̅̅ ∙ 𝐷0̅̅ ̅̅ ̅̅ ̅̅ ̅̅ + 𝐷1 𝐷3 ∙ 𝐷0̅̅ ̅̅̿̿ ̿̿ ̿̿ ̿̿ ̿̿ + 𝐷3̅̅ ̅̅ ∙ 𝐷2̿̿ ̿̿ ̿̿ ̿̿ ̿̿

+ 𝐷3̅̅ ̅̅ ∙ 𝐷0̿̿ ̿̿ ̿̿ ̿̿ ̿̿ + 𝐷1̅̅ ̅̅

𝐷3 ∙ 𝐷0̅̅ ̅̅ + 𝐷3̅̅ ̅̅ ∙ 𝐷2 +

𝐷3̅̅ ̅̅ ∙ 𝐷0 + 𝐷1̅̅ ̅̅

B2 𝐷2̅̅ ̅̅ ∙ 𝐷0̅̅ ̅̅ + 𝐷3 ∙ 𝐷2̅̅ ̅̅ + 𝐷2 ∙ 𝐷1 + 𝐷1 ∙ 𝐷0̅̅ ̅̅ 𝐷2̅̅ ̅̅ ∙ 𝐷0̅̅ ̅̅̅̅ ̅̅ ̅̅ ̅̅ ̅̅ + 𝐷3 ∙ 𝐷2̅̅ ̅̅̅̅ ̅̅ ̅̅ ̅̅ ̅̅

+ 𝐷2 ∙ 𝐷1̅̅ ̅̅ ̅̅ ̅̅ ̅̅ + 𝐷1 ∙ 𝐷0̅̅ ̅̅̅̅ ̅̅ ̅̅ ̅̅ ̅̅ 𝐷2̅̅ ̅̅ ∙ 𝐷0̅̅ ̅̅̿̿ ̿̿ ̿̿ ̿̿ ̿̿ + 𝐷3 ∙ 𝐷2̅̅ ̅̅̅̅ ̅̅ ̅̅ ̅̅ ̅̅

̅̅ ̅̅ ̅̅ ̅̅ ̅̅

+ 𝐷2 ∙ 𝐷1̿̿ ̿̿ ̿̿ ̿̿ ̿̿ + 𝐷1 ∙ 𝐷0̅̅ ̅̅̿̿ ̿̿ ̿̿ ̿̿ ̿̿

𝐷2̅̅ ̅̅ ∙ 𝐷0̅̅ ̅̅ + 𝐷3 ∙ 𝐷2̅̅ ̅̅ +

𝐷2 ∙ 𝐷1 + 𝐷1 ∙ 𝐷0̅̅ ̅̅

B4 𝐷3̅̅ ̅̅ ∙ 𝐷1̅̅ ̅̅ ∙ 𝐷0̅̅ ̅̅ + 𝐷3 ∙ 𝐷0 + 𝐷1 ∙ 𝐷0 + 𝐷2

∙ 𝐷1 𝐷3̅̅ ̅̅ ∙ 𝐷1̅̅ ̅̅ ∙ 𝐷0̅̅ ̅̅̅̅ ̅̅ ̅̅ ̅̅ ̅̅ ̅̅ ̅̅ ̅̅ + 𝐷3 ∙ 𝐷0̅̅ ̅̅ ̅̅ ̅̅ ̅̅

+ 𝐷1 ∙ 𝐷0̅̅ ̅̅ ̅̅ ̅̅ ̅̅ + 𝐷2 ∙ 𝐷1̅̅ ̅̅ ̅̅ ̅̅ ̅̅ 𝐷3̅̅ ̅̅ ∙ 𝐷1̅̅ ̅̅ ∙ 𝐷0̅̅ ̅̅̿̿ ̿̿ ̿̿ ̿̿ ̿̿ ̿̿ ̿̿ ̿̿ + 𝐷3 ∙ 𝐷0̿̿ ̿̿ ̿̿ ̿̿ ̿̿

+ 𝐷1 ∙ 𝐷0̿̿ ̿̿ ̿̿ ̿̿ ̿̿ + 𝐷2 ∙ 𝐷1̿̿ ̿̿ ̿̿ ̿̿ ̿̿

𝐷3̅̅ ̅̅ ∙ 𝐷1̅̅ ̅̅ ∙ 𝐷0̅̅ ̅̅ + 𝐷3 ∙ 𝐷0

+𝐷1 ∙ 𝐷0 + 𝐷2 ∙ 𝐷1

B5 𝐷2 ∙ 𝐷0 + 𝐷1̅̅ ̅̅ ∙ 𝐷0̅̅ ̅̅ 𝐷2 ∙ 𝐷0̅̅ ̅̅ ̅̅ ̅̅ ̅̅ + 𝐷1̅̅ ̅̅ ∙ 𝐷0̅̅ ̅̅̅̅ ̅̅ ̅̅ ̅̅ ̅̅ 𝐷2 ∙ 𝐷0̿̿ ̿̿ ̿̿ ̿̿ ̿̿ + 𝐷1̅̅ ̅̅ ∙ 𝐷0̅̅ ̅̅̿̿ ̿̿ ̿̿ ̿̿ ̿̿ 𝐷2 ∙ 𝐷0 + 𝐷1̅̅ ̅̅ ∙ 𝐷0̅̅ ̅̅

Table 8: Transformation of Boolean equations using AND and OR gates to NAND gates

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Verilog Source Code

Image 2: Verilog behavioral dataflow code for proposed circuit

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Image 3: Verilog structural description code for proposed circuit

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Image 4: Verilog Test Bench code to test behavioral dataflow code and structural description code for proposed circuit

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Timing Diagram for Behavioral Dataflow Code Simulation

Image 5: Timing Diagram for Verilog’s simulation the behavioral dataflow code using an assumed propagation delay of 10 time units

Timing Diagram for Structural Description Code Simulation

Image 6: Timing Diagram for Verilog’s simulation of the structural description code using typical propagation delays of specific gates in the Texas Instruments 7400HCT family

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Circuit Schematic

Image 7: Schematic for the proposed circuit, drawn using LTspice IV, positive logic, and IEEE digital symbols

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Bill of Materials

Amount Part # Chip Purpose Schematic Designator

1 CD74HCT04 Logic Hex Inverter U1

U2

U3

U4

U5

U6

U7Dual 4-Input NAND GatesCD74HCT202

Bill of Materials

4 SN74HCT00 Quadrupal 2-Input Positive-NAND Gates

Table 9: Bill of materials for proposed circuit with parts from Texas Instruments and reference designators from the circuit’s schematic

In Conclusion

Due to the logic gates available for Texas Instruments in the 74HCT family, it was decided to use DC75HCT04 inverters, and SN74HCT00 & SN74HCT20 NAND gates to design this circuit. These choices were made to make the circuit as efficient and cheap as possible, while using the components available. The timing for the structural description and the test bench code was written using the typical propagation delays described for each chip at 25°C in nanoseconds. Since the typical delays were used for the code, there is some room in the calculations for extreme propagation delay values for the circuit based off of the data sheets supplied for each chip. These are as follows:

Min Typ Max Min Max Min Max

CD74HCT04 tPLH, t PHL CL = 50 pF 4.5 V - - 19 ns - 24 ns - 29 ns

CD74HCT04 tPLH, t PHL CL = 15 pF 5 V - 7 ns - - - -

SN74HCT00 tpd - 4.5 V - 11 ns 25 ns

SN74HCT00 tpd - 5.5V - 10 ns 22 ns

CD74HCT20 tPLH, t PHL CL = 50 pF 2 V - - 100 ns - 125 ns - 150 ns

CD74HCT20 tPLH, t PHL CL = 50 pF 4.5 V - - 20 ns - 25 ns - 30 ns

CD74HCT20 tPLH, t PHL CL = 50 pF 6 V - - 17 ns - 21 ns - 26 ns

CD74HCT20 tPLH, t PHL CL = 15 pF 5 V - 8 ns - - - - -

Chip

Test

Conditions

25° C -40° C to 85° C -55° C to 125° C

VccSymbol

Tale 10: Propagation delays as described by Texas Instrument data sheets, found at http://www.ti.com/lit/ds/symlink/cd74hct04.pdf on 11/7/2014, http://www.ti.com/lit/ds/symlink/cd74hct00.pdf on

11/9/2014, and http://www.ti.com/lit/ds/symlink/cd74hct20.pdf on 11/9/2014

Looking at this chart, one can see that some of the extreme delays can be ignored due to incompatible test conditions. If all chips in the circuit are operating with a 4.5 V Vcc at one of the temperatures on the extreme end of the spectrum, it is possible that some of the braille dot output could take at least 84 ns to propagate from input to output. This would be a predictable worst case scenario.

Under standard conditions, the circuit would be expected to perform much more like the Verilog simulations. Braille dot outputs would be most reliable directly before in the input signal change for the next number using the described timing. The timing could be altered to widen the window of reliable results.