Mixed Methodology

Hitachi Adopts Cadence AMS Model-Based Methodology and Tools for Mixed-Signal Design Verification; Accelerated mixed-signal verification by 160X for one of its largest designs and reduced full-chip simulation time to 30 minutes Publication info: M2 Presswire ; Coventry [Coventry]02 June 2016.

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ABSTRACT  

SAN JOSE, Calif. -- Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that Hitachi, Ltd. (TSE:6501)

has adopted a Cadence(R) Analog Mixed-Signal (AMS) model-based methodology and tools to shorten the

verification cycle for one of its largest mixed-signal design projects. By upgrading its previous transistor-level

methodology to a model-based methodology, Hitachi successfully accelerated mixed-signal verification for this

project by 160X and reduced full-chip simulation time to 30 minutes. The results were achieved by comparing the

transistor-level and the model-based methodology on the same four CPUs. The significant reduction in the

verification cycle time provided Hitachi with the ability to meet time-to-market goals for designs that integrate both

analog and digital functions. FULL TEXT  

M2 PRESSWIRE-June 2, 2016-Hitachi Adopts Cadence AMS Model-Based Methodology and Tools for Mixed-Signal

Design Verification; Accelerated mixed-signal verification by 160X for one of its largest designs and reduced full-

chip simulation time to 30 minutes

(C)2016 M2 COMMUNICATIONS http://www.m2.com

June 2, 2016

SAN JOSE, Calif. -- Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that Hitachi, Ltd. (TSE:6501)

has adopted a Cadence(R) Analog Mixed-Signal (AMS) model-based methodology and tools to shorten the

verification cycle for one of its largest mixed-signal design projects. By upgrading its previous transistor-level

methodology to a model-based methodology, Hitachi successfully accelerated mixed-signal verification for this

project by 160X and reduced full-chip simulation time to 30 minutes. The results were achieved by comparing the

transistor-level and the model-based methodology on the same four CPUs. The significant reduction in the

verification cycle time provided Hitachi with the ability to meet time-to-market goals for designs that integrate both

analog and digital functions.

With its previous transistor-level methodology, Hitachi predominantly relied on block-level verification followed by

tuning analog-digital interfaces to ensure full-chip functionality, which typically required multiple, costly iterations.

By using a Verilog-AMS real number modeling and simulation flow supported by a full set of Cadence tools-

Virtuoso(R) Analog Design Environment (ADE), Spectre(R) Accelerated Parallel Simulator (APS), Spectre eXtensive

Partitioning Simulator (XPS), Virtuoso AMS Designer and Incisive(R) Enterprise Simulator-Hitachi reduced

iterations and met its accuracy requirements, ultimately speeding time to market.

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For more information on the Cadence tools, please visit www.cadence.com/news/hitachi.

"We've had a trusted partnership with Cadence for many years, and our effective collaboration produced a design

environment that significantly improved our productivity and helped us achieve design goals," said Satoshi Ueno,

director of Design Engineering Second Department, Technology Development Operation 1, IT Platform Products

Management Division, Information and Communication Technology Business Division at Hitachi, Ltd. "Cadence

has the behavioral modeling expertise, methodology and tools that we needed to reduce our verification time and

enable us to thoroughly verify our design-not just at the block level, but at the full-chip level, which includes

sensitive analog-digital interfaces. The gains achieved have had a positive impact on our business, and we also

plan to evaluate the Cadence tools and methodology for medical applications and various other system

applications."

About Cadence

Cadence enables global electronic design innovation and plays an essential role in the creation of today's

integrated circuits and electronics. Customers use Cadence software, hardware, IP and services to design and

verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and

computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and

research facilities around the world to serve the global electronics industry. More information about the company,

its products and its services is available at www.cadence.com.

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Publication title: M2 Presswire; Coventry

Publication year: 2016

Publication date: Jun 2, 2016

Publisher: Normans Media Ltd

Place of publication: Coventry

Country of publication: United Kingdom, Coventry

Publication subject: Communications

Source type: Wire Feeds

Language of publication: English

Document type: News

ProQuest document ID: 1793386486

Document URL: https://search.proquest.com/docview/1793386486?accountid=32521

Copyright: (Copyright M2 Communications, 2016)

Last updated: 2016-06-02

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