LTSPICE simulation

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Project 1 10/20/2020 Start your project with a short (1 paragraph for each problem) executive summary of your approach and results. In most cases, this is the only thing your audience (i.e. management) will be reading at work. Follow up with details of your simulation setup and results.

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1) In Midterm 1, Question 1, you were asked to plot the IDS/VDS curves for an NMOS (W=0.3µm, L=0.18µm)

and PMOS (W=0.3µm, L=0.18µm) transistor in the TSMC 0.18um process with the following conditions: NMOS tox = 4.1x10-9 m, VTN0 = 0.35V, µn0 = 327 cm2/V-s PMOS tox = 4.1x10-9 m, VTP0 = -0.41V, µp0 = 128 cm2/V-s Plot the IDS vs. VDS curves for NMOS (W=0.3µm, L=0.18µm), VGS=0, 0.9V, and 1.8V PMOS (W=0.3µm, L=0.18µm), VGS=0, -0.9V, and -1.8V (a) Use SPICE (suggested LTSPICE) to create the IDS/VDS curves for the same transistor sizes

HINT: use a nested .DC operating point analysis (b) Superimpose your hand calculated values from Midterm 1 onto the same graph (c) Explain what you would consider are significant differences between the curves

1.8V0.9V0.45V 01.35V-1.8V -0.9V -0.45V-01.35V VDS

IDS

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2) Simulate the LOWEST CLOCK frequency for which this latch would retain a LOGIC ONE using the SPICE models for the TSMC 0.18um process.Assume the following:

a) Minimum Valid Voltage for LOGIC ONE = 1.3 Volts b) Maximum Voltage for LOGIC ONE = 1.8 Volts

LOWEST CLOCK Frequency = _____________________

CLOCK

INPUT M1

W/L = 2µm/0.18µm

M2 W/L =

1µm/0.18µm

M3 W/L =

2µm/0.18µm

STORAGE NODE 1.8 V