Digital Circuit Project

ECE 171

Spring 2018

Project 1

With security the big deal it is, a local startup, XStep, has created their own BCD encoding for banking

transactions. They want all BCD information converted to their proprietary encoding before it is

formally encrypted and stored. You’ve been hired to create a device that can convert a single BCD digit

to their “encrypted” XStep value.

Decimal BCD XStep Value

0 0000 1100

1 0001 1001

2 0010 0000

3 0011 1010

4 0100 1000

5 0101 0011

6 0110 1111

7 0111 0001

8 1000 0110

9 1001 0101

Design a circuit that implements the change controller using SOP form. Be sure to show truth tables, K-

maps, and reduced equations. Describe your circuit using a Verilog behavioral dataflow description and

simulate it by writing a testbench. Assume the device has a propagation delay of 5 time units.

You can compile and simulate your Verilog program using the Verilogger software system or any other

Verilog environment. Save and print the simulator timing diagram so that you can include it in your final

report.

After you get your behavioral dataflow model working and verified, create a Verilog structural

description for the same design and verify it. You may use any of the actual logic gates in the 74HCT

family. Be sure to model your design using actual 74HCT family propagation delay values for the devices

you chose. This means specifically that your Verilog program must assign tPLH and tPHL values to every

gate. You can get these from the 74HCT data sheets, which can be found on the Texas Instruments web

site (www.ti.com) – click on “Logic” under Find Products. Some are also available via links on the course

page. You do not need to use SOP form for the structural description, but if the logic you implement for

the structural description differs from the equations you obtained for the dataflow model, you need to

show how you derived them.

Note that this means that your total propagation delay will be determined by actual devices and will

differ from the dataflow design you did. You can use the same testbench that you used to verify your

dataflow description (though you may need to change the timing).

Since this is your first time working with XStep, they have requested regular check-ins. This is worth

10% of the final project grade! Feedback will be provided from XStep (and me) on your design based on

these check-ins; missing points can be regained by correcting the final version if (and only if) something

is turned in for the check in. If you miss a check-in, the points cannot be regained.

• Monday 4/9 Development Environment

o Turn in a screenshot of a successful compilation of the provided program.

• Monday 4/16 Truth Tables

o Turn in your truth tables for the design.

• Monday 4/23 Kmaps

o Turn in your initial Kmaps for the design.

• Monday 4/30 Circuit

o Turn in a drawing (hand drawn is fine) for the final circuit for the design.

This final report must include

1. A brief problem description

a. The problem your circuit solves

b. Specific requirements

2. The project deliverables (exactly what you are generating)

3. Approach/methodology (the steps you will take to solve the problem)

4. Your design work (“black box” diagram, truth table, K-map, reduced equations)

5. Verilog source code listings (for both designs and the testbench)

6. The timing diagram showing how your design performed

7. A schematic with reference designators and bill of materials

8. A statement indicating the worst-case propagation delay of your circuit (indicating the input and

output and delay).

While your schematic may be hand-drawn, you will receive 5 points extra credit if you use a schematics

capture package to produce it. Options available on MCECS computers include LTSpice and Orcad

Capture.

Your report must be typed, stapled and submitted on 8.5 x 11 inch paper. Do not use any kind of report

cover. K-maps can be hand-drawn.