Programable Logic controller questions 1-3

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MODULE TITLE: PROGRAMMABLE LOGIC CONTROLLERS

TOPIC TITLE: PROGRAMMABLE FACILITIES

LESSON 3: SHIFT REGISTERS

PLC - 6 - 3

Published by Teesside University Open Learning (Engineering)

School of Science & Engineering

Teesside University

Tees Valley, UK

TS1 3BA

+44 (0)1642 342740

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________________________________________________________________________________________

INTRODUCTION ________________________________________________________________________________________

In this lesson we are concerned totally with the device known as a shift

We start by briefly considering hardware shift registers which can normally be

obtained in integrated circuit package form or be constructed from a number of

separate sequential logic gate devices. The operational similarities between

such hardware shift registers and the software versions found to be

implemented as facilities within PLCs are discussed so that their use in ladder

diagrams may be understood.

The applications examined during the lesson concentrate on the provision of

sequential stepping of outputs, which is probably the most common use of this

facility. It is also the easiest to understand. More complex arrangements of

shift registers within ladder diagrams are possible but these are not examined

in this module.

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________________________________________________________________________________________

YOUR AIMS ________________________________________________________________________________________

Upon completion of this lesson you should be able to:

• understand the basic operation of various types of hardware shift

registers

• relate the similarities between hardware shift registers and PLC ones

• state a suitable order of inputs for ladder diagram shift register

symbols

• explain the operation of PLC shift registers

• design ladder diagrams to obtain output step sequences by the use of

PLC shift registers

• design step sequence diagrams using cascaded shift registers.

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________________________________________________________________________________________

SHIFT REGISTERS ________________________________________________________________________________________

From previous work, both in this module and in the microprocessor module,

the idea of a register as being a grouping of temporary electronic storage cells

collected together in blocks of eight, sixteen or thirty-two should now be well

established. To reinforce this, a register is often drawn in diagrammatic form

as a row of boxes, each being capable of holding a single bit of information,

which, in digital binary terms, must be either a logic 1 or a logic 0.

An eight-bit register has eight individual bits or one byte of information. A

sixteen-bit register has sixteen individual bits or two bytes of information and

so on. In Lesson 3 of Topic 5, bit manipulation, in the form of successively

shifting individual bits one position to the right or left through a register, was

described. In essence, this is the basis of the operation of the device known as

a shift register.

Shift registers are made as standard integrated circuits which are readily

available for use in digital circuit applications (control, communication etc.).

They can be purchased in different construction technologies to cater for

speed, power, propagation delay and cost variations. A brief examination of

the operation of a typical shift register known as a ‘Parallel-in, Serial-out’

device would show, for example, eight bits of data loaded, as a byte, into the

data register in one operation. The application of pulses (known as the ‘clock’)

to a separate input has the effect of moving, or shifting, the data bits one bit

position along through the register, in the same way that the microprocessor

‘shift’ instruction did in lesson PLC - 5 - 3. At the extreme end of the register

the bit in the last bit position becomes available as a logic level on an output

pin.

The diagrams of FIGURE 1 and FIGURE 2 illustrate this behaviour.

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FIG. 1

FIG. 2

As successive clock pulses are applied the byte of data progressively moves

(shifts) towards the single output of the register, one bit at a time. When all

eight bits of the byte have been serially clocked out of the register it is assumed

to be empty (or cleared). It cannot be ‘empty’ in a physical sense because

being a digital binary device each logic level remaining must be either a 1 or a

0 (normally all 0’s). However, once the register is cleared it becomes available

to accept a new data byte, reloaded in a parallel form.

Logic 1 output

Shift clock pulse

After the clock pulse is applied

'Empty' bit position

Shift register

1 1 1 1 10 0 1

Logic levels on the parallel input pins

1 1 1 1 1 10 0

Shift clock pulse input

Shift register Bit output register

One bit of

output data

Load data (effectively close the

switch then open it)

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A second type of shift register, referred to as a ‘Serial-in, Parallel-out’ type,

essentially works in the reverse way from that described in the previous

paragraph. A single input data line carrying a logic level is applied to the

level of the input line is transferred (or shifted) to become the logic level in the

first bit position of the register (FIGURE 3). The application of the next clock

pulse shifts this bit level to the second bit position and transfers into the first

bit position the current level of the serial input line. This may still be the same

level as it previously was or it may have been changed to the opposite level

before the clock pulse arrived. For an eight-bit register, when all eight bits

have been clocked into their bit positions an output signal is applied to allow

the eight logic levels to be output, in parallel fashion, to eight separate lines or

an eight line bus (see FIGURES 3 and 4).

FIG. 3

Clock pulse input

Shift register

1 Single data line input

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FIG. 4

A third possibility is the ‘Serial-in, Serial-out’ shift register. Such an eight-bit

input line and a single signal output line. The eight bit values are clocked into

the register, held there for a brief period and then clocked out (as shown in

FIGURE 5 below).

FIG. 5

Shift clock-out

Shift register

Single data

input line

Single data

output line

Bit output register

Bit input register

Shift clock-in

Parallel output data lines

1 0 1 1 0 00 1

Output data

Shift register

Parallel output control

(Close switch to load output

data register)

Single data line input

Shift clock pulse input

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As you can appreciate from the brief descriptions given, variations in hardware

shift registers do exist. In emulating these devices when they are implemented

by a PLC, various features are taken from different shift registers, which may

make the PLC version appear as a hybrid.

In the main, the PLC implementation of shift registers is likely to be purely by

software, since greater flexibility then becomes possible.

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________________________________________________________________________________________

PLC SHIFT REGISTERS ________________________________________________________________________________________

From the foregoing description of hardware shift registers, it is clear that a

shift register may have numerous input or output signals as well as the

necessary clocking control which causes the shifting operations. FIGURE 6

shows a typical ladder diagram symbol for a PLC shift register. Each device

must carry its own identification to distinguish it from others in the diagram so

that the PLC operates on the correct device. In FIGURE 6, SFT 0 represents

shift register 0.

FIG. 6

Reference to FIGURE 6 shows that three input lines are being used. In a

program listing derived from the ladder diagram, it is obviously important that

the inputs are specified in the correct order. The first input, shown as the rung

containing input contacts 003, is taken to be the data signal input. This is

equivalent to the single serial input line of the serial-in type of hardware

device.

The second rung is the input line which provides the clocking control to cause

the shifting of the data bits through the register.

Input data

Clock

Reset

SFT 0

007

003

005

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The third rung contains the elements which provide a reset action affecting all

bits of the register simultaneously, i.e. a master reset. A suitable signal on this

line causes every bit within the register to be cleared to a logic 0. A word of

warning should be given about the action of this reset line similar to that

mentioned for the reset line of the counters in Lesson 2. Some PLCs require

this line to be closed to cause reset, whilst others require it to be an open

circuit for similar action. If this reset line is held active (closed or open as

necessary) then the shift register will be held disabled.

The shift register symbol used on the ladder diagram does not normally

indicate the identification of the register bits being controlled. This

information can be obtained from the machine manual. In some cases the

may even be made into sixteen bits by cascading two separate eight bit

registers. To obtain the most flexible use of the register each individual bit

position needs to be identified by code/number and regarded, during

programming, as being a memory cell relay designated for shift register use.

The diagram of FIGURE 6 has been amended by showing an eight-bit register

attached to the shift register symbol (to become FIGURE 7). Each bit position

of the register is identified by a relay number which can be interrogated, to

determine its logic state, at some other point within the ladder diagram. This

representation of appending the register onto the ladder symbol is used here

purely for descriptive purposes. It would not normally appear on a ladder

diagram.

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FIG. 7

The identification and numbering used here are taken from a leading

manufacturer's machine.

PLC SHIFT REGISTER OPERATION

It is important to understand the basic operation of the shift register before

attempting to use it within control applications. Referring to FIGURE 7, if the

input contacts 005 are closed then each relay (50 through to 57) will reset to 0

and will remain reset whilst 005 contacts remain closed.

When contacts 005 open the device is enabled to act as a shift register.

Thereafter, as long as contacts 005 remain open, the logic state of the input

data line will be clocked into the register at each successive pulse of the clock

input. In an attempt to make this a more graphic explanation we will need to

assume some logic levels over a sequence of events. FIGURE 8 shows the

state of the device after the application of the reset.

Input data

Clock

Reset

SFT 0

007

003

005

Shift register relays

50 51 52 53 54 55 56 57

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FIG. 8

Assume that, after reset, the input contacts 003 are closed (representing a logic

1) when the clock input 007 contacts close then open again. This provides one

clock pulse which causes the logic state of each register relay to be shifted one

position along and the input level to be transferred to the first register bit

position. In our diagram the input level goes into relay 50 causing it to be

switched on (all other relays are presently off). See FIGURE 9 below.

FIG. 9

If a second clock pulse is now applied then the logic 1 state of relay 50 is

shifted to relay 51 (switching it on) and the current level at the data input (003

contacts still closed) is transferred into relay 50. Relays 50 and 51 will then be

on. FIGURE 10 shows the condition of the register relays after the second

clock pulse.

All other relays switched off

50 51 52 53 54 55 56 57

1 0 0 0 0 0 0

Relay switched

Each relay switched off

50 51 52 53 54 55 56 57

0 0 0 0 0 0 0 0

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FIG. 10

Assume now that input contacts 003 are opened and then a third clock pulse is

applied. The state of relay 51 is shifted to relay 52 (switching it on), the state

of relay 50 is shifted to relay 51 (keeping it switched on) and the current input

data level (now logic 0 because contacts 003 are open) is transferred into relay

50 (switching it off). FIGURE 11 shows the register condition after this clock

pulse.

FIG. 11

The shifting of data into the relays within the register continues in this way

after each clock pulse. After eight clock pulses the original input data status

will be in relay 57. The next clock pulse causes the status of relay 57 to be

shifted out and lost because relay 57 is the last relay within our eight bit

The relays associated with any shift register are memory cells within the PLC

memory. They are not physical output relays and therefore they cannot

themselves drive an output. Contacts defined by shift register relays can,

50 51 52 53 54 55 56 57

0 1 1 0 0 0 0 0

Relays switched

These relays

off

50 51 52 53 54 55 56 57

1 1 0 0 0 0 0 0

These relays

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however, be used to drive a physical output relay. The diagram of FIGURE 12

shows relay contacts from shift register relays being used to drive (switch on

or off) outputs. A program listing for the diagram is also given. Compare the

diagram and the listing to check that you can follow the program.

FIG. 12

PROGRAM LISTING

STEP OP CODE OPERAND

000 LD 003 – data input line 001 LD 007 – clock input line 002 LD 005 – reset conditions line 003 SFT0 – shift register identification 004 LD 50 005 OUT 20 006 LD 53 007 OUT 27 008 END

shift register relay 53 being used to drive ooutput 27} shift register relay 50 being used to drive ooutput 20}

SFT 0007

003

005

OUT 20

OUT 27

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You should now be able to analyse the operation of the circuit of FIGURE 12

over a number of clocking inputs with varying data input levels. However,

imagine that you are seeing this diagram for the first time. If you attempt to

read the diagram without reference to the machine manual there is no way of

knowing that contacts 50 and 53 are designated as being part of a shift register

because the diagram does not indicate this.

Be careful in future reading of PLC ladder diagrams.

The shift register appears to have a straightforward, almost mechanised,

operation. To obtain some level of understanding of its typical use in control

applications simple examples need to be examined.

Possibly the most straightforward use of a shift register is in the production of

a sequence of step operations which require virtually no feedback and the

minimum of input signals.

Consider an application where five digital outputs from a PLC are to be used

to control banks of lights in a set sequence of steps. Each move from step to

step is controlled by a switch input acting as clock. The required step

sequence is shown by the chart of FIGURE 13.

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FIG. 13

After reset the sequence is to be initiated by the pressing of a push-to-make

switch connected to a first ring input, thereafter the whole sequence should run

through once before the initialisation process is again required.

Consider, as a solution, the diagram of FIGURE 14. Input 002 is the initiating

contact and 007 the clock.

STEP NO.

RESET

7 (RESET)

OUT 0

OUT 1

OUT 2

OUT 3

OUT 4

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FIG. 14

To obtain the chart sequence the following action is required:

1. Close and open 005 contacts to cause reset of all shift register relays (all

outputs will switch off).

2. Press and release the push switch connected to input 002. The memory

relay 20 is used to remember that the push has been pressed. Relay 20

MR20 50

OUT 0

OUT 3

OUT 2

002

MR 20

MR20

005

007

SFT 0

OUT 1

OUT 4

50 51 52 53 54 55 56 57

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therefore switches on providing a logic 1 level at the data input to the

shift register.

3. Close and open 007 clocking contacts. The data input (logic 1) is

transferred to relay 50 which switches on. Contacts from shift register

relay 50 are used twice in the diagram.

In rung 1 the 50 contacts open to unlatch memory relay 20 (this puts

a logic 0 on the data input to the shift register).

At rung 5, the closing of the 50 contacts switches on output OUT 0 to

provide step 1 of the chart.

4. The next clock pulse (007 contacts) shifts the 1 from relay 50 to 51, the

current data input level (logic 0) is transferred to relay 50.

This provides step 2 of the chart. Relay 51 is switched on and therefore

contacts 51 in rungs 5 and 6 are closed. Outputs OUT 0 and OUT 1 will

be on.

5. The next clock pulse shifts the logic 1 from relay 51 to 52.

OUT 1 and OUT 2 are switched on.

6. The next clock pulse shifts the logic 1 from relay 52 to 53.

OUT 2 and OUT 3 are switched on.

7. The next clock pulse shifts the logic 1 from relay 53 to 54.

OUT 3 and OUT 4 are now on.

8. The next clock pulse shifts the logic 1 from relay 54 to 55.

Only rung 9 contains contacts 55 which switch on OUT 4.

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9. The next clock pulse shifts the logic 1 from relay 55 to 56.

All outputs will now be switched off and the 56 contacts in parallel with

005 in the reset line will cause reset of the shift register.

Examination of the operation shows that only one logic 1 was applied, as data,

at the initialisation of the sequence. Thereafter this same one was shifted

through the register with its progress being used to drive outputs at particular

times, thus obtaining the required sequence.

With this use of the register the contact numbers which are required to drive

the outputs can be obtained by reference to the chart of FIGURE 15. Where an

output is to be on, the relay containing a 1 at that time can have its number

entered into the chart. The ladder diagram information can then be extracted

straight from the chart.

The chart of FIGURE 15 is partially filled in. Complete the chart by writing the

number of the relay containing a 1 at the intersection of the step number and the

output when that output is required to be on. (Output OUT 0 is already done.)

FIG. 15

STEP NO.

RESET

OUT 0

ON 50

ON 51

OUT 1

OUT 2

OUT 3

OUT 4

RELAY WITH 1

RESET

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Notice that the OUT 0 column contains the relay numbers 50 and 51. These

two numbers appear as ORed contacts to switch on OUT 0 in the ladder

diagram of FIGURE 14.

Now compare the numbers which you have entered into the chart with the

ORed numbers of the contacts shown for each output on FIGURE 14. They

should be the same.

With this use of a shift register any sequence which the chart may dictate can

be mapped out, with the contacts being chosen with ease by pure extraction.

The main limitation to this method is that the length of the register determines

the maximum number of possible different steps in the sequence. The

clocking could be applied on a regular timed interval basis to make the

sequence appear as an automatic progression of switching events. For

instance, suppose the chart sequence of FIGURE 15 required a fixed time

period of, say, 60 seconds between each step after the initialisation input. The

output from a 60 second timer could then be used to clock the register (instead

of input 007).

The diagram of FIGURE 16 is very similar to that of FIGURE 14. Read the

diagram to determine the circuit operation.

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FIG. 16

See if you can answer the following questions.

MR21 56MR20

MR 21

TIM00 60 SECS

TIM00MR21

005

MR20 50002

MR 20

MR20

005

TIM00

SFT 0

OUT 0

OUT 1

OUT 2

OUT 3

OUT 4

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1. Why is relay 21 necessary in the diagram?

....................................................................................................................................................

________________________________________________________________________________________

Relay 20 is used to remember the momentary closure of input 002, to latch the

memory relay 21 and to provide the initial logic 1 at the input to the shift

any one time, relay 20 must be switched off by the data input (logic 1) being

transferred to relay 50. The timer, on the other hand, is required to be switched

on by the closing of input 002, thereafter to provide a free-running pulse to

operate the shift register clock. Relay 20 indirectly enables the timer via the

21 relay. Thereafter 21 retains the timer in the enabled mode until such time as

the shift register relay is energised or the reset input 005 is operated.

2. Input contacts 005 are being used as a stop and reset control. Why should a set

of 005 contacts appear in rung 2?

....................................................................................................................................................

________________________________________________________________________________________

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Relay 21 must be able to be stopped (disabled) by a suitable input signal (005

in this case). If it is not reset at the same time as the other devices then the

next time that 002 input is pressed there is no guarantee that the first timed

period would be of the correct duration.

3. Rung 3 has a set of AND NOT TIM 00 contacts. What is the purpose of these?

....................................................................................................................................................

________________________________________________________________________________________

The AND NOT TIM00 contacts in rung 3 are used to disable the timer almost

immediately after it has just timed out. When TIM00 output switches on, the

N/C TIM00 contacts in rung 3 will open and disable the timer. The timer will

switch off and then begin the timing all over again. This operation ensures a

relatively long off-time followed by a very short on-time, which is repeated

until a reset action is applied to release relay 21.

If the sequence is intended to continue on a cyclic basis until forced to stop and

is then reset by the application of input 005, then contacts 56 can be removed

from the reset line and be placed in parallel with the 002 input contacts. The

AND NOT 56 contacts in rung 2 would need to be removed.

Redraw the circuit with these changes and check through its operation.

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________________________________________________________________________________________

SHIFT REGISTER CASCADES ________________________________________________________________________________________

For applications where longer step sequences are required a sixteen-bit shift

registers then two eight-bit devices may be cascaded. In the case, when the

logic level leaves the last relay of the first register it is transferred into the first

relay position of the second register. It is then shifted through the second in

the same manner as the first. The same clocking and reset controls would

normally be required for both shift registers. The part diagram of FIGURE 17

shows two shift registers. SFT0 controls relays 50 to 57 and SFT1 controls

relays 60 to 67. The reset is by applying input 005 and the clocking is by input

007. Both registers are reset and clocked at the same time. The logic level of

the last relay (57) in SFT0 is the data input feed to SFT1. The overall

operation is, therefore, as that of a sixteen-bit register.

FIG. 17

SFT 0007

003

005

SFT 1007

005

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In more complicated applications the clocking, data and reset inputs would be

derived from circuit elements within the execution of the program, which

means that the clocking would not necessarily be on a regular basis.

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________________________________________________________________________________________

NOTES ________________________________________________________________________________________

....................................................................................................................................................

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________________________________________________________________________________________

SELF-ASSESSMENT QUESTIONS ________________________________________________________________________________________

1. Briefly describe the operation of a Serial-in, Parallel-out shift register.

2. FIGURE 18 shows a PLC ladder diagram symbol for a shift register.

Explain the significance of each input into the register.

FIG. 18

3. Draw out the section of a ladder diagram covered by the following part of

its listing.

STEP OP CODE OPERAND

043 LD 027

044 LD 007

045 LD 005

046 SFT3

047 LD 071

048 OUT 024

049 LD 074

050 OUT 026

012

TIM01 SFT 2

020

001

CNT0

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If shift register SFT3 controls the eight relays from 70 to 77, determine

and explain the circuit operation if the data input is a logic 1 for the first

clock pulse and a logic 0 thereafter.

4. This question is a repeat of question 2 from the Self-Assessment section

of Lesson 2. Solve the problem this time by the use of one three-second

timer and two eight-bit shift registers.

Design a ladder diagram circuit which will fulfil the following specification:

With the application of a momentary switch closure an output from the

PLC is to come on. After 3 seconds this output is to switch off and a

second output switch on for a further period of 6 seconds, before it

switches off.

When the second output switches off the first output must switch back on

to begin a repeat of the 3 second on /6 second off operation.

When the second output switches off for the fourth time the sequence is

considered complete and both outputs remain switched off until the next

momentary switch closure.

FIGURE 8 of Lesson 2 shows the timing diagram.

First output

Second output

3 seconds

6 seconds

Off

Time axis

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________________________________________________________________________________________

ANSWERS TO SELF-ASSESSMENT QUESTIONS ________________________________________________________________________________________

1. A Serial-in, Parallel-out shift register is a device which accepts data

currently available on a single data input line and transfers this data, on

the application of a clocking pulse, into the first bit position of a multibit

position along to make provision for the ‘new’ bit level. The contents of

the register may all be read (or made available) at the output pins of the

device, at any time, by applying a suitable signal level on an output

control pin.

2. The three inputs to the shift register symbol are (in order from top to

bottom) the data input, the clocking input and the reset input. For the

diagram shown, a logic 1 will be available at the data input only if 012

contacts and 020 contacts are simultaneously closed. The clocking input

pulse can be provided by either 001 contacts or TIM01 contacts. Some

care is needed with this ORing arrangement because if one set of contacts

is closed then effectively the other set is locked out until the first set

opens again. This is due to the edge sensitive operation. Reset of the

3. Compare your diagram with that of FIGURE 19.

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FIG. 19

The logic 1 level at the data input would clock through the register with

each successive clock pulse. After the first clock pulse relay 70 will be

switched on but the section of the program does not show relay 70 driving

an output. After the second clock pulse, relay 71 will be switched on

which means that output OUT 024 will also be on. The next clock pulse

switches off output OUT 024. A further two clock pulses will be required

before output OUT 026 comes on. Any further clocking will mean that

all outputs are off, a condition which can also occur if at any time

contacts 005 are closed.

4. The chart of FIGURE 20 shows the requirement of the step sequences.

The relay numbering provides the contact numbers for the ladder

diagram. FIGURE 21 shows a suitable ladder diagram for comparison

with your own.

SFT 3007

027

005

071

074

OUT 024

OUT 026

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FIG. 20

STEP NO.

RESET

OUT 0

OUT 1

RESET

Change to second register

3 seconds on

2 × 3 seconds on}

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FIG. 21

36 64

R000

3050001 000

30 000

001

INPUT 001 IS THE

MOMENTARY INPUT

INPUT 000 IS A

MASTER RESET

SFT 0

SFT 1

R000

000

TIM0

TIM0 TIM0

000

3 SECS

OUT 21

OUT 20

TIM0

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________________________________________________________________________________________

SUMMARY ________________________________________________________________________________________

This lesson has concentrated on the operation and typical uses of the device

known as a shift register. The applications chosen as examples of usage were

small and are likely to represent only a proportion of the control requirements

of a system. The ladder diagrams may seem quite large for such small

operations but the size of the diagram is of less importance than the ease of

programming or subsequent reading and understanding of the diagram (which

may be quite some time after actual design).

When using shift registers it is important to establish which register relays are

being controlled by any particular register. In the main, these would be set and

stated by the manufacturer (in the manual), but it is possible on certain

machines for the relays (or channels of relays) to be selected by the

programmer. When this is the case it is imperative that the selection is fully

documented for future use.

This lesson may not have covered all aspects of shift register usage but

sufficient coverage has been made for the majority of purposes.

Teesside University Open Learning (Engineering)

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setdistillerparams << /HWResolution [2400 2400] /PageSize [612.000 792.000] >> setpagedevice