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MODULE TITLE: PROGRAMMABLE LOGIC CONTROLLERS

TOPIC TITLE: THE STRUCTURE OF THE PLC

LESSON 1: INSIDE THE CPU OF THE PLC

PLC - 5 - 1

Published by Teesside University Open Learning (Engineering)

School of Science & Engineering

Teesside University

Tees Valley, UK

TS1 3BA

+44 (0)1642 342740

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________________________________________________________________________________________

INTRODUCTION ________________________________________________________________________________________

In a previous lesson we came across a schematic diagram of a CPU showing

how the CPU related to the read-only (ROM) and random access memories

(RAM). The theoretical operation of these memories was also covered and the

‘fetch and execute cycle’ of the CPU. In this lesson we are going to look in a

little more detail at the internal arrangements of the CPU.

The internal architecture of CPUs varies greatly from one type of machine to

another. However, we will here deal with CPUs in a general way to give you

an appreciation of the internal arrangement of most 8-bit processors. What

you learn here, moreover, can be readily extended to larger, more powerful,

processors. Despite their sophistication, modern 64-bit machines operate to

the same basic principles as the 8-bit machines from which they have evolved.

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________________________________________________________________________________________

YOUR AIMS ________________________________________________________________________________________

On completing the lesson you should be able to:

• state what is meant by the terms OPCODE and OPERAND

• appreciate that instructions can consist of one, two or three bytes

• explain the role of the PC, IR, ID, ACCUMULATOR, MAR and

GENERAL PURPOSE registers, and FLAGS

• sketch a block diagram of the internal architecture of a typical CPU

• sketch and explain what is meant by the opcode FETCH, READ and

WRITE cycles of a CPU

• explain the terms STATE, MACHINE CYCLE, INSTRUCTION

CYCLE.

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________________________________________________________________________________________

INSTRUCTION FORMAT ________________________________________________________________________________________

An instruction consists of a number of bytes of information stored in

consecutive memory locations. As you may remember, the symbols ‘0’ and

‘1’ are called bits (from BInary digiT). Eight ‘bits’ are referred to as a byte.

An instruction may be one, two, three or, exceptionally, four

bytes long. The first byte is always the operations code, shortened to

‘opcode’.

The opcode defines what operation the instruction will perform – for example,

ADD, SUBTRACT, AND, OR, COMPARE, and so on. The remaining part of

the instruction is called the operand, and represents either data (one byte) or

an address (two bytes). FIGURE 1 shows the format of one, two and three

byte instructions.

e.g. ‘Halt’ e.g. ‘Compare FF’ e.g. ‘Jump to OB7A’

FIG. 1

(a) One byte

(b) Two bytes

Single byte operand

Two byte operand

7 6 5 4 3 2 1 0 msb lsb

Opcode Opcode

Data

Opcode

Address (low byte)

Address (high byte)

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________________________________________________________________________________________

REGISTERS ________________________________________________________________________________________

A register is a line of bistable elements (usually 8 or 16 bits long) in which a

‘word’ can be stored. Once a word has been ‘loaded’ into a register it will

remain in this state until acted upon by some external event. Registers within

the CPU are used as temporary stores. Typically, eight bit registers are used to

store data or opcodes, and 16 bit registers used to store addresses. FIGURES

2(a) and 2(b) show 8 bit and 16 bit registers. It can be seen that the 16 bit

‘most significant byte’ (or ‘high byte’) and ‘least significant byte’ (or ‘low

byte’).

FIG. 2(a – b)

Instructions will permit various operations to be performed on certain CPU

registers. Some of these instructions are illustrated in FIGURE 2(c – h). For

example, a register can be ‘incremented’ or ‘decremented’. By this it is meant

that 1 is added to or subtracted from its contents. Or, it may be possible to

shift or rotate the register’s data, in one direction or another, as shown in

FIGURES 2(e) – (h).

lsb

Data bus

msb

Address bus

HIGH BYTE LOW BYTE

D7 D0 D7 D0D0 D7

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FIG. 2(c – h)

Finally, as shown in FIGURE 2(i), the CPU’s registers are interconnected by

means of internal busses so that data can be transferred between them. Note

that the 16 bit registers have access to both the address and data busses. The

significance of this will become apparent later in the lesson.

FIG.2(i)

D7 D0

Internal address bus

D7 D0D7 D0 D7 D0

Internal data bus

16 Bit register

8 Bit register

0 10 0 0 10 00 10 0 0 10 0

10 0 0 0 0 0 11 0 0 0 1 0 0 00 0 1 0 0 0 1 0

1 0 0 1 0 0 0 00 10 0 0 10 00 10 0 0 10 0

0 0 00 00 0 10 0 0 1 0 0 000 0 0 1 0 0 1 0

0 10 0 0 10 0

+1 -1

(f) Shift Left (g) Rotate right (h) Rotate left

Before

After

Instruction:

Before

After

Instruction:

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________________________________________________________________________________________

FETCHING AN INSTRUCTION ________________________________________________________________________________________

Let’s now examine how an instruction is fetched from external memory into

the CPU.

The instruction is stored, as part of the program, in consecutive memory

locations of RAM or ROM, and one byte is fetched from memory into the

CPU at a time. (Remember the data bus is only 8 bits wide!) The first byte to

be fetched is always the opcode, as this defines what the instruction will do,

and without it the CPU would be unable to process the subsequent bytes.

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FIG. 3

The left-hand half of FIGURE 3 (to the left of the bold black lines) represents

the CPU, and the right hand half the external memory (ROM or RAM). Let’s

examine the parts shown within the CPU:

(i) First of all, the INSTRUCTION REGISTER (IR) is an 8 bit register with

the task of storing opcodes as they are fetched from memory.

ADDRESS

D7 D0

A d d re

ss d

ec o d in

A15 A0

Address bus

Write

Data bus

Memory (ROM & RAM)

D7 D0

In cr

em en

t R

es et

Control Signals

Read

CPU

System clock

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(ii) The instruction register will pass the opcode to the INSTRUCTION

DECODER (ID). As the opcode is a coded instruction, it must be

decoded to generate the required control signals. An 8-bit opcode

can represent 256 possible states and it is the role of the instruction

decoder to produce these control states from the opcode.

(iii) Thirdly, the SYSTEM CLOCK is an essential feature of the CPU as it will

control the synchronization of all data transfers to ensure that the right

data arrives at the right place at the right time. A transition in the system

clock initiates changes in the internal state of the CPU and in its external

control signals (such as and ) to allow data to flow from

one location to another.

(iv) The PC (PROGRAM COUNTER) is a 16-bit register used to store the

address of the next instruction to be fetched. It keeps a record of where

we are in the program. By way of analogy, move your finger along the

text as you read this page. As you read each word, ‘step’ or in other

words ‘increment’ your finger onto the next word to be read: your finger

is acting as a ‘program counter ’! Similarly, as each instruction is

completed, the PC is incremented 1, 2 or 3 times (depending upon the

number of bytes in the instruction) so that it is pointing to the start of the

next instruction in the program. In fact, the PC is automatically

incremented every time it is read so that it is ready to access the memory

location holding the next byte of the program. An increment control

signal is shown connected to the PC. This signal is activated by a

transition in the system clock during some stage of the instruction cycle.

The PC is also shown with a RESET control. The RESET is activated,

either automatically or manually, when the system is first switched on in

order to put the contents of the PC to a known state (usually 0000H).

This is then used as the start address for the program.

WRITEREAD

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THE OPCODE FETCH

Now refer to FIGURE 4 which shows the system at a particular stage in a

program. The PC contains the address ‘1800’ (0001 1000 0000 0000) which

has just been put onto the address bus. The address will be decoded by address

decoding logic so that memory location ‘1800’ is accessed. The contents of

this memory location (0011 1110 or 3E) will now be put on to the data bus.

Assuming that the machine is at the start of a fetch/execute cycle, then the byte

appearing on the data bus will be treated by the CPU as an opcode and will be

stored in the instruction register. The IR will pass the opcode to the instruction

decoder (ID) which will generate the required control signals for the execution

of this particular instruction.

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FIG. 4

The complete opcode fetch has occupied 4 machine cycles. The number of

clock cycles required to complete a memory access operation is called a

MACHINE CYCLE. Thus, in our example, the opcode ‘fetch’ is MACHINE

CYCLE 1, consisting of 4 clock cycles or T states.

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ADDRESS

D7 D0 A

d d re

ss d

ec o d in

A15 A0

Address bus

Write

Data bus

Memory (ROM & RAM)

0 System clock

D7 D0

In cr

em en

t R

es et

Read

CPU

0 0 0 17FD

1 1 0 0 0 0 0 0 0 0 0 0 0

1 1 1 1 1

0 0

1 1 1 1

0 0 0 0 1 1 1 1

1 1 10 0 0

0 1 1 1 1 1

0 0 0 0 0 0

17FE

17FF

1800

1801

1802

1803

1804

1805

0 10 01 1 1 1

Opcode

Data

Opcode

Address

3 Byte instruction

2 Byte instruction

1 Byte instruction

1800 H

C o n tr

o l

si g n a ls

________________________________________________________________________________________

THE COMPUTER REGISTER SET ________________________________________________________________________________________

After decoding the opcode some data manipulation will now need to be

performed in the CPU. In order to do this extra hardware mainly in the form

of extra registers and an ALU (arithmetic logic unit), as shown in FIGURE 5,

is needed. Note that all the registers are connected to a common internal data

bus.

FIG. 5

A.L.U.

8 BIT REGISTER

16 BIT REGISTER

DATA BUS

ADDRESS BUS

C F

T E M P

BAS

MAR

IDCONTROL SIGNALS

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The new hardware additions include:

(a) GENERAL PURPOSE REGISTERS

These are used as temporary data stores. There may be several general

purpose registers but, for the sake of clarity, only two (B and C) have been

shown in FIGURE 5. Had there been no such registers in the CPU then all

data would have to be stored in the external RAM – even if it represented only

an intermediate result of a calculation. This would involve much to-ing and

fro-ing between the CPU and its RAM which is, as you can begin to

appreciate, time-consuming. To speed things up, most CPUs have in-built

general purpose registers. The number of such registers a CPU will have is a

design compromise between space on the ‘chip’ (registers take up quite a bit of

chip area) and speed and flexibility of operation. Typically, in an 8-bit CPU,

the number varies from two to eight. Often, the general purpose registers can,

under program control, be used individually as 8-bit registers or as 16-bit

can be organised as three pairs. Register pairs are useful for storing addresses

and the HL (High/Low) pair is particularly useful in this respect.

FIG. 6

8 Bit

16 Bit

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(b) ACCUMULATOR (A)

The accumulator is a register of special significance because:

(i) in operations involving the ALU (ADD, SUBTRACT, AND, OR, etc.) it

is the source of one of the bytes of data to be processed

(ii) the results of ALU operations end up in the accumulator.

The role of the accumulator is depicted in FIGURE 7(a):

FIG. 7(a)

Imagine that we wish to add the contents of register B to those of A. The two

registers simultaneously put their contents (1) and (2) to the ALU input which

adds the bit pairs; the result appears on the output (3). The result is then fed

back into the accumulator where it over-writes the original contents. Thus the

original contents of A are lost! The accumulator ‘accumulates’ the result of

ALU operations.

B TEMP

Data bus

ALU

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THE TEMPORARY REGISTER AND TEMPORARY ACCUMULATOR

The temporary register was shown in FIGURE 5 previously and the detail

reproduced here in FIGURE 7(a). One may ask the question; what is the

purpose of the register?

The answer is that it is needed because the ALU requires a byte applied to each

of its inputs simultaneously. At the same time, the output from the ALU will

appear on the data bus. If we study FIGURE 7(a) we see that there will be a

bus conflict between the B registar and the ALU output. In FIGURE 7(a) the

contents of B are first transferred to TEMP so that the output of the ALU has

exclusive use of the data bus. The contents of the ALU are then written back

into the accumulator.

How then, the questions arises, can the accumulator simultaneously act as both

input and output?

The answer is, of course, that it cannot, and if its going to hold the output of

the ALU, then its contents must be transferred to a TEMPORARY

ACCUMULATOR (TA), as shown in FIGURE 7(b). (To simplify the story so

far the TA was omitted from FIGURE 5.)

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FIG. 7(b)

The temporary accumulator cannot be accessed and is an integral part of the

accumulator/ALU.

A three byte instruction can consist of an opcode followed by an address. This

address points to the memory location which holds the data upon which the

operation must be performed. In order to fetch data, the two bytes following

the opcode must be formed into an address and then put onto the address bus.

The AS is the register in which such an address is formed.

(d) MEMORY ADDRESS REGISTER (MAR)

The MAR holds the address of the memory location currently being accessed.

Sixteen bit address registers (or register pairs) will pass their contents to the

MAR when the address they hold is to be accessed. The MAR is necessary so

that the contents of registers such as the PC or AS can be altered without

affecting the current address.

B F ATEMP

Data bus

ALU

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Consider an example to show the role of the registers mentioned so far.

The instruction to be fetched and executed, is ‘32 00 1F’ in HEX. In words,

this means ‘store the contents of the accumulator in memory address location

1F00’ (again, notice the address is in reverse order!). Assume that 87H resides

in the accumulator: then, after the execution of the instruction, 87H will be

stored at memory location 1F00. The instruction commences at address 1803.

The sequence of events will be as follows:

1. The source address of the opcode (1803) is put onto the address bus, via

the MAR, by the PC (FIGURE 8(a)). The PC is then incremented. The

opcode ‘32’ is read from memory and decoded. In decoding the opcode,

the CPU will now expect a further two bytes to follow and that these two

bytes should be formed into an address in the AS.

FIG. 8(a)

1804

1800

Memory

A.L.U.

8 BIT REGISTER

16 BIT REGISTER

DATA BUS

ADDRESS BUS

C F

T E M P

BAS

MAR

ICONTROL SIGNALS

1801 1802 1803

1805

18 03 87

32 00 1FREAD

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2. The contents of the PC are again put onto the address bus to fetch the low

byte (00) of the address contained in the instruction. This is stored in the

lower half of the AS, as shown in FIGURE 8(b).

FIG. 8(b)

3. The high byte of the address is then fetched and stored in the upper half of

the AS (FIGURE 8(c)).

1804

1800

Memory

A.L.U.

8 BIT REGISTER

16 BIT REGISTER

DATA BUS

ADDRESS BUS

C F

T E M P

BAS

MAR

1801 1802 1803

1805

18 03 87

32 00 1FREAD

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FIG. 8(c)

4. The contents of the AS are now put onto the address bus (via the MAR) to

access memory location ‘1F00’ and the accumulator contents (87) written

into it (FIGURE 8(d)).

FIG. 8(d)

IF00

A.L.U.

8 BIT REGISTER

16 BIT REGISTER

DATA BUS

ADDRESS BUS

C F

T E M P

BAS

MAR

WRITE

1800 Memory

1801 1802 1803 1804 1805

32 00 1F

87061800 871F

1804

1800

Memory

A.L.U.

8 BIT REGISTER

16 BIT REGISTER

DATA BUS

ADDRESS BUS

C F

T E M P

BAS

MAR

1801 1802 1803

1805

18 03 87

32 00 1FREAD

1F 00

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Note that the PC will now be pointing to the address of the start of the next

instruction (i.e. 1806).

FLAG REGISTER (F)

The flag register is a collection of 8 bistable elements or ‘pigeon-holes’, each

of which can be accessed independently. Each bistable in the flag register is

able to record an aspect of the operational state (or the STATUS) of the CPU.

For example, suppose that two numbers are subtracted to give a zero result.

Then the ZERO FLAG is set to 1 to record this.

The exact structure of the flag register depends upon the type of

microprocessor. A simple, hypothetical set of three flags is illustrated in

FIGURE 9. Bits 1 to 5 are not designated.

FIG. 9

CF is the CARRY FLAG. In the case of addition, it is set to 1 if a carry

is generated from the m.s.b.

Z is the ZERO FLAG, already described.

S is the SIGN FLAG. It is set if a negative result is given when using

signed arithmetic (i.e. when the m.s.b. is 1)

6 5 4 3 2 1 LSB

0 MSB

S Z CF S = Sign

Z = Zero

C = Carry

X = Not used

X X XXX

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The state of the flag can be used to initiate a certain sequence of events

illustrated in the flow chart (FIGURE 10) below.

FIG. 10

THE TIMING DIAGRAM FOR THE FETCH AND EXECUTE CYCLE

Timing diagrams for various operations performed in a microprocessor are not

intended to be covered in this unit. However, for the sake of completeness we

show here a schematic of how the clock cycles (designated T1, T2, T3, etc.)

align with the machine cycles (MCs) and actions comprising the fetch execute

cycle. FIGURE 11 shows the timing diagram and the significance of the

circled numbers is as follows:

(1) the opcode is read into the instruction register.

(2) the program counter is then incremented to fetch the next byte (‘LL’)

which will form the lower half of the address.

Subtract B from A

Result = 0 ?

Continue with main program

Perform task ' X'

Yes

CPU 'looks' to see if zero flag is set.

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(3) the next increment of the PC will cause the upper half of the address

(‘HH’) to be fetched. LL and HH are stored in the MAR to form the

address HHLL.

(4) at the commencement of MC4 this address is put onto the address bus.

The entire process takes (4 + 3 + 3 + 3) = 13 clock states, and 4 machine

cycles (one opcode fetch, two read and one write cycle).

FIG. 11

T1 T2 T3 T4 T1 T2 T3 T1 T2 T3 T1 T2 T3

MC 1 (Opcode fetch)

MC 2 (Fetch LL)

MC 4 (Execute)

MC 3 (Fetch HH)

Clock

Address bus

Data bus

Read

Write

Opcode address 'HH LL'

'HH''LL'

IN IN IN OUT

Instruction cycle

1 2 3 4 5

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________________________________________________________________________________________

SELF-ASSESSMENT QUESTIONS ________________________________________________________________________________________

1. Describe briefly the difference between an opcode and an operand, as

explained in the lesson, and give an example of each.

2. Describe what is meant by ‘bus conflict’.

3. State the function of the temporary register and temporary accumulator

during ALU operations.

4. Describe briefly the purpose of the following:

• instruction register

• instruction decoder

• program counter

• address store

• memory address register

• flag register.

5. Explain how the flag register can indicate the status of ALU operations.

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________________________________________________________________________________________

NOTES ________________________________________________________________________________________

...................................................................................................................................................

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________________________________________________________________________________________

ANSWERS TO SELF-ASSESSMENT QUESTIONS ________________________________________________________________________________________

1. The opcode defines what operation an instruction will perform.

Example – ADD, SUBTRACT, AND, OR, etc.

The operand is the part of the instruction that consists of either data or an

address.

Example – data FA, address 0B7A.

2. Bus conflict occurs when two or more items of internal CPU hardware

attempt to write to a data bus.

3. The purpose of the temporary register and temporary accumulator is to

avoid the bus conflict that would arise during ALU operations involving

instructions of two bytes or more.

4. • Instruction register is used to store the opcodes of instructions

fetched from memory.

• Instruction decoder is used to generate control signals from the

opcode passed to it from the instruction register.

• Program counter records which point in the program the computer is

at by storing the next instruction to be fetched from memory.

• Address store is the register into which a 2 byte memory address is

moved following an opcode with operand address being placed into

the instruction register.

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• Memory address register is the register into which the address placed

in the AS is moved and represents the location of the address

currently being accessed. It is necessary to store the current address

whilst the program couner and address store may be changed without

affecting the current address.

• Flag register is used to indicate the status of important operations of

the CPU.

5. The flag register can indicate whether an operation of the ALU has

produced a positive or negative result, whether the result is zero and when

a carry has been generated.

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________________________________________________________________________________________

SUMMARY ________________________________________________________________________________________

An INSTRUCTION consists of one or more bytes of data which are fetched

sequentially from memory.

The first byte to be fetched is the OPCODE. This is fetched during the

OPCODE FETCH cycle.

In any subsequent READ CYCLES the OPERAND of the instruction is

fetched from memory.

The operand, as defined in this lesson, may be the data upon which the

instruction will be performed or an address at which the data is, or will be,

located.

The PROGRAM COUNTER (PC) is a 16-bit register which holds the address

of the next instruction to be fetched. The PC is automatically incremented

each time it is used.

The ADDRESS STORE is a 16 bit register used to form an address from data

brought from memory.

The MEMORY ADDRESS REGISTER is a 16-bit register used to hold the

address of data to be accessed in memory.

The INSTRUCTION REGISTER (IR) is an 8-bit register used to hold the

current opcode. The IR passes the opcode to the INSTRUCTION DECODER

which generates the required control signals.

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A microprocessor also contains several general purpose data registers. The

most important of these is the ACCUMULATOR which is both a source and

destination of ALU operations.

The FLAG register is used to record the status of the microprocessor.

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setdistillerparams << /HWResolution [2400 2400] /PageSize [612.000 792.000] >> setpagedevice