Low power Project 2,3 and Nanotechnology Hw 3, project2

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EE-451: Introduction to Nanotechnology, Fall 2018, Project 2: Design and Simulation of Quantum-dot Cellular Automata (QCA) Nanoelectronic Circuits

In this project, we are going to use QCADesigner (version: 2.0.2) to design and simulate some QCA nanoelecronic circuits. QCADesigner is free QCA circuit layout design and simulation software developed by the Walus Group at the University of British Columbia (CA). You may download QCADesigner version 2.0.2 with the required GTK+ Runtime Environment from our Canvas website under folder “Files\Software\QCADesigner\QCADesigner-2.0.2-setup-gtk.zip”. Please download it to your local hard drive, unzip it, and run the installation process to install it into your computer. Please note that the version 2.0.3 is relatively new and there may be some bugs in it. You may not be able to get correct simulation results using version 2.0.3. So please use more stable version 2.0.2 instead of 2.0.3 for our project. Note: To ensure correct outputs, please set “Simulation engine” as "Bistable Approximation", and change its "Number of Samples" from “12800” (default value) to “128000”. 1. Design and simulation of a 3-input majority gate. A majority gate implements following function: M(A,B,C)=AꞏB+BꞏC+AꞏC. 1). Design a 3-input majority gate with 3 symmetrical inputs, as shown in Figure 1. All the QCA cells are in clock zone 0. Use exhaustive simulation to simulate the majority gate, submit the screen shot of the waveforms of inputs (A, B, C) and output (Out). Fill Table 1 to compare your simulated responses with expected outputs. Does the majority gate show correct function?

Figure 1. An 3-input majority gate with symmetrical inputs

Table 1. Simulated patterns of 3-input QCA majority gate with symmetrical inputs Patterns (ABC) Expected output (Out) Simulated output (Out) Output correct? (Yes/ No)

000 001 010 011 100 101 110 111

2). Now let’s simulate a 3-input QCA majority gate with asymmetrical inputs (Figure 2). All the QCA cells are in clock zone 0. Use exhaustive simulation to simulate the majority gate, show the screen shot of the inputs (A, B, C) and output (Out) waveforms. Fill Table 2 to compare your simulated responses with expected outputs. Does the majority gate show correct function now? What is the relationship between output (Out) and its nearest input (A)? Can you explain the reason for this?

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Figure 2. A 3-input QCA majority gate with asymmetrical inputs

Table 2. Simulated patterns of 3-input QCA majority gate with asymmetrical inputs Patterns (ABC) Expected output (Out) Simulated output (Out) Output correct? (Yes/ No)

000 001 010 011 100 101 110 111

3). Now let’s simulate the same 3-input QCA majority gate with asymmetrical inputs, but with different clocks to synchronize the gates (Figure 3). As shown in Figure 3, three input lines (A, B and C) are clocked as zone 0, the majority gate is clocked as zone 1, and output line (Out) is clocked as zone 2. Use exhaustive simulation to simulate the majority gate, show the screen shot of the inputs (A, B, C) and output (Out) waveforms. Fill Table 3 to compare your simulated responses with expected outputs. In which clock zone does the output (Out) get the valid values? Does the majority gate show correct function now? What conclusion can you draw from this experiment?

Figure 3. A 3-input QCA majority gate with asymmetrical inputs but synchronized with clocks

Table 3. Simulated patterns of 3-input QCA majority gate with asymmetrical inputs Patterns (ABC) Expected output (Out) Simulated output (Out) Output correct? (Yes/ No)

000 001 010 011 100 101 110 111

2. Design a 2-input AND gate with 2 asymmetrical inputs, as shown in Figure 4. Three input lines are clocked as zone 0, the AND gate is clocked as zone 1, and output line (Out) is clocked as zone 2. Use exhaustive simulation to simulate the 2-input AND gate, submit the screen shot of the waveforms of inputs

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(A, B) and output (Out). Fill Table 4 to compare your simulated responses with expected outputs. Does the AND gate show correct function?

Figure 4. A 2-input AND gate synchronized with clocks

Table 4. Simulated patterns of 2-input AND gate synchronized with clocks Patterns (AB) Expected output (Out) Simulated output (Out) Output correct? (Yes/ No)

00 01 10 11

3. For the above 2-input AND gate in Question 2, change it into a 2-input OR gate by changing the fixed polarity of bottom QCA cell from “-1” to “+1” . Use exhaustive simulation to simulate the 2-input OR gate, submit the screen shot of the waveforms of inputs (A, B) and output (Out). Fill Table 5 to compare your simulated responses with expected outputs. Does the OR gate show correct function?

Table 5. Simulated patterns of 2-input OR gate synchronized with clocks Patterns (AB) Expected output (Out) Simulated output (Out) Output correct? (Yes/ No)

00 01 10 11

4. Design a vertical inverter chain as shown in Figure 5, and couple out the signals you want from the chain. It has input signal “a”, and multiple outputs as shown in the figure. A vertical wire with 45º cells can be treated as an inverter chain, and you can couple out signal (a) or its inversion (a’) easily by placing a regular QCA cell between two neighboring 45º cells.

Figure 5. A vertical inverter chain and its coupled outputs

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Simulate the above circuit, and list the screen shots of all the signals (input a, outputs a1, a1_bar, a2, a2_bar, a3, a3_bar, a4, a4_bar, b). Based on the waveforms, please list the relationship between each output signal and input signal a. (For example, a1=a, a1_bar=a1’=a’, etc.) 5. Design and simulation of XNOR gate. Design a QCA circuit to implement function:

BABABXNORAZ  )( Set the appropriate clock zones for all the QCA cells to synchronize the signals in the circuit. Show the screenshot of the layout design of your 2-input XNOR gate. Use exhaustive simulation to simulate the 2- input XNOR gate, show the screen shot of the inputs (A, B) and output (Out) waveforms. Fill Table 6 to compare your simulated responses with expected outputs. Does the XNOR gate function correctly?

Table 6. Simulated patterns of XNOR gate synchronized with clocks Patterns (AB) Expected output (Out) Simulated output (Out) Output correct? (Yes/ No)

00 01 10 11

6. Design and simulation of a one-bit QCA full adder. A one-bit full adder should implement Sum and Cout functions as below:

inininin CBACBACBACBASum  (1)

ininout CACBBAC  (2)

There are many possible QCA implementations of one-bit full adder. Among them, one example design is shown as below:

)],,(),,,(),,,([ ininin CBAMCBAMCBAMMSum  (3)

),,( inout CBAMC  (4)

Can you use Boolean logic to verify above implementation does give the function of a one-bit full adder? That is, derive Equation (1) from Equation (3), and derive Equation (2) from Equation (4), separately. Now try to use QCADesigner to design the layout of one-bit full adder based on Equation (3) and (4). Capture the screen shot of your QCA layout. Further, use your 7-bit student ID (first bit as “0”) to derive a pattern sequence to simulate the function of your QCA full adder. Convert each decimal bit of your student ID into a binary pattern (ABC). Since 3-bit pattern only can represent decimal number 0~7, you can replace decimal number “8” in your student ID with decimal number “0”, and replace decimal number “9” in your ID with decimal number “1”. For example, if your student ID is: 0823956, then change it into: 0023156. Thus your 7-bit pattern sequence is: ABCin=0→0→2→3→1→5→6. That is: ABCin=000→000→010→011→001→101→110. Use your pattern sequence to simulate your QCA full adder, capture the screen shots of your simulated waveforms, and fill in Table 7. Does your designed QCA full adder function correctly for all your 7 patterns?

Table 7. Simulated patterns of one-bit QCA full adder Patterns (ABCin)

Expected Sum

Simulated Sum

Expected Cout Simulated Cout Correct? (Yes or No)

Due on 04/16/2018, Monday in class.