LTSPICE simulation

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Midterm 1 10/13/2020

1) A 0.18µm CMOS process has the following transistor characteristics: NMOS tox = 4.1x10-9 m, VTN0 = 0.35V, µn0 = 327 cm2/V-s PMOS tox = 4.1x10-9 m, VTP0 = -0.41V, µp0 = 128 cm2/V-s (a) Plot the IDS vs. VDS curves for NMOS (W=0.3µm, L=0.18µm), VGS=0, 0.9V, and 1.8V

PMOS (W=0.3µm, L=0.18µm), VGS=0, -0.9V, and -1.8V

(b) When you use SPICE simulation to get the same curves for the NMOS transistor, you find out that the simulated values for the same transistor sizes, voltages, etc. are

lower in saturation than your hand calculations predicted.

State two (2) non-ideal effects which may account for this lower current:

i)

ii)

1.8V0.9V0.45V 01.35V-1.8V -0.9V -0.45V-01.35V VDS

IDS

BARMAK MANSoo#CAN

11/1/20

500nA# 483mA

. .

. - - - - -

- - - - - - -

;--# =

- -- -

- - - - - - - a

7414mA . ' I

y.it- , I' f- , y Nmospros 21 qua , i µVos=&9V us -0 moves .

- of in a y'

"÷.÷÷÷.÷÷÷"÷÷÷÷ ""

""

Thos -

vase - I .8V

:

VELOCITY SATURATION

MOBILITY DEGRADATION

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Date:

Intentionally left blank for your work:

BARMAK MANSOORIAN

go

① CALCULATE An Bp D= oh ↳¥

,

Ana 32744.see * 8.4×10-7%42 *&p?Yg£-m ② emanate cconmf.mg?,xtsEg..saIE.mFEInNM

" ' Pms) =4=46×0

-"

Fae #

a 8.4×0-7 Fkn' Bp = 128¥.see * 8.4×10-7%4* 06.71¥

4.1×10 on Bpa 1.8×10

- "F- V.SEC

③ CALCULATE MAI CURRENT Of Nmos TRANSISTOR AS SANITY CHECK ..

IDNMOS Max = Ben * I ( 1.EV- 0.3 '' I

4

= 4.6×10 -F- * 1.OTVZ *SEC

= 4.8×10-4 F¥c= 4-8×0

-" A = 480mA (SEEMS A

Boot RCIGHT)

④ CALCULATE MAX CURRENT OF Pmo, TRANSISTOR

AS CHECK .

I

ID.pro, Max = Bp * I (- 1.or- C

-g.a)2)

= 1.8×154%7*0.966 V2 = 173µA (SEEMS ABOUT

RIGHT)

⑤ NOW CALCULATE VDSAT's (TRANS,now points BETWEEN

SATURATION AND UNEAR)

Vas = @ → Vos 20.35 V ,

so TRANS'S 'M OFF

pmo, veg=p → us,> I - ol.eu/

,

so TRANS'S TOR OFF

NMOS go TRANSISTOR ON

Vos .io/.sVlVos3I-ol.av/ , Vos = 4.SV

Vcs > 0.35N, So TRANSISTOR

ON

=

-

0.su- C -0.9)

" in:÷%:? " \ "in:* -ourVGS> 1. JV frost>I -O.eu/ , so TRANSISTOR ONVGS> 1. EV Vos >4. ITV , So TRANSISTOR ON

VDSAT II.8V- C-0.9) VDSAt =/

.8V- 0.35V

= 1.YTV Vpsat = - 1.39W

VDSAT

⑥ CALCULATE SAT CURRENTS AND ONE URRENT

VALUE BEFORE EACH VDSAT . Aco 6 w/¢ , TH'S

WILL GIVE You 3 POINTS FOR EACEH VGS

PMOS Vos -01 ⇒ TRANSISTOR OFF IDs-01 For

NMog veg reef ⇒ TRANSISTOR OFF IDS -_0 FOR ALL VDS

ALL VDS - -

Ves . -0.9V

Vcs = 0.9V for ↳s<Vps L

-0.491 '''E ⑤ ABOVE) For Vps> VDSAT>0.554£

⑤ ABOVE) ✓ Ips -- IDsat = Bp t f

- 0.49 ) "

2 21.6 Ips -- IDsat = Ph t ( 0.9 - 0.35¥ -y F -¢.gg/IDSAT--mA=4.6xio-4#.c*Iz(0.55HIDSAT--69mA = 1.8×10 ⇒*{( FOR VDSLVDSAT PICK A Vbs VALVE .

I'LL PICK VDS? 01222 FOR VDSLVDSAT PICK A Vbs VALVE . I'LL

PICK VDS? 01225g

IDs= IDsan = An [ (0.910.35k KYIV) (0.22N)) IDs= IDsan = Bp [ ( -0.49 -(-0.225-9)/-0.2254)

= 1.8×10 '

* 5.96×107! 10nA

= 4.6×10 '

* 0.098V -

= 45mA

IDSLCN (VDSAT-50.225K)= 10mA IDSLCN (VDSAT-_0.225D= 45mA -

- ¥Vcs =Vcs =L-OV for ✓Ds Lrp, L-1.3N (Sf:÷÷E ⑤ ABOVE)FOR Vps> VDSAT> 1.4N (S¥i÷÷E ⑤ ABOVE) IDs -- IDsat = Bp Iz f - 1.39 V)'Ips -- IDsat = Ph t (l-YTV)" -4uF¥ * { f-1.3g y' IDSAT-- 173mA= 4.6×10-4 * {4954' IDSAT-- 483mA = i.8×10 ,VDS VALVE . I'LL PICK VDS? 019 V FOR VDS> VDSAT PICK A Vbs VALVE . I'LL PICK VDS? 019 VFOR VDSLVDSAT PICK A ¢, I = Ipsc,n= puff - 1.39 V -f 4)(④ 9 V))IDs= IDsan = An [ ( 1.4N - -2410.9 V)) -Y F= 1.8×10-* 0.846 V2 = 4.6×10

-

* 0.9J v. SEE V. SEC

Ipa,w (VDs= 0.94=152MA IDSUN (VDS -_ 0.9V) = 419mA

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2) Calculate the LOWEST CLOCK frequency for which this latch would retain a LOGIC ONE. Assume the following:

a) VTN = 0.35 Volt (neglect body effect for this problem) b) Total Leakage current on STORAGE NODE = 100 x 10-15 Amps (assume all leakage

current is to ground).

c) Minimum Valid Voltage for LOGIC ONE = 1.3 Volts d) Maximum Voltage for LOGIC ONE = 1.8 Volts e) Gate Capacitance (for 0.18um long device) = 1.67 fF/µm f) Diffusion Capacitance = 1.12 fF/µm

LOWEST CLOCK Frequency = _____________________

CLOCK

INPUT M1

W/L = 2µm/0.18µm

M2 W/L =

1µm/0.18µm

M3 W/L =

2µm/0.18µm

STORAGE NODE 1.8 V

BARMAK MANSooriAN

11/1/20

92Hz

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Intentionally left blank for your work:

TSARMAK MANSOORcan

114/50

① STEP I CALCULATE THE HIGHEST VOLTAGE THAT CAN END UP ON -

STORAGE NODE → clock = C.gr/NpUT--l.8V l- N

"THE@STORAGE NODE = 1.gu- of.zTv= 1.45W I-85£ t.TV

② CALCULATE CAPACITANCE @ STORAGE NODE

STORAGE NODE

§ STORKE IN#Ac f ICoate Paros

NODE and =

1.4N -1¥¥hk__hq? 'Footy:&. § Jeane f- coated''g CAFF = 1.1214%4*44--2.24

FF ( Mca?'EEYIfIee)

Coatepmos = 1.67#* 2mm = 3. Seeff ( M

' cfFIEI-awc.es) mm

CGATENMOS = 1.67#m* gun = 1.67ft (M2eap?ATE)

CTOTAC @ STORAGE NODE =

7-25tf

③ CALCULATE RATE OF CHANGE OF VOLTAGE

ON STORACE NODE:

re Q=CV ⇒= I-- Cdf Iata'7a -1725ft

= =cook

I

7-25x co -'5F

= 13.8 %EC

⑦ How MANY VOLTS MOST STORAGE NODE Discharge TO

CAUSE " BAD " ONE ?

MAX VOLTAGE= 1.95 V

MIN " l " vaeueec.gr } Ar=

150mV

⑤ DV F- II. 13.0¥

150mV

At-_BI -

13.TV/sec=l3.8YstcDt--1.1×10-2 SEC ⑥ LOWEST CLOCK

FREQUENCY

Fan =c-= 92Az

At

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3) Implement the following Logic Function in Static CMOS using the minimum number of transistors:

Y = (A + B) & (C + D)

BARMAK MANSOOR CAN

11/1/20

A -01474 B-off Daddy ¥7OUT -

C -14 ¥ ⇐ (CTD) I ← 4 -

A -14%4 ⇐Cate ) ±

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Intentionally left blank for your work:

TSARMAK MANSooRiAN

11/1/20

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4) Draw a process cross section from A to A’ as marked in the following layout (identify the layers in your drawing – i.e. p-diffusion, n-diffusion, poly, metal1, contact, etc.:

BARMAK MANSONAN

offs

METAL' METALL

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