VLSI

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Midterm 1 10/13/2020

1) A 0.18µm CMOS process has the following transistor characteristics: NMOS tox = 4.1x10-9 m, VTN0 = 0.35V, µn0 = 327 cm2/V-s PMOS tox = 4.1x10-9 m, VTP0 = -0.41V, µp0 = 128 cm2/V-s (a) Plot the IDS vs. VDS curves for NMOS (W=0.3µm, L=0.18µm), VGS=0, 0.9V, and 1.8V

PMOS (W=0.3µm, L=0.18µm), VGS=0, -0.9V, and -1.8V

(b) When you use SPICE simulation to get the same curves for the NMOS transistor, you find out that the simulated values for the same transistor sizes, voltages, etc. are lower in saturation than your hand calculations predicted. State two (2) non-ideal effects which may account for this lower current: i) ii)

1.8V0.9V0.45V 01.35V-1.8V -0.9V -0.45V-01.35V VDS

IDS

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2) Calculate the LOWEST CLOCK frequency for which this latch would retain a LOGIC ONE. Assume the following:

a) VTN = 0.35 Volt (neglect body effect for this problem) b) Total Leakage current on STORAGE NODE = 100 x 10-15 Amps (assume all leakage

current is to ground). c) Minimum Valid Voltage for LOGIC ONE = 1.3 Volts d) Maximum Voltage for LOGIC ONE = 1.8 Volts e) Gate Capacitance (for 0.18um long device) = 1.67 fF/µm f) Diffusion Capacitance = 1.12 fF/µm

LOWEST CLOCK Frequency = _____________________

CLOCK

INPUT M1

W/L = 2µm/0.18µm

M2 W/L =

1µm/0.18µm

M3 W/L =

2µm/0.18µm

STORAGE NODE 1.8 V

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3) Implement the following Logic Function in Static CMOS using the minimum number of transistors: Y = (A + B) & (C + D)

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4) Draw a process cross section from A to A’ as marked in the following layout (identify the layers in your drawing – i.e. p-diffusion, n-diffusion, poly, metal1, contact, etc.: