Low power Project 1,2,3

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ELEG-548: Low Power VLSI Circuit Design, Spring 2018, Project #2:

Power Analysis of CMOS/Domino Full Adder

The purpose of this project is to analyze power consumption for different circuit structures using

PSPICE. In the following designs, the size of each NMOS transistor is W/L=3μm/2μm, the size of

each PMOS transistor is W/L=9μm/2μm. Power sources are: Vdd=5V, Gnd=0V. In PSPICE

Capture, you need to consider the connections of bulk terminal of each transistor. You already did

the schematic design for both CMOS and domino full adders in Project #1. This is a group project.

Please work with your partner in project #1, and submit a joint report with your partner. You can

reuse your designs in project #1 without redesigning them.

Part 1. Static CMOS implementation

Figure 1. Schematic of a CMOS full adder (28 transistors)

1). Based on your schematic design for CMOS full adder in Project #1, first you need to verify the

correct function of your circuit. We assume you already did this in Project #1 and got correct

output waveforms. However, if you didn’t get correct output waveform in Project #1, you must

debug your design to find out the mistakes and correct them.

2). Double check to ensure you put net alias of “Vdd” to all the Vdd nodes, and net alias of “Gnd”

to all the ground nodes. Also ensure you put net aliases “A, B, Ci, Co, Sum” (and “clk” for clock in

Domino circuit) to the corresponding nodes. Otherwise you may have node name inconsistency

errors in the following steps.

3). Once the circuit works properly, extract the netlist from your schematic design. Copy it to a text

file, and combine it with other auxiliary circuit to construct a .cir file in PSPICE AD for power

analysis. Delete all the voltage definition lines (lines starting with V_name for power rails and

primary inputs) from your netlist and redefine your power rails. Reapply the input pattern sequence

as:

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ABCi = 100, 010, 110, 001, 101, 011, 111, 000, plus patterns corresponding to the last 2 digits of

your student ID.

Denote the input patterns ABCi=”000, 001, 010, 011, 100, 101, 110, 111” as pattern #0, 1, 2, 3, 4, 5,

6, 7 separately. Use the last 2 digits of your student ID as input pattern sequence appending to the

above pattern sequence, each number in your student ID stands for the corresponding input pattern

number. The number “8” and “9” in your student ID corresponds to pattern #0. For example, if the

last two digits of your student ID are “79”, then it translates to input pattern sequence: “#7, #0”,

which is: ABCi=111, 000. Thus you should apply your input pattern sequence as

ABCi = 100, 010, 110, 001, 101, 011, 111, 000, 111, 000.

That is, you will have 10 input patterns sequence, and each pattern lasts for 20ns. Assume the input

rising/falling ramps (0-100%) as 0.1ns, and set the simulation time as 200ns. For the power

analysis auxiliary circuit components, you can set Cp=100pF, Rp=100kΩ. Assume you want to

directly read the average power for t=[0, 160ns], you can calculate your K value for the

current-controlled-current-source as

003125.0 10160

101005 9

12

  

 

 



T

CV K dd

Use the SPICE codes to simulate the power consumption. Print out the waveforms for A, B, Ci, Co

and Sum signals. Also print out and submit the spice file (.cir file) you used for simulation.

4). In a separate page, print out the output voltage waveform of V(Pavg) for the Pavg node on the

auxiliary capacitance Cp. In the V(Pavg) waveform, use cursor measurement to read the average

power consumption for time period t=[0, 160ns].

5). Based on the V(Pavg) waveform, use cursor measurement and calculation to find out the average

power dissipation during time periods T1=[0, 80ns] and T2=[0, 200ns] separately.

6). Find out the switching activities of the nodes for the given input patterns. Fill in Table 1 in

appendix. Explain why some pattern changes lead to significant power dissipation, while others do

not.

7). Now add load capacitance of 200fF, 400fF separately to Co and Sum nodes in your spice file.

That is,

first case: Cload_sum=Cload_co=200fF

second case: Cload_sum=Cload_co=400fF

Apply the same pattern as the case when Cload_sum=Cload_co=0fF in step 3, find out the power

curve (the voltage waveform of Pavg node) and read the average power consumption for time

period t=[0, 160ns]. Based on these data and the date for Cload_sum=Cload_co=0fF in step 3, plot

a curve of average power Pavg versus Cload capacitance for Cload=0fF, 200fF and 400fF.

According to your result, if the load capacitance increases, is the power consumption increased or

decreased? Explain the reason.

Part 2. Domino circuit implementation

Please repeat all the steps 1~6 of Part1 (but skipping step 7 for load capacitance) using domino

circuit structure, as shown in Figure 2.

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Figure 2. Full-adder design using Domino circuit

Part 3. Comparison of the power dissipation for two circuit structures

Based on the above analysis, for the same transistor sizing and same input patterns, which circuit

structure consumes more power? Why? Please explain clearly.

In your project report, make sure you answer all the above questions. Each question accounts for

certain points. You also need to have a brief explanation about the whole project.

Due day: 03/26/2018 Monday in class.

Note: In this project, you are asked to extract the netlist from Schematic design. You do NOT need

to design the layout for the circuits. However, some students expressed their interests to practice

the layout design skills. Thus if you wish to design the layout and extract netlists from the layout

instead of the schematic, that is even better because the layout contains all the parasitic effects and

it can accurately reflect the real power consumption of your circuit. If you choose to do so, you

may get a maximum bonus of 10’. If you choose to design layout in Mentor Graphics IC station

using AMI05 technology (λ=0.3μm), you can set the size of each NMOS transistor is W/L=10λ/7λ,

the size of each PMOS transistor is W/L=30λ/7λ. If you choose to go with the layout option, you

may either do it independently or as a group of 2 students (each student finishes part 1 and part 2

individually, but both will complete part 3 and write the report together). I leave it as your choice.

However, please be aware that layout design is very time-consuming. If you are not familiar with

layout design, you are NOT encouraged to do so.

Appendix: Table 1. Switching activities of CMOS full adder (example only, please input your own

patterns) Pattern A B Ci Co Co

Switch?

Sum Sum Switch?

Total switches (Sum and Co)

Expected Energy Consumption (zero, small or

Simulated energy consumption (zero, small or

0 0 1 0 0 1

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large) large)

1 1 1 1 1 Yes 1 No 1 small small

2

3

4

5

6

7

8

9

10

Table 2. Switching activities of Domino full adder (example only, please input your own patterns)

(clk: clock input) Pattern A B Ci Co Co

Switch?

Sum Sum Switch?

Total switches (Sum and Co)

Expected Energy Consumption (zero, small or large)

Simulated energy consumption (zero, small or large)

0 (clk=0)

0 1 0 0 1

0(clk=1) 0 1 0 0 No 1 No 0 zero zero

1(clk=0) 1 1 1 0 No 1 No 0 zero zero

1(clk=1) 1 1 1 1 Yes 1 No 1 small zero

2(clk=0)

2(clk=1)

3(clk=0)

3(clk=1)

4(clk=0)

4(clk=1)

5(clk=0)

5(clk=1)

6(clk=0)

6(clk=1)

7(clk=0)

7(clk=1)

8(clk=0)

8(clk=1)

9(clk=0)

9(clk=1)

10(clk=0)

10(clk=1)