Low power Hw 2

1

ELEG-548: Low Power VLSI Circuit Design, Spring 2018, Homework #2. 1. (20’) A CMOS inverter is shown in Figure 1. Assume for every clock cycle Tclk=100ns, one test pattern is applied at input. For time period t=0~2800ns, the output waveform is shown in the figure. Vdd=5V, threshold voltage of NMOS/PMOS transistor: Vtn=-Vtp=0.8V, load capacitance CL=1.2pF. 1). Find the average switching activity Asw , 0→1 switching probability α0→1, and 1→0 switching probability α1→0 of output signal Vout during time period t=0~2800ns. 2). If only transition power is considered, during time period t=0~2800ns, how much energy is drawn from voltage source Vdd? How much total thermal energy (heat) is generated? 3). Find the average transition power Ptran_avg of output node (out) during time period t=0~2800ns. 4). Given input rising/falling time: tr=tf=0.1ns, maximum short circuit current at input rising/falling transition: Iscmaxr=Iscmaxf=0.2µA. Calculate the average short circuit power Psc_avg of the CMOS inverter during time period t=0~2800ns. 5). If load capacitance CL is increased to 10pF, will the average transition power Ptran_avg at output node be increased or decreased? Why? Will the average short-circuit power Psc_avg of the CMOS inverter be increased or decreased? Why? Please use 2~3 sentences to briefly explain the reason for each case.

Figure 1. CMOS inverter

2. (15’) For short circuit power Psc of an inverter in Figure 2, if input Vin has a 1→0 switching,

Figure 2. Inverter with load capacitance CL

1). If the size (W/L ratio) of the transistors increases, will the short circuit power be increased or decreased? Why? Does this change the time period (tE-tB) or the peak value of short-circuit current, or both? If we want to reduce the lasting period (tE-tB) of the short-circuit current, what should we do? 2). If input Vin has a 1→0 switching, which transistor current (Idsp of PMOS or Idsn of NMOS) will be the bottle neck to decide the overall short-circuit current? If the load capacitance CL increases, will the short circuit current be increased or decreased? Why? Please draw a figure to explain it. 3). Assume 50 consecutive input patterns are applied to the inverter, and each pattern lasts for 20ns. During this time period T=1000ns, the inverter input makes 12 rising transitions and 12 falling transitions. Given Vdd=5V, Vtp=-0.7V, Vtn=0.8V, input rising time tr=0.1ns, input falling time tf=0.2ns, maximum short-circuit current for input rising transition is Iscmaxr=60nA, maximum short- circuit current for input falling transition is Iscmaxf=80nA. What is the total short-circuit energy Esc consumed during this time period? What is the average short circuit power Psc_avg during this time period T=1000ns? 3.(15’) Consider a VLSI chip with 400 million transistors. It consists of both static CMOS logic

2

gates and memory. Among them, there are 300 million logic gate transistors with average transistor width of 12λ/transistor, and 100 million memory transistors with average transistor width of 4λ/transistor. Assume that clock signal is routed on a metal layer with average width of 1.6µm and overall length of 40mm. The parasitic capacitance of metal layer for clock wire is 1fF/µm2. Assume Vdd=5V, feature size of fabrication process is 2λ=64nm, gate capacitance per transistor width Cg=2fF/mm. For static CMOS logic gates, average switching activity Asw=0.4, for memory arrays, the average switching activity Asw=0.2; for clock wire, average switching activity Asw=2. The VLSI chip works at frequency f=2.2GHz. Neglect other wire capacitance except the clock wire. What is the average transition power Ptran of the VLSI chip? (Hint: Total transition power = logic transition power + memory transition power + clock wire transition power) 4.(15’) The reverse-biased PN-junction leakage currents in a 2-input CMOS NAND gate is shown in Figure 3, and their values can be calculated from equation: where Is: reverse saturation current of PN-junction, V: applied voltage across PN-junction (negative if it’s reverse-biased), Vth: thermal voltage, Vth=kT/q, where k=1.38×10-23J/K (Boltzmann’s constant), q=1.6×10-19C (electron charge), T: temperature. Assume room temperature: T=300K, Vdd=5V, Gnd=0V. For static input pattern AB=10 (i.e. VA=5V, VB=0V), mark the “ON” or “OFF” state for each transistor, and mark the voltages at nodes “Out” and “M” in the figure. Assume for each PN-junction IS=6.2fA, find the reverse-biased PN-junction leakage currents Ireverse1, Ireverse2, Ireverse3, Ireverse4=? Mark the flowing paths of non-zero reverse-biased PN-junction leakage currents in the figure (i.e. where do they come from, where they flow to, as well as the flowing path).

Figure 3. Reverse-biased PN-junction leakage currents in a 2-input CMOS NAND gate

5.(15’)A CMOS 2-input AND gate is shown in Figure 4. If we wish to use PSPICE power simulation to simulate its average power consumption for time period T=400ns. During this time period, 4 input patterns were input to the AND gate, with each pattern lasting for 100ns. Assume Vdd=5V. 1). Draw the schematic for the PSPICE power simulation circuit. You need to clearly draw the AND gate and the auxiliary power measurement circuitry in transistor level, and the connection between them. Please do NOT use a block diagram to represent the original circuit. 2). Assume in power measurement circuitry, R=800kΩ, C=120pF, what value should the controlling coefficient (K) of the current controlled current source be set to? 3). After PSPICE power simulation, the voltage waveform across the capacitance C is shown in Figure 5. From figure 5, what is the average power consumption Pavg and total energy consumption E of the AND gate during time period T=400ns? What is the average power consumption Pavg and

 1/  thVVSreverse eII

3

total energy consumption E of the AND gate during time period t=0~280ns? Shade the area in Figure 5 which represents the energy consumption of the AND gate during time period t=0~280ns.

Figure 4. A CMOS 2-input AND gate

Figure 5. PSPICE power simulation curve

6.(20’) Consider a CMOS logic circuit (implemented using static CMOS technology) driving a 0.2pF load as shown in Figure 6. Also, the characteristics of the cell library are shown below. Input capacitance of a gate is the parasitic capacitance between each input and ground; output capacitance of a gate is the parasitic capacitance between each output and ground. Assume all inputs are uncorrelated and random, i.e., the probability for each input to be “1” (“1” probability) is: p(A)=p(B)=p(C)=p(D)= 0.5 1). Find the “1” probabilities for nodes E, F, G. 2). Calculate switching capacitances for nodes A, B, C, D, E, F, G. 3). Assume Vdd=5V, clock frequency (the frequency of applied patterns) fclk=1MHz. Calculate average switching power for the whole circuit. (Hint: total switching power of a circuit is the sum of the switching power of all the nodes.) Table 1. Characteristics of 0.8μm CMOS cell library

Gate type Area Output Capacitance(fF) Input Capacitance (fF) Average delay (ns) INV 2 80 48 0.22+1.00C0 NOR3 4 102 48 0.37+1.5C0 NAND2 3 136 48 0.27+1.5C0

Figure 6. A CMOS logic circuit

Due: 02/28/2018 (Wednesday) in class.