Low Power VLSI Circuit Design final

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ELEG-548: Low Power VLSI Circuit Design, Spring 2020, Final Exam

Name: ____________________________________ Student ID: ______________________

Note: Use very brief answer for each question. Your grade is decided by the accuracy instead of the

length of your answer.

1. (30’) A State Transition Graph (STG) for a sequential circuit is shown in Figure 1. We need to

assign the states for four states S1, S2, S3 and S4 with two state registers.

Figure 1. State transition graph (STG) of a sequential circuit

1). Assume all primary inputs patterns (AB=00, 01, 10, 11) are equally probable. Based on STG,

find out conditional transition probabilities for all the transitions, and mark them in the STG.

2). Assume the state probabilities of states are:

P(S1)=1/12, P(S2)=1/6, P(S3)=5/12, P(S4)=1/3.

Find the absolute transition probabilities Paij for all transitions between states Si and Sj (i≠j), and

mark them in the STG.

3). Based on the results, find the weights Wij for all the transitions between states Si and Sj (i≠j).

4). Based on the weighted STG, can you find out a low power state assignment for the above

sequential circuit with minimum power cost function (Fc) value? Please clearly show how you

achieve the low power state assignment step by step. Please show your state assignment matrix,

and clearly mark the state assignment for each state (S1=? S2=? S3=? S4=?).

5). For your low power state assignment, find out the power cost function value Fc=?

2. (25’) A 16-bit carry-select full adder circuit is shown in Figure 2. It takes two 16-bit inputs A, B:

A=A15A14…A0, B=B15B14…B0, and computes: SUM=A+B.

The carry-select full adder uses two 8-bit full adders to precompute the sum of higher eight bits of

inputs assuming the carry-out from the sum of lower eight bits to be “0” or “1” separately. The

actual carry-out from the lower eight bits will decide which higher 8-bit SUM to be passed to the

final output (SUM<8:15>).

(1). This circuit can be revised to implement type-2 logic shut-down technique to save power. The

A7, B7 bits can be used to construct predictor functions. Derive the “1”-predictor function g1 and

“0”-predictor function g2 for the carryout of lower 8-bit full adder. Whenever the carryout of lower

8-bit full adder can be predicted, one of the two higher 8-bit full adders can be shut down to save

power.

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(2). Re-plot the circuit separately to show how type-2 logic shut-down technique is implemented.

You need to show clearly how g1 and g2 are connected in the circuit. (Hint: You may need to add

LE (load_enable) for some registers.)

(3). Assume 1-probabilities p(A<i>)=0.25, p(B<i>)=0.82, (i=0~15) what is the probabilities when

the circuit can be in shut-down mode? Assume average power of each one-bit full adder as Padder,

the power of 8-bit full-adder block is 8Padder. If we only consider the power consumption of

full-adders, while ignoring power consumption of other gates/registers/Load_Enables, what would

be the approximate percentage power saving we can achieve by using type-2 logic shut-down

technique (just a rough estimation)?

Figure 2. 16-bit carry-select full adder circuit

3. (25’) Low Power Data Communication: An 8-bit data bus is driven by an 8-bit counter, as

shown in Figure 3.

1). If a regular binary counter is used, what is the average number of bit switches per clock cycle

on the 8-bit data bus? Derive the equation to find out the average number of bit switches per clock

cycle for N-bit binary counter. Show your proof of the equation step by step.

2). If a gray-code counter is used, what is the average number of bit switches per clock cycle on

the 8-bit data bus? What is the number of bit switches per clock cycle for N-bit gray code counter?

3). If bus-inversion encoding technique is used to reduce the power of data communication, sketch

how you are going to implement the bus-inversion encoding logic (circuit design) on the 8-bit data

bus. For what patterns will the data be inverted? What is the average number of bit switches per

clock cycle on the 8-bit data bus with bus-inversion encoding technique?

4). Based on above 3 choices, which option gives the lowest power consumption?

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Figure 3. Data communication: 8-bit counter driving an 8-bit data bus

4.(20’) A transmission gate based one-bit full adder circuit is shown in Figure 4.

1). Based on the circuit design, what are the logic functions implemented at P, S and Co? Derive its

logic expression, and use Boolean transformation to prove it does implement the correct function

of Sum and Carry-out for one-bit full adder as below.

2). For this circuit in Figure 4, how are you going to measure its power consumption using PSPICE

power simulation? Draw the complete circuit with auxiliary power measurement circuitry and

clearly show where you are going to insert dummy voltage sources.

Figure 4. A transmission gate based full adder

Due on 05/05/2020 (Tuesday) online in Canvas before 5pm.