Low power Project 1,2,3

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ELEG-548: Low Power VLSI Circuit Design, Spring 2018, Project #3:

Implementation of Type-2 Logic Shut-down Technique for Low Power

Note: This is an optional project. You do NOT have to do it, but it is a good opportunity for you to

earn bonus points to improve your final total grade. If you choose to do it, please submit your report

to me on or before 04/23/2018 (Monday) in class, and you can get up to 50 bonus points added to

your project #2 grade. You can do it either independently or with your team partners in your

previous projects. You can even do it as four students in a group. If you choose to do it, even if you

cannot complete the project by 04/23/2018, you can still submit your partial results/report to me,

and you will get partial bonus points based on the results you obtained. Our grading criteria are:

If you worked out the design of some key components (e.g. register with load-enable, full-adder,

etc.), define them as blocks and verified their correction functions: up to 15’;

If you worked out the complete design of comparator without logic shut-down and verified its

correct function: add additional 15’,

If you worked out the complete design of comparator with logic shut-down and verified its correct

function: add additional 15’,

If you find out the power consumption of both comparators with and without logic shut-down and

make correct comparison: add additional 5’.

In this project you will design an 8-bit pipelined comparator circuit, and then implement type-2

logic shut-down precomputation technique we introduced in class to save power. You will use

PSPICE power simulation method introduced in project #2 to analyze the power consumption of

both circuits to see how much power you can save by implementing logic shut-down technique.

Assume Vdd=5V, Gnd=0V, each pattern lasts for 5ns, and clock period for registers: Tclk=5ns.

Simulation time: t=0~85ns.

Magnitude comparator is very useful in many digital signal process applications. A comparator

compares the magnitude of two numbers A and B. That is, if A≥B, the comparator gives an output

of “1”; if A<B, it gives an output of “0”. Convince yourself that a magnitude comparator can be

implemented by full adder, as shown in Figure 1. If you use full adders to add A with B’s inversion

and Cin=1, then Cout=1 when A≥B, and Cout=0 when A<B. That is, Cout exactly gives you the correct

output of a magnitude comparator for numbers A and B. For the full adder, you can reuse the full

adder design in Project #2. You are encouraged to use PSPICE hierarchy design. That is, if you need

to frequently use a certain circuit (e.g. 1-bit full adder), you can first design the schematic of this

circuit, simulate it and make sure it works properly, and then define it as a block. In the higher

hierarchy level, you can directly use this block without re-design it. This saves you tremendous time

and effort when you design a complex circuit with repeating sub-circuits. A PSPICE hierarchy

design tutorial is attached with this project for your reference. This will significantly improve your

working efficiency in complex VLSI circuit design with repeating blocks. For fair comparison, use

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the same register design with load-enable (LE) input for both comparators with and without logic

shut-down technique.

Part 1. 8-bit pipelined comparator design without logic shut-down technique

1). Design the schematic of a CMOS 8-bit magnitude comparator, as shown in Figure 1. It

compares two 8-bit inputs A7~0 and B7~0. If A≥B, then Cout=1; If A<B, then Cout=0. Judging from

Cout value, we know which input (A or B) is larger.

Fig. 1. Block diagram of an 8-bit magnitude comparator using full adder

The actual implementation of the 8-bit magnitude comparator is shown in Figure 2. We know

negative number is generally implemented as 2’s complement in digital logic. Thus:

A-B=A+(-B)=A+(2’s complement of B)=A+(B’+1).

Thus the following circuit actually implement the function of (A+B’+Cin)=(A+B’+1)=A-B. If A≥B,

then Cout=1; If A<B, then Cout=0. This is exactly the comparator function we need. You can reuse

the CMOS full adder circuit you designed in Project #1. Just add an inverter to B, and repeat the

1-bit full adder cell with inverter for 8 times, then make series connection to get the comparator, as

shown in Figure 2. You are encouraged to use PSPICE hierarchy design. You can define the 1-bit

CMOS full adder you designed in Project#1 as a block, then directly call it and use it in your

comparator design without redesigning it. You can also design a CMOS inverter, verify its function,

then define it as an inverter block, and directly reuse it in the comparator design. This will greatly

simplify your comparator design and improves your design efficiency.

Figure 2. Implementation of 8-bit comparator using full adder cells

After that, you can add corresponding registers in your schematic to get the 8-bit pipelined

comparator, as shown in Figure 3. You can also first design a one-bit register, verify its function,

and then define it as a register block and reuse it in the following circuit.

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Figure 3. Design of an 8-bit pipelined magnitude comparator

This original 8-bit pipelined magnitude comparator will be used as a power reference for

comparison purpose. You should not add any low-power technique into this design. Print out the

screen shots of your PSPICE schematic and attach it with your report.

2). Apply random input patterns of A and B to the circuit to verify the correct function of the

comparator, and use PSPICE power simulation to find the average power dissipation Pavg_ref during

time period of these patterns. For fair comparison, you should use random patterns to simulate the

power consumption. For example, you can use a random pattern generator to generate these input

patterns. However, since the 8-bit comparator circuit in this project is not that large, the power

saving via logic shut-down technique may not be that significant. To make the power saving more

observable, we designed a group of 16 input pattern sequence, as listed in the Hint file. It allows the

comparator with logic shut-down technique to be in logic shut-down mode for more cases, so that

the power saving can be significant. Please use the 16 input pattern sequence listed in the Hint file

for power simulation. Extract the netlist and simulate the circuit in PSPICE A/D. Please attach

the .cir file you used for simulation, and print out the waveforms for the clock, inputs (A7~A0,

B7~B0) and outputs (Cout), as well as the power curve V(Pav) for power simulation. Verify your

final Cout output for each pattern and ensure that the final V(Cout) is in good agreement with the

expected values in the table. Please keep in mind that it’s a pipelined structure and you are expected

to see two clock cycles’ delay in your final output. That is, after your first pattern is applied in this

clock cycle, you will not see the correct output immediately. Instead, your first valid output for Cout

will show up in the next clock cycle. If the functions of the circuit are correct, calculate the average

power Pavg_ref of the reference comparator for time period t=0~85ns. For power simulation

auxiliary circuit, you need to decide the K value of the current-controlled current source:

K=CꞏVdd/T, where T=85ns.

Part 2. 8-bit pipelined comparator design with type-2 logic shut-down technique

In this part, re-design the 8-bit pipelined magnitude comparator using the type-2 logic shut-down

technique we discussed in the class. Note that type-2 logic shut-down method is the one with input

latches partitioned. You can reuse the schematic design from Part 1, just add the extra circuits for

logic shut-down implementation. Use the same clock period as Part 1. Repeat the steps in part 1 for

this version of design using the same set of test patterns (this ensures fair comparison between both

circuits). Find out average power consumption Pavg_shutdown for the 16 patterns you used in Part 1.

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Part 3. Power saving calculation for type-2 logic shut-down implementation

Compare the average power you measured in Part 1 and Part 2. Does logic shut-down technique

save power for the comparator? If yes, how much power is saved? You can calculate the percentage

power savings using equation:

%100 _

__ _ 

 

refavg

shutdownavgrefavg savepercent

P

PP P

What conclusion can you draw?

Appendix: 1-bit CMOS full-adder design.

Figure 4. Schematic of a CMOS full adder (28 transistors)

Full report due on or before 04/23/2018 (Monday) if you choose to do it.