Low Power HW

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ELEG-548: Low Power VLSI Circuit Design, Spring 2018, Final Exam

Name: ____________________________________ Student ID: ______________________

Note: Use very brief answer for each question. Your grade is decided by the accuracy instead of the

length of your answer.

1. (25’) Assume implementations of two functions F1 and F2 are shown in Figure 1. Assume the

“1”-probabilities of input signals in both circuits are:

p(a)=p(c)=0.6, p(b)=0.02.

(1). List the logic functions of F1 and F2. Are they equivalent to each other? Please use Boolean

logic transformation to verify your conclusion.

(2). Find out the gate counts for both implementations. If small area is concerned in circuit design,

which implementation would you prefer?

(3). Are there any signal correlations in both circuits? Find out the 1-probabilities of all nodes for

both implementations, and mark them in the figure.

(4). Find out the switching activities (Asw) of all nodes for both implementations, and mark them in

the figure.

(5). Assume Vdd=5V, and working frequencies of both circuits are f=100MHz. The input and

output capacitances for all the gates are equal, and for each gate:

Cin=Cout=1pF.

Find out the power difference between implementations F1 and F2. (Note: For nodes d, e and g,

C(d)=C(e)=C(g)=2pF due to the output capacitance of previous gate and input capacitance of next

gate. For input capacitance of inverter, C(b)=1pF)

(6). Based on the result in step (5), if low power is preferred in circuit design, which

implementation (F1 or F2) would you choose?

(a). Implementation F1 (b). Implementation F2

Figure 1. Comparison of two functions F1 and F2

2. (25’) Gated clock for low power: The state transition diagram of a sequential circuit is shown in

Figure 3. Assume primary inputs are a, b, and state registers as S1, S2. The state assignment is:

For state Sm0: S1S2=00; for state Sm1: S1S2=01; for state Sm2: S1S2=11.

1). Find all the self-loops in the STG. For each self-loop, list the corresponding ab value and S1S2

value.

2). From the results in (1), construct Karnaugh map for the gated-clock activation function Fa so

that when Fa=0, the clock is fed as normal clock; when Fa=1, the clock signal will be “frozen” to

save power. Please fill the Karnaugh map in Figure 2 as below.

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Figure 2. Karnaugh map for gated clock activation function Fa

3). Based on the Karnaugh map, find out the gated-clock activation function Fa. Implement it with

minimum area overhead (i.e. minimum literal count) but without abandoning any case in Karnaugh

map.

4). Based on above derived gated-clock activation function Fa and original clock signal (“clk”),

how would you implement gated-clock signal (“gated_clk”)? Draw the gate level implementation

of “gated_clk” (draw your circuit clearly), and write the logic expression of “gated_clk”. (Note:

Your implementation should only uses clk, a, b, S1 and S2 as inputs.)

Figure 3. State Transition Diagram (STG) of a sequential circuit

3. (25’) A 16-bit carry-select full adder circuit is shown in Figure 4. It takes two 16-bit inputs A, B:

A=A15A14…A0, B=B15B14…B0, and computes: SUM=A+B.

The carry-select full adder uses two 8-bit full adders to precompute the sum of higher eight bits of

inputs assuming the carry-out from the sum of lower eight bits to be “0” or “1” separately. The

actual carry-out from the lower eight bits will decide which higher 8-bit SUM to be passed to the

final output (SUM<8:15>).

(1). This circuit can be revised to implement type-2 logic shut-down technique to save power. The

A7, B7 bits can be used to construct predictor functions. Derive the “1”-predictor function g1 and

“0”-predictor function g2 for the carryout of lower 8-bit full adder. Whenever the carryout of lower

8-bit full adder can be predicted, one of the two higher 8-bit full adders can be shut down to save

power.

(2). Re-plot the circuit separately to show how type-2 logic shut-down technique is implemented.

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You need to show clearly how g1 and g2 are connected in the circuit. (Hint: You may need to add

LE (load_enable) for some registers.)

Figure 4. 16-bit carry-select full adder circuit

4.(25’) A transmission gate based pass transistor logic circuit is shown in Figure 5.

1). What is the logic function implemented at output F? Derive its logic expression, and show your

analysis in details. How many transistors are there in it? If the same logic function is implemented

with static CMOS logic, minimally how many transistors are needed?

2). For this circuit in Figure 5, replace the CMOS inverter with transistor design. How are you

going to measure its power consumption using PSPICE power simulation? Draw the complete

circuit with auxiliary power measurement circuitry and clearly show where you are going to insert

dummy voltage sources.

Figure 5. A transmission gate based pass transistor logic

Due on 05/02/2018 (Wednesday) before 12noon.