CMPS Logic Design :Use the VHDL compiler or the graphical designer and simulator to design tiny processor able to execute a mini version of the ARM Thumb instruction set in accordance with the specifications below.

MIDWESTERN STATE UNIVERSITY

DEPARTMENT OF COMPUTER SCIENCE

CMPS 3023: Logic Design

Spring semester 2019

Project Assignment

03/07/2019 - due on April 24, 2019

This project is to be performed either individually or by a group of at most 4 students.

Use the VHDL compiler or the graphical designer and simulator to design tiny processor

able to execute a mini version of the ARM Thumb instruction set in accordance with the

specifications below.

For this project, you are to design (using VHDL and components design or schematics

capture) and simulate an 8-bit processor (8-bit registers), which includes two registers R0

and R1, able to execute the instruction set shown on table 1.

Table 1. Mini version Thumb Instruction set

Mnemonic Action

ADD Rd,Rs1,Rs2 Add Rs1 and Rs2, stores in Rd 0001 100k kkss sddd

ADD Rd,Rs1,#k Add Rs1 and #k, stores in Rd 0001 110k kkss sddd

SUB Rd,Rs1,Rs2 Subtract Rs2 from Rs1, stores in Rd 0001 101k kkss sddd

SUB Rd,Rs1,#k Subtract #k from Rs1, stores in Rd 0001 111k kkss sddd

EOR Rd,Rs Xor Rs and Rd, stores in Rd 0100 0000 01ss sddd

MOV Rd,#K Move 8 bit value to Rd 0010 0ddd kkkk kkkk

AND Rd,Rs Ands Rs and Rd, stores in Rd 0100 0000 00ss sddd

NEG Rd,Rs Complements Rs, stores in Rd 0100 0010 01ss sddd

LSL Rd,Rs,#1 Left shifts Rs by 1bit, stores in Rd 0000 0000 01ss s ddd

LSR Rd,Rs,#1 Right shifts Rs by 1bit, stores in Rd 0000 1000 01ss s ddd

OUT Rs Displays contents of Rs 1101 1111 0000 0sss

kkk,sss: source register; ddd: destination register; R0 = 000, R1 = 001

The block diagram of the mini version Thumb processor is shown on Figure 1. The

machine has 18 input signals and 14 output signals. The 18 input signals consist of 16 bits

used for instructions and 2 extra bits used to clock the operations: one clock signal will

command the execution of the operation (EXE) and the other will update the destination

register (UPD) (these two bits cannot be zero at the same time). The 14 output bits are

connected to two seven-segment displays and should show the value contained in R0 (in

hexadecimal format), except when instructed to do it differently by the instruction OUT.

Coding example: MOV R0,5 in binary 0010 0000 0000 0101

MOV R1,13 in binary 0010 0001 0000 1101

MOV ADD R1,R0,R1 in binary 0001 1000 0000 1001

VERY IMPORTANT:

1. Clock signals activate circuit components when they are zero.

2. 7-segment lights go ON when their signal is zero (OFF when it is one)

Project report:

Use computer word processing and drawing tools of your choice to generate your report.

It must consist of the following items:

1. Block diagram of the circuit implementation (show major components like registers,

logic units, multiplexers, connections, etc.).

2. Printout of the circuit schematics or VHDL code used to implement the design.

3. Electronic copy of the .vhd or the .bdf file required to run the simulation.

4. Brief description of the experiment with a FPGA implementation.

Your project is due on April 24, 2019. You need to start working NOW!!!! Anything

that you try to do in the last week before the due date will not work for sure. Time is an

important factor in this project. If you write your solution in VHDL and the entire

solution has less than 3 entities described, then your maximum grade is 50. If your

project does not work or you cannot justify why it does not work, then your grade will be

zero. Acceptable justifications are based on software limitations only, and in this case you

must show you had every component defined and tested and only the integration failed.

Failure in reporting the FPGA implementation experiment will reduce your grade by ten

points. NO EXTENSIONS!!

Thumb mini

micro

processor

x15

x13

x11

x9

x7

x5

x3

x1

upd

exe

AL

b0

b5 b1

b4 b6 b2

b3

a0 to a6

a0

a5 a1

a4 a6 a2

a3

b0 to b6