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Digital Circuits lab report

library ieee; USE ieee.std_logic_1164.ALL; ENTITy lab6 IS PORT( a, b, c, d: IN std_logic; sega, segb, segc, segd, sege, segf, segg: OUT std_logic); END lab6; ARCHITECTURE arc of lab6 IS BEGIN sega<= not ( a or c or ( b and d) or ((not b) and (not d))); segb<= not ((not b) or((not c) and (not d )) or ( c and d)); segc<= not (b or (not c) or d); segd<= not (a or (c and (not d) ) or ((not b) and c) or ( (not b) and (not d) ) or (b and (not c) and d)); sege<= not (((not b) and (not d)) or ( c and ( not d))); segf<= not (a or (( not c) and ( not d )) or (b and ( not c) ) or ( b and (not d))); segg<= not (a or ( c and (not d )) or (( not b) and c ) or ( b and (not c ))); END arc;