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EECE 320 Lab 2 Fall 2019

Lab 2: Single Cycle ARM

Prof. Kredo

Due by 23:59 Friday, October 4

Objectives

• Build and test a single-cycle ARM CPU that implements a subset of the ARM Thumb instruction set • Design a combinational logic control unit

Description

In this lab you will use Logisim to build a single-cycle CPU to understand the ARM control and datapath signals. To test your CPU, you will run assembly language programs, which you write, on your CPU and simulate the operation in Logisim. You will be given two functional blocks to help you out and an assembler that will generate a file to initialize your instruction memory. You must implement the control units as combinational logic.

Details

You will be given an empty project to start your lab that includes debug output pins you must use. Do not change the vertical ordering of the pins and do not add any input or output pins. The empty project is available on Learn. Do not rename your file or your top-level circuit. All components that you design must be within a single file.

When generating your Instruction Memory, make it a 16-bit word addressable memory with an address width of 7 bits (7 bits for an address input and 16 bits of data as output). Thus, no program may be longer than 128 instructions. Use a RAM module with “One asynchronous load/store port”. Use a 32-bit word addressable RAM module with a 7-bit address for your Data Memory and select independent read and write ports.

You must use a 32-bit byte addressable program counter in a Register. Your design must have only one clock, which you receive as input from the CLK pin. Do not modify or

manipulate the clock signal. You will be given an implementation of the ARM ALU and a register file, available as subcircuits in the

blank file. The ALU works as outlined in Lab 1 and the register file has the same functionality as described in class and similar to that in the book. Ensure you do not load any library files into your submission; all of your subcircuits must be in the same file.

Your CPU must execute the following instructions: ADDS, SUBS, B{cond}, B, LDR, STR, ANDS, EORS, ORRS, MVNS and NOP. You must support all instruction formats in the Instruction Summary handout for ADDS and SUBS, the immediate instruction formats ([Rn, #imm5]) for LDR and STR, and the EQ, NE, CS, CC, MI, PL, VS, and VC branch conditions. You do not need to implement any instruction format not in the Instruction Summary handout.

To test your CPU you have three options: local simulation, an online tester, and an online grader. Running a simulation locally requires a file to initialize your instruction memory, which you can get by using the online assembler1. The assembler takes an ARM assembly language program as input and generates the contents of a file that can initialize your Instruction Memory. You can initialize your instruction memory

1http://www.ecst.csuchico.edu/∼kkredo/teaching/eece320/assembler/

EECE 320 Lab 2 Fall 2019

by right clicking on the Instruction Memory and selecting Load Image. Whenever you change the memory initialization file, you must reload it in Logisim. The lab tester2 executes an assembly program you provide on your circuit and the solution circuit and displays any differences to you. Finally, the lab grader3 executes a suite of tests on your CPU to generate an approximate lab grade.

For this lab, you must use only combinational logic to implement the control unit. However, the imple- mentation does not need to be optimized. Follow the naming conventions used in class.

Include all group member names in a text field in the design file and hand in your .circ file through Learn. Only one submission per group.

Well organized and documented designs are easier to grade and thus tend to earn more points than poor designs. If the grader can find a mistake quickly, then you’ll get partial credit. However, this is harder to do if the grader can’t determine what you were doing.

Every student must complete an independent Group Evaluation form on Learn for each lab, which may be used to adjust individual grades.

Output Ports

The output signals must be connected as follows:

PC The output of the the current PC Instruction The output of the Instruction Memory, this is the machine code for the current instruction Write Destination The write control signal for the register file D address Destination address for the register file D data Destination data for the register file N,Z,C,V Current condition code register flags (not the flags for next cycle) Memory read Read control signal for data memory Memory write Write control signal for data memory M address Address input to data memory M data in Data (write) input to data memory

Grading

The lab will be graded based on the following point distribution. Partial credit may be given as appropriate.

• 20 points: ADDS and SUBS • 30 points: Other ALU operations • 20 points: Memory operations • 10 points: Unconditional branch • 20 points: Conditional branches

A maximum of 70 points can be earned if the solution Control Unit is used exclusively for control signals.

2http://www.ecst.csuchico.edu/∼kkredo/teaching/eece320/tester/ 3http://www.ecst.csuchico.edu/∼kkredo/teaching/eece320/grader/

EECE 320 Lab 2 Fall 2019

Hints

• Test and debug in steps. Start with a subset of the lab requirements, implement it, test it, and then add other requirements. Performing the testing and debugging in steps will ease your efforts. The grading list is a recommended implementation path.

• Think about the hardware you are creating before trying it out. The text is necessarily vague and leaves out details, so do not simply copy the figures and expect your CPU to work.

• Create subcircuits for your design. This simplifies the layout and allows you to test in steps. • At times you may wish to restart your local simulation. If you add a button to your design, you can

tie it to the reset or zero inputs of all sequential elements. This allows you to quickly reset your entire circuit and start over again.

Solution Control Unit

A complete control unit is provided in the EECE320 library for your testing and comparison purposes. However, you will not have access to the internal working of the subcircuit. The control unit takes as input the current instruction and the current flag values (those set by the previous instructions). Below are details on the meaning of the output signal values which control multiplexers.

Signal Value Meaning

PC Src 0 PC set to PC+2

1 PC set to output of ALU

S1 Mux 0 ALU Rn input from RF

1 ALU Rn input from PC+4

RF Mux 0 S2 addr from Rm

1 S2 addr from Rd

S2 Mux 0 ALU Rx input from RF

1 ALU Rx input from immediate mux

Mem Mux 0 ALU result used for RF data

1 Memory output used for RF data

Imm Mux

00 Immediate value for ADDS and SUBS

01 Immediate value for LDR and STR

10 Immediate value for unconditional branch

11 Immediate value for conditional branch