Single Cycle ARM
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InstructionSummary.docxInstruction Summary Spring 2019
EECE 320 Instruction Summary Spring 2019
Instruction Summary Spring 2019
Introduction
This handout summarizes the operation and encoding for the instructions used in labs for the class. All instructions use the lower registers (R0-R7).
RTL Notation
|
Notation |
Description |
|
x←y |
Assign y to x |
|
SE{x} |
Sign extend x to 32 bits |
|
ZE{x} |
Zero extend x to 32 bits |
|
x:y |
Concatenate x and y |
|
x[m..n] |
Bitfield operator, use bits m to n of x |
|
AND, OR, EOR, NOT |
Bitwise operators |
|
x<<y, x>>y |
Shift x left or right by y places with zeros added as needed |
|
x ASR y |
Shift x right by y places extending the most significant bit as needed |
|
M[x] |
Access memory at location x |
|
R[x] |
Contents of register x |
Condition Flags
|
Flag |
Name |
Instructions |
Operation |
|
N |
Negative |
All appropriate |
Set to bit 31 of the result |
|
Z |
Zero |
All appropriate |
Set to 1 when the result equals 0 and set to 0 otherwise |
|
C |
Carry |
Add, subtract, compare |
Set to 1 if a carry occurs and set to 0 otherwise |
|
|
|
Shift and rotate |
Set to last bit shifted out of register |
|
V |
Overflow |
All appropriate |
Set to 1 if an overflow occurs and set to 0 otherwise |
Memory Instructions
Assembly Format and Function
|
Instruction |
RTL |
Flags Updated |
Notes |
|
LDR Rd, [Rn, #const] |
R[Rd]←M[R[Rn]+ZE{imm5:00}] |
|
0 ≤const≤ 124 and multiple of 4 |
|
STR Rd, [Rn, #const] |
M[R[Rn]+ZE{imm5:00}]←R[Rd] |
|
0 ≤const≤ 124 and multiple of 4 |
Instruction Format
|
15 |
14 |
13 |
12 |
11 10 9 |
8 7 6 5 |
4 3 2 |
1 0 |
|||
|
0 |
1 |
1 |
0 |
L |
|
imm5 |
|
Rn |
|
Rd |
L Load indicator.
0 Store
1 Load
Addition and Subtraction Instructions
Assembly Format and Function
|
Instruction |
RTL |
Flags Updated |
Notes |
||
|
ADDS Rd, Rn, #const |
R[Rd]←R[Rn]+ZE{imm3} |
N Z |
C |
V |
0 ≤const≤ 7 |
|
ADDS Rd, Rn, Rm |
R[Rd]←R[Rn]+R[Rm] |
N Z |
C |
V |
|
|
SUBS Rd, Rn, #const |
R[Rd]←R[Rn]-ZE{imm3} |
N Z |
C |
V |
0 ≤const≤ 7 |
|
SUBS Rd, Rn, Rm |
R[Rd]←R[Rn]-R[Rm] |
N Z |
C |
V |
|
Instruction Format
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 7 6 5 |
4 3 2 |
1 0 |
||
|
0 |
0 |
0 |
1 |
1 |
i |
op |
Rm/imm3 |
|
Rn |
|
Rd |
i Immediate field indicator.
0 Rm/imm3 is a register field
1 Rm/imm3 is an immediate field op Operation indicator.
0 Addition
1 Subtraction
Register Manipulation Instructions
Assembly Format and Function
|
Instruction |
RTL |
Updated Flags |
||
|
ANDS Rd, Rn |
R[Rd]←R[Rd] AND R[Rn] |
N |
Z |
|
|
ASRS Rd, Rn |
R[Rd]←R[Rd] ASR R[Rn][7..0] |
N |
Z |
C+ |
|
BICS Rd, Rn |
R[Rd]←R[Rd] AND (NOT R[Rn]) |
N |
Z |
|
|
EORS Rd, Rn |
R[Rd]←R[Rd] EOR R[Rn] |
N |
Z |
|
|
LSLS Rd, Rn |
R[Rd]←R[Rd]<<R[Rn][7..0] |
N |
Z |
C+ |
|
LSRS Rd, Rn |
R[Rd]←R[Rd]>>R[Rn][7..0] |
N |
Z |
C+ |
|
MVNS Rd, Rn |
R[Rd]←NOT R[Rn] |
N |
Z |
|
|
ORRS Rd, Rn |
R[Rd]←R[Rd] OR R[Rn] |
N |
Z |
|
|
RORS Rd, Rn |
R[Rd]←R[Rd]<<(32-R[Rn][7..0]) OR R[Rd]>>R[Rn][7..0] |
N |
Z |
C+ |
C+: Carry unchanged if R[Rn][7..0]==0.
Instruction Format
|
15 |
14 |
13 |
12 |
11 |
10 9 |
8 7 6 5 |
4 3 2 |
1 0 |
|||
|
0 |
1 |
0 |
0 |
0 |
0 |
|
op |
|
Rn |
|
Rd |
op Operation indicator.
|
|
|
No Operation (NOP) Instruction
Assembly Format and Function
|
Instruction |
RTL |
Flags Updated |
|
NOP |
Do nothing |
|
Note that there are two versions of the NOP instruction, with the second (all zero) version not standard ARM Thumb.
Instruction Format
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
1 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Conditional Branch Instructions
Assembly Format and Function
|
Instruction |
RTL |
Flags Updated |
|
Bcond LABEL |
If cond then PC←PC+4+SE{imm8:0} |
|
See below for condition codes.
Instruction Format
|
15 |
14 |
13 |
12 11 |
10 9 8 7 6 5 |
4 3 2 1 0 |
||
|
1 |
1 |
0 |
1 |
|
cond |
|
imm8 |
cond Condition code.
|
Encoded Value |
Assembly Condition |
Flags Checked |
Description |
|
0000 |
EQ |
Z==1 |
Equal to zero |
|
0001 |
NE |
Z==0 |
Not equal to zero |
|
0010 |
CS |
C==1 |
Carry set |
|
0011 |
CC |
C==0 |
Carry clear |
|
0100 |
MI |
N==1 |
Minus (Negative) |
|
0101 |
PL |
N==0 |
Plus (Non-negative) |
|
0110 |
VS |
V==1 |
Overflow set |
|
0111 |
VC |
V==0 |
Overflow clear |
Unconditional Branch Instruction
Assembly Format and Function
|
Instruction |
RTL |
Flags Updated |
|
B LABEL |
PC←PC+4+SE{imm11:0} |
|
Instruction Format
|
15 |
14 |
13 |
12 |
11 10 9 8 7 |
6 5 4 3 2 1 0 |
|
|
1 |
1 |
1 |
0 |
0 |
|
imm11 |
1
1
5
