HW

Q1: Use a K-Map to minimize the following expressionsto both a minimum SOP and a minimum POS form. Show an implementation for both the minimized POS and minimized SOP.

A. F(A,B,C)= AB’+A+BC’+A’B’C’

B. F(A,B,C,D) = (A+B+D)’ + ABC’ + CD’

Q4: Create an ideal truth table, then draw an “ideal” timing diagram for F (A, B, C )= ( A  AB)+ C . Do not do any simplification of the expression before showing the timing diagram. Then reduce the equation to the smallest possible expression. Now draw the “ideal” timing diagram and compare the results with the previous timing diagram.

( High C B A Low )1 2 3 4 5 6 7 (ns)

Q5: Use the input timing sequence shown in Q4. Create an “ideal” timing diagram (i.e., zero delay for gates and invertors) for F(A, B,C) AC +(BB).