COMPUTER ENGINEERING

CEC Homework Definitions Provide a Definition for the following Terms. Answer related question if present. It is NOT

sufficient to simply provide the words for which an acronym is an abbreviation. Define and explain sufficient to show that you understand the term and usage within the context of this course.

1). EDA Design flow

2). Functional Simulation

3). Device level Simulation

4). Timing Simulation

5). Synthesis

6). SOC

7). ASIC

8). Fab-less

9). HDL 10). Homogeneous Multiprocessor 11). Heterogeneous Multiprocessor 12). DSP 13). Processor Family 14). Feature Size 15). Mask set

Questions

16). Explain why (3) levels of simulation are appropriate in an EDA design flow. Compare & contrast each of the 3 levels and explain why seperating these (3) levels and types of simulation can improve engineer productivity.

17). Compare & contrast the (3) circuit design styles given below. Provide an example application where each might be appropriate.

a) Full Custom b) Standard Cell c) PLD/FPGA

18). Generate a single figure with three lines showing the cost / unit for each of the three design styles given in Q # 17. For the FPGA design - assume a $40E3 design/NRE cost and a $60 FPGA used. For the Full Custom, assume a design/NRE cost of $1.2E6, and a manufacturing cost of $4. For the Standard Cell, assume a design/NRE cost of $400E3 and a manufacturing cost of $4.75. The Y axis should be the cost / unit of the IC, and X axis should be volume of manufacture from 10 units to 50E6 units.

19). Using the data / figure from Q # 18, over what range of volumes does each of (a - c) from Q # 17 result in the lowest design cost?

20). When examining a design style tradeoff between FPGA and Full Custom, what other engineering factors or considerations in the choice exist beyond cost / unit?