Verilog Lab EE
louisJ
heap2.zipadder8.v
`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 20:10:15 09/25/2016 // Design Name: // Module Name: adder4 // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module adder8( input [7:0] A, input [7:0] B, input C0, output [7:0] S, output C8 ); assign {C8,S} = {1'b0, A} + {1'b0, B} + C0; endmodule
adder8_summary.html
| mem16x8 Project Status | |||
| Project File: | heap_sol.xise | Parser Errors: | X 1 Error |
| Module Name: | adder8 | Implementation State: | New |
| Target Device: | xc6slx16-3csg324 |
| |
| Product Version: | ISE 14.7 |
| |
| Design Goal: | Balanced |
| |
| Design Strategy: | Xilinx Default (unlocked) |
| |
| Environment: |
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| Detailed Reports | [-] | ||||
| Report Name | Status | Generated | Errors | Warnings | Infos |
| Synthesis Report | |||||
| Translation Report | |||||
| Map Report | |||||
| Place and Route Report | |||||
| Power Report | |||||
| Post-PAR Static Timing Report | |||||
| Bitgen Report |
| Secondary Reports | [-] | |
| Report Name | Status | Generated |
bcd_display.v
`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 20:46:08 11/24/2015 // Design Name: // Module Name: sqrt_display // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module bcd_display( input [7:0] DISP, input CLK, input RST, output reg [3:0] THOUS, output reg [3:0] HUNS, output reg [3:0] TENS, output reg [3:0] ONES ); integer i; reg [4:0] th1; reg [4:0] h1; reg [4:0] t1; reg [4:0] o1; reg [4:0] th0; reg [4:0] h0; reg [4:0] t0; reg [4:0] o0; /* always @(X or DISP) begin thous_int[1] = 4'd0; thous_int[0] = 4'd0; huns_int[1] = 4'd0; huns_int[0] = 4'd0; tens_int[1] = 4'd0; tens_int[0] = 4'd0; ones_int[1] = 4'd0; ones_int[0] = 4'd0; // Taken from http://www.eng.utah.edu/~nmcdonal/Tutorials/BCDTutorial/BCDConversion.html for (i=15; i>=0; i=i-1) begin // add 3 to columns >= 5 if(thous_int[1] >= 5) thous_int[1] = thous_int[1] + 3; if(huns_int[1] >= 5) huns_int[1] = huns_int[1] + 3; if(tens_int[1] >= 5) tens_int[1] = tens_int[1] + 3; if(ones_int[1] >= 5) ones_int[1] = ones_int[1] + 3; // shift left one thous_int[1] = thous_int[1] << 1; thous_int[1][0] = huns_int[1][3]; huns_int[1] = huns_int[1] << 1; huns_int[1][0] = tens_int[1][3]; tens_int[1] = tens_int[1] << 1; tens_int[1][0] = ones_int[1][3]; ones_int[1] = ones_int[1] << 1; ones_int[1][0] = X[i]; end for (i=7; i>=0; i=i-1) begin // add 3 to columns >= 5 if(huns_int[0] >= 5) huns_int[0] = huns_int[0] + 3; if(tens_int[0] >= 5) tens_int[0] = tens_int[0] + 3; if(ones_int[0] >= 5) ones_int[0] = ones_int[0] + 3; // shift left one huns_int[0] = huns_int[0] << 1; huns_int[0][0] = tens_int[0][3]; tens_int[0] = tens_int[0] << 1; tens_int[0][0] = ones_int[0][3]; ones_int[0] = ones_int[0] << 1; ones_int[0][0] = DISP[0]; end if (which) begin THOUS = thous_int[1]; HUNS = huns_int[1]; TENS = tens_int[1]; ONES = ones_int[1]; end else begin THOUS = thous_int[0]; HUNS = huns_int[0]; TENS = tens_int[0]; ONES = ones_int[0]; end end */ always @* begin th0 = 0; h0 = 0; t0 = 0; o0 = 0; if(DISP[7] == 1) begin th0 = th0+0; h0=h0+1; t0=t0+2; o0=o0+8; if(o0 >= 10) begin o0 = o0 - 10; t1 = t1 + 1; if(t1 >= 10) begin t0 = t0 - 10; h0 = h0 + 1; if(h0 >=10) begin h0 = h0 - 10; th0 = th0 + 1; end end end end if(DISP[6] == 1) begin th0 = th0+0; h0=h0+0; t0=t0+6; o0=o0+4; if(o0 >= 10) begin o0 = o0 - 10; t0 = t0 + 1; if(t0 >= 10) begin t0 = t0 - 10; h0 = h0 + 1; if(h0 >=10) begin h0 = h0 - 10; th0 = th0 + 1; end end end end if(DISP[5] == 1) begin th0 = th0+0; h0=h0+0; t0=t0+3; o0=o0+2; if(o0 >= 10) begin o0 = o0 - 10; t0 = t0 + 1; if(t0 >= 10) begin t0 = t0 - 10; h0 = h0 + 1; if(h0 >=10) begin h0 = h0 - 10; th0 = th0 + 1; end end end end if(DISP[4] == 1) begin th0 = th0+0; h0=h0+0; t0=t0+1; o0=o0+6; if(o0 >= 10) begin o0 = o0 - 10; t0 = t0 + 1; if(t0 >= 10) begin t0 = t0 - 10; h0 = h0 + 1; if(h0 >=10) begin h0 = h0 - 10; th0 = th0 + 1; end end end end if(DISP[3] == 1) begin th0 = th0+0; h0=h0+0; t0=t0+0; o0=o0+8; if(o0 >= 10) begin o0 = o0 - 10; t0 = t0 + 1; if(t0 >= 10) begin t0 = t0 - 10; h0 = h0 + 1; if(h0 >=10) begin h0 = h0 - 10; th0 = th0 + 1; end end end end if(DISP[2] == 1) begin th0 = th0+0; h0=h0+0; t0=t0+0; o0=o0+4; if(o0 >= 10) begin o0 = o0 - 10; t0 = t0 + 1; if(t0 >= 10) begin t0 = t0 - 10; h0 = h0 + 1; if(h0 >=10) begin h0 = h0 - 10; th0 = th0 + 1; end end end end if(DISP[1] == 1) begin th0 = th0+0; h0=h0+0; t0=t0+0; o0=o0+2; if(o0 >= 10) begin o0 = o0 - 10; t0 = t0 + 1; if(t0 >= 10) begin t0 = t0 - 10; h0 = h0 + 1; if(h0 >=10) begin h0 = h0 - 10; th0 = th0 + 1; end end end end if(DISP[0] == 1) begin th0 = th0+0; h0=h0+0; t0=t0+0; o0=o0+1; if(o0 >= 10) begin o0 = o0 - 10; t0 = t0 + 1; if(t0 >= 10) begin t0 = t0 - 10; h0 = h0 + 1; if(h0 >=10) begin h0 = h0 - 10; th0 = th0 + 1; end end end end end always @* begin THOUS = th0[3:0]; HUNS = h0[3:0]; TENS = t0[3:0]; ONES = o0[3:0]; end endmodule
cntr8.v
`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 09:38:39 04/05/2017 // Design Name: // Module Name: cntr8 // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module cntr8( input clk, input reset, input inc, input dec, output [7:0] q ); reg [7:0] q_fb; always @(posedge clk) begin if(reset == 1) q_fb <= 8'd0; else if(inc == 1) q_fb <= q_fb+1; else if(dec == 1) q_fb <= q_fb-1; end assign q = q_fb; endmodule
comp8.v
`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 12:56:56 10/12/2016 // Design Name: // Module Name: comp8 // Project Name: // Target Devices: // Tool versions: // Description: Unsigned 8-bit comparator // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module comp8( input [7:0] A, input [7:0] B, output LT, output GT, output EQ ); wire [8:0] Aint, Bint; assign Aint = {1'b0, A}; assign Bint = {1'b0, B}; assign LT = (Aint < Bint); assign GT = (Aint > Bint); assign EQ = (Aint == Bint); endmodule
dff1s.v
`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 07:23:33 08/31/2016 // Design Name: // Module Name: dff1 // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module dff1s( input clk, input clr, input set, input d, output reg q ); always@(posedge clk) begin if(clr == 1) q <= 0; else if(set == 1) q <= 1; else q <= d; end endmodule
fuse.xmsgs
fuseRelaunch.cmd
-intstyle "ise" -incremental -lib "unisims_ver" -lib "unimacro_ver" -lib "xilinxcorelib_ver" -lib "secureip" -o "C:/Users/Mark/Dropbox/EE209/Lab/heap2_sol/heap_soc_tb_isim_beh.exe" -prj "C:/Users/Mark/Dropbox/EE209/Lab/heap2_sol/heap_soc_tb_beh.prj" "work.heap_soc_tb" "work.glbl"
heap.cmd_log
xst -intstyle ise -ifn "C:/Users/Mark/Dropbox/EE209/Lab/heap_sol/heap.xst" -ofn "C:/Users/Mark/Dropbox/EE209/Lab/heap_sol/heap.syr" xst -intstyle ise -ifn "C:/Users/Mark/Dropbox/EE209/Lab/heap_sol/heap.xst" -ofn "C:/Users/Mark/Dropbox/EE209/Lab/heap_sol/heap.syr" xst -intstyle ise -ifn "C:/Users/Mark/Dropbox/EE209/Lab/heap_sol/heap.xst" -ofn "C:/Users/Mark/Dropbox/EE209/Lab/heap_sol/heap.syr" xst -intstyle ise -ifn "C:/Users/Mark/Dropbox/EE209/Lab/heap_sol/heap.xst" -ofn "C:/Users/Mark/Dropbox/EE209/Lab/heap_sol/heap.syr" xst -intstyle ise -ifn "C:/Users/Mark/Dropbox/EE209/Lab/heap_sol/heap.xst" -ofn "C:/Users/Mark/Dropbox/EE209/Lab/heap_sol/heap.syr" xst -intstyle ise -ifn "C:/Users/Mark/Dropbox/EE209/Lab/heap_sol/heap.xst" -ofn "C:/Users/Mark/Dropbox/EE209/Lab/heap_sol/heap.syr" xst -intstyle ise -ifn "C:/Users/Mark/Dropbox/EE209/Lab/heap_sol/heap.xst" -ofn "C:/Users/Mark/Dropbox/EE209/Lab/heap_sol/heap.syr" xst -intstyle ise -ifn "C:/Users/Mark/Dropbox/EE209/Lab/heap_sol/heap.xst" -ofn "C:/Users/Mark/Dropbox/EE209/Lab/heap_sol/heap.syr" xst -intstyle ise -ifn "C:/Users/Mark/Dropbox/EE209/Lab/heap_sol/heap.xst" -ofn "C:/Users/Mark/Dropbox/EE209/Lab/heap_sol/heap.syr" xst -intstyle ise -ifn "C:/Users/Mark/Dropbox/EE209/Lab/heap_sol/heap.xst" -ofn "C:/Users/Mark/Dropbox/EE209/Lab/heap_sol/heap.syr" xst -intstyle ise -ifn "C:/Users/Mark/Dropbox/EE209/Lab/heap_sol/heap.xst" -ofn "C:/Users/Mark/Dropbox/EE209/Lab/heap_sol/heap.syr" xst -intstyle ise -ifn "C:/Users/Mark/Dropbox/EE209/Lab/heap_sol/heap.xst" -ofn "C:/Users/Mark/Dropbox/EE209/Lab/heap_sol/heap.syr" xst -intstyle ise -ifn "C:/Users/Mark/Dropbox/EE209/Lab/heap_sol/heap.xst" -ofn "C:/Users/Mark/Dropbox/EE209/Lab/heap_sol/heap.syr" xst -intstyle ise -ifn "C:/Users/Mark/Dropbox/EE209/Lab/heap_sol/heap.xst" -ofn "C:/Users/Mark/Dropbox/EE209/Lab/heap_sol/heap.syr" xst -intstyle ise -ifn "C:/Users/Mark/Dropbox/EE209/Lab/heap_sol/heap.xst" -ofn "C:/Users/Mark/Dropbox/EE209/Lab/heap_sol/heap.syr" xst -intstyle ise -ifn "C:/Users/Mark/Dropbox/EE209/Lab/heap_sol/heap.xst" -ofn "C:/Users/Mark/Dropbox/EE209/Lab/heap_sol/heap.syr" xst -intstyle ise -ifn "C:/Users/Mark/Dropbox/EE209/Lab/heap_sol/heap.xst" -ofn "C:/Users/Mark/Dropbox/EE209/Lab/heap_sol/heap.syr" xst -intstyle ise -ifn "C:/Users/Mark/Dropbox/EE209/Lab/heap_sol/heap.xst" -ofn "C:/Users/Mark/Dropbox/EE209/Lab/heap_sol/heap.syr"
heap.lso
work
heap.ngc
XILINX-XDB 0.1 STUB 0.1 ASCII XILINX-XDM V1.6e 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heap.prj
verilog work "reg8e.v" verilog work "pe4_2.v" verilog work "mux3_8bit.v" verilog work "mem16x8.v" verilog work "ctrlpush.v" verilog work "ctrlpop.v" verilog work "cntr8.v" verilog work "heap.v"
heap.stx
heap.syr
Release 14.7 - xst P.20131013 (nt64) Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to xst/projnav.tmp Total REAL time to Xst completion: 1.00 secs Total CPU time to Xst completion: 0.46 secs --> Parameter xsthdpdir set to xst Total REAL time to Xst completion: 1.00 secs Total CPU time to Xst completion: 0.46 secs --> Reading design: heap.prj TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Parsing 3) HDL Elaboration 4) HDL Synthesis 4.1) HDL Synthesis Report 5) Advanced HDL Synthesis 5.1) Advanced HDL Synthesis Report 6) Low Level Synthesis 7) Partition Report 8) Design Summary 8.1) Primitive and Black Box Usage 8.2) Device utilization summary 8.3) Partition Resource Summary 8.4) Timing Report 8.4.1) Clock Information 8.4.2) Asynchronous Control Signals Information 8.4.3) Timing Summary 8.4.4) Timing Details 8.4.5) Cross Clock Domains Report ========================================================================= * Synthesis Options Summary * ========================================================================= ---- Source Parameters Input File Name : "heap.prj" Ignore Synthesis Constraint File : NO ---- Target Parameters Output File Name : "heap" Output Format : NGC Target Device : xc6slx16-3-csg324 ---- Source Options Top Module Name : heap Automatic FSM Extraction : YES FSM Encoding Algorithm : Auto Safe Implementation : No FSM Style : LUT RAM Extraction : Yes RAM Style : Auto ROM Extraction : Yes Shift Register Extraction : YES ROM Style : Auto Resource Sharing : YES Asynchronous To Synchronous : NO Shift Register Minimum Size : 2 Use DSP Block : Auto Automatic Register Balancing : No ---- Target Options LUT Combining : Auto Reduce Control Sets : Auto Add IO Buffers : YES Global Maximum Fanout : 100000 Add Generic Clock Buffer(BUFG) : 16 Register Duplication : YES Optimize Instantiated Primitives : NO Use Clock Enable : Auto Use Synchronous Set : Auto Use Synchronous Reset : Auto Pack IO Registers into IOBs : Auto Equivalent register Removal : YES ---- General Options Optimization Goal : Speed Optimization Effort : 1 Power Reduction : NO Keep Hierarchy : No Netlist Hierarchy : As_Optimized RTL Output : Yes Global Optimization : AllClockNets Read Cores : YES Write Timing Constraints : NO Cross Clock Analysis : NO Hierarchy Separator : / Bus Delimiter : <> Case Specifier : Maintain Slice Utilization Ratio : 100 BRAM Utilization Ratio : 100 DSP48 Utilization Ratio : 100 Auto BRAM Packing : NO Slice Utilization Ratio Delta : 5 ========================================================================= ========================================================================= * HDL Parsing * ========================================================================= Analyzing Verilog file "C:\Users\Mark\Dropbox\EE209\Lab\heap_sol\reg8e.v" into library work Parsing module <reg8e>. Analyzing Verilog file "C:\Users\Mark\Dropbox\EE209\Lab\heap_sol\pe4_2.v" into library work Parsing module <pe4_2>. Analyzing Verilog file "C:\Users\Mark\Dropbox\EE209\Lab\heap_sol\mux3_8bit.v" into library work Parsing module <mux3_8bit>. Analyzing Verilog file "C:\Users\Mark\Dropbox\EE209\Lab\heap_sol\mem16x8.v" into library work Parsing module <mem256x8>. Analyzing Verilog file "C:\Users\Mark\Dropbox\EE209\Lab\heap_sol\ctrlpush.v" into library work Parsing module <ctrlpush>. Analyzing Verilog file "C:\Users\Mark\Dropbox\EE209\Lab\heap_sol\ctrlpop.v" into library work Parsing module <ctrlpop>. Analyzing Verilog file "C:\Users\Mark\Dropbox\EE209\Lab\heap_sol\cntr8.v" into library work Parsing module <cntr8>. Analyzing Verilog file "C:\Users\Mark\Dropbox\EE209\Lab\heap_sol\heap.v" into library work Parsing module <heap>. ========================================================================= * HDL Elaboration * ========================================================================= Elaborating module <heap>. Elaborating module <cntr8>. WARNING:HDLCompiler:413 - "C:\Users\Mark\Dropbox\EE209\Lab\heap_sol\cntr8.v" Line 33: Result of 9-bit expression is truncated to fit in 8-bit target. WARNING:HDLCompiler:413 - "C:\Users\Mark\Dropbox\EE209\Lab\heap_sol\cntr8.v" Line 34: Result of 32-bit expression is truncated to fit in 8-bit target. Elaborating module <mem256x8>. Elaborating module <pe4_2>. Elaborating module <mux3_8bit>. Elaborating module <ctrlpush>. WARNING:HDLCompiler:413 - "C:\Users\Mark\Dropbox\EE209\Lab\heap_sol\ctrlpush.v" Line 49: Result of 32-bit expression is truncated to fit in 8-bit target. Elaborating module <reg8e>. WARNING:HDLCompiler:1127 - "C:\Users\Mark\Dropbox\EE209\Lab\heap_sol\ctrlpush.v" Line 54: Assignment to qidle ignored, since the identifier is never used Elaborating module <ctrlpop>. WARNING:HDLCompiler:1127 - "C:\Users\Mark\Dropbox\EE209\Lab\heap_sol\ctrlpop.v" Line 42: Assignment to qidle ignored, since the identifier is never used WARNING:HDLCompiler:413 - "C:\Users\Mark\Dropbox\EE209\Lab\heap_sol\ctrlpop.v" Line 54: Result of 32-bit expression is truncated to fit in 8-bit target. WARNING:HDLCompiler:413 - "C:\Users\Mark\Dropbox\EE209\Lab\heap_sol\ctrlpop.v" Line 57: Result of 32-bit expression is truncated to fit in 8-bit target. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit <heap>. Related source file is "C:\Users\Mark\Dropbox\EE209\Lab\heap_sol\heap.v". INFO:Xst:3210 - "C:\Users\Mark\Dropbox\EE209\Lab\heap_sol\heap.v" line 54: Output port <V> of the instance <goenc> is unconnected or connected to loadless signal. Found 1-bit register for signal <popworking>. Found 1-bit register for signal <done>. Found 1-bit register for signal <pushworking>. Found 8-bit comparator greater for signal <size[7]_PWR_1_o_LessThan_9_o> created at line 85 Summary: inferred 3 D-type flip-flop(s). inferred 1 Comparator(s). Unit <heap> synthesized. Synthesizing Unit <cntr8>. Related source file is "C:\Users\Mark\Dropbox\EE209\Lab\heap_sol\cntr8.v". Found 8-bit register for signal <q_fb>. Found 8-bit adder for signal <q_fb[7]_GND_2_o_add_3_OUT> created at line 33. Found 8-bit subtractor for signal <GND_2_o_GND_2_o_sub_6_OUT<7:0>> created at line 34. Summary: inferred 1 Adder/Subtractor(s). inferred 8 D-type flip-flop(s). Unit <cntr8> synthesized. Synthesizing Unit <mem256x8>. Related source file is "C:\Users\Mark\Dropbox\EE209\Lab\heap_sol\mem16x8.v". Found 256x8-bit single-port RAM <Mram_mem_array> for signal <mem_array>. Summary: inferred 1 RAM(s). Unit <mem256x8> synthesized. Synthesizing Unit <pe4_2>. Related source file is "C:\Users\Mark\Dropbox\EE209\Lab\heap_sol\pe4_2.v". Summary: inferred 1 Multiplexer(s). Unit <pe4_2> synthesized. Synthesizing Unit <mux3_8bit>. Related source file is "C:\Users\Mark\Dropbox\EE209\Lab\heap_sol\mux3_8bit.v". Summary: inferred 2 Multiplexer(s). Unit <mux3_8bit> synthesized. Synthesizing Unit <ctrlpush>. Related source file is "C:\Users\Mark\Dropbox\EE209\Lab\heap_sol\ctrlpush.v". Found 5-bit register for signal <state>. Found finite state machine <FSM_0> for signal <state>. ----------------------------------------------------------------------- | States | 5 | | Transitions | 9 | | Inputs | 4 | | Outputs | 4 | | Clock | clk (rising_edge) | | Reset | reset (positive) | | Reset type | synchronous | | Reset State | 10000 | | Encoding | auto | | Implementation | LUT | ----------------------------------------------------------------------- Found 9-bit adder for signal <n0066> created at line 49. Found 8-bit comparator greater for signal <dinltp> created at line 48 Found 9-bit comparator greater for signal <GND_6_o_BUS_0002_LessThan_19_o> created at line 70 Summary: inferred 1 Adder/Subtractor(s). inferred 2 Comparator(s). inferred 3 Multiplexer(s). inferred 1 Finite State Machine(s). Unit <ctrlpush> synthesized. Synthesizing Unit <reg8e>. Related source file is "C:\Users\Mark\Dropbox\EE209\Lab\heap_sol\reg8e.v". Found 8-bit register for signal <q>. Summary: inferred 8 D-type flip-flop(s). Unit <reg8e> synthesized. Synthesizing Unit <ctrlpop>. Related source file is "C:\Users\Mark\Dropbox\EE209\Lab\heap_sol\ctrlpop.v". Found 6-bit register for signal <state>. Found finite state machine <FSM_1> for signal <state>. ----------------------------------------------------------------------- | States | 6 | | Transitions | 11 | | Inputs | 5 | | Outputs | 5 | | Clock | clk (rising_edge) | | Reset | reset (positive) | | Reset type | synchronous | | Reset State | 100000 | | Encoding | auto | | Implementation | LUT | ----------------------------------------------------------------------- Found 9-bit adder for signal <n0081> created at line 54. Found 8-bit comparator greater for signal <sizegt2> created at line 44 Found 9-bit comparator greater for signal <n0002> created at line 45 Found 8-bit comparator greater for signal <n0004> created at line 46 Found 8-bit comparator greater for signal <cltp> created at line 47 Found 8-bit comparator greater for signal <mdout_lt_c> created at line 59 Summary: inferred 1 Adder/Subtractor(s). inferred 5 Comparator(s). inferred 7 Multiplexer(s). inferred 1 Finite State Machine(s). Unit <ctrlpop> synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # RAMs : 1 256x8-bit single-port RAM : 1 # Adders/Subtractors : 3 8-bit addsub : 1 9-bit adder : 2 # Registers : 10 1-bit register : 3 8-bit register : 7 # Comparators : 8 8-bit comparator greater : 6 9-bit comparator greater : 2 # Multiplexers : 15 2-bit 2-to-1 multiplexer : 1 32-bit 2-to-1 multiplexer : 6 8-bit 2-to-1 multiplexer : 8 # FSMs : 2 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Synthesizing (advanced) Unit <cntr8>. The following registers are absorbed into counter <q_fb>: 1 register on signal <q_fb>. Unit <cntr8> synthesized (advanced). Synthesizing (advanced) Unit <mem256x8>. INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram_mem_array> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. ----------------------------------------------------------------------- | ram_type | Distributed | | ----------------------------------------------------------------------- | Port A | | aspect ratio | 256-word x 8-bit | | | clkA | connected to signal <clk> | rise | | weA | connected to signal <wen> | high | | addrA | connected to signal <addr> | | | diA | connected to signal <din> | | | doA | connected to internal node | | ----------------------------------------------------------------------- Unit <mem256x8> synthesized (advanced). ========================================================================= Advanced HDL Synthesis Report Macro Statistics # RAMs : 1 256x8-bit single-port distributed RAM : 1 # Adders/Subtractors : 2 9-bit adder : 2 # Counters : 1 8-bit updown counter : 1 # Registers : 51 Flip-Flops : 51 # Comparators : 8 8-bit comparator greater : 6 9-bit comparator greater : 2 # Multiplexers : 14 32-bit 2-to-1 multiplexer : 6 8-bit 2-to-1 multiplexer : 8 # FSMs : 2 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Analyzing FSM <MFsm> for best encoding. Optimizing FSM <push_control/FSM_0> on signal <state[1:3]> with gray encoding. ------------------- State | Encoding ------------------- 10000 | 000 00001 | 001 00100 | 011 00010 | 010 01000 | 110 ------------------- Analyzing FSM <MFsm> for best encoding. Optimizing FSM <pop_control/FSM_1> on signal <state[1:6]> with user encoding. -------------------- State | Encoding -------------------- 100000 | 100000 000001 | 000001 001000 | 001000 000010 | 000010 000100 | 000100 010000 | 010000 -------------------- Optimizing unit <reg8e> ... Optimizing unit <heap> ... Optimizing unit <ctrlpush> ... Optimizing unit <ctrlpop> ... Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block heap, actual ratio is 1. Final Macro Processing ... ========================================================================= Final Register Report Macro Statistics # Registers : 68 Flip-Flops : 68 ========================================================================= ========================================================================= * Partition Report * ========================================================================= Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- ========================================================================= * Design Summary * ========================================================================= Top Level Output File Name : heap.ngc Primitive and Black Box Usage: ------------------------------ # BELS : 196 # INV : 1 # LUT2 : 18 # LUT3 : 6 # LUT4 : 33 # LUT5 : 51 # LUT6 : 71 # MUXCY : 7 # MUXF7 : 1 # XORCY : 8 # FlipFlops/Latches : 68 # FD : 3 # FDR : 40 # FDRE : 24 # FDS : 1 # RAMS : 8 # RAM256X1S : 8 # Clock Buffers : 1 # BUFGP : 1 # IO Buffers : 29 # IBUF : 11 # OBUF : 18 Device utilization summary: --------------------------- Selected Device : 6slx16csg324-3 Slice Logic Utilization: Number of Slice Registers: 68 out of 18224 0% Number of Slice LUTs: 212 out of 9112 2% Number used as Logic: 180 out of 9112 1% Number used as Memory: 32 out of 2176 1% Number used as RAM: 32 Slice Logic Distribution: Number of LUT Flip Flop pairs used: 220 Number with an unused Flip Flop: 152 out of 220 69% Number with an unused LUT: 8 out of 220 3% Number of fully used LUT-FF pairs: 60 out of 220 27% Number of unique control sets: 5 IO Utilization: Number of IOs: 30 Number of bonded IOBs: 30 out of 232 12% Specific Feature Utilization: Number of BUFG/BUFGCTRLs: 1 out of 16 6% --------------------------- Partition Resource Summary: --------------------------- No Partitions were found in this design. --------------------------- ========================================================================= Timing Report NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE. Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ clk | BUFGP | 76 | -----------------------------------+------------------------+-------+ Asynchronous Control Signals Information: ---------------------------------------- No asynchronous control signals found in this design Timing Summary: --------------- Speed Grade: -3 Minimum period: 4.772ns (Maximum Frequency: 209.558MHz) Minimum input arrival time before clock: 5.055ns Maximum output required time after clock: 5.887ns Maximum combinational path delay: No path found Timing Details: --------------- All values displayed in nanoseconds (ns) ========================================================================= Timing constraint: Default period analysis for Clock 'clk' Clock period: 4.772ns (frequency: 209.558MHz) Total number of paths / destination ports: 2791 / 156 ------------------------------------------------------------------------- Delay: 4.772ns (Levels of Logic = 3) Source: pop_control/preg/q_7 (FF) Destination: hmem/Mram_mem_array1 (RAM) Source Clock: clk rising Destination Clock: clk rising Data Path: pop_control/preg/q_7 to hmem/Mram_mem_array1 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDRE:C->Q 3 0.447 1.015 pop_control/preg/q_7 (pop_control/preg/q_7) LUT6:I0->O 2 0.203 0.845 pop_control/cltp1_SW3 (N43) LUT5:I2->O 18 0.205 1.050 pop_control/cltp21 (pop_control/cltp) LUT6:I5->O 8 0.205 0.802 mwen1 (mwen) RAM256X1S:WE 0.000 hmem/Mram_mem_array1 ---------------------------------------- Total 4.772ns (1.060ns logic, 3.712ns route) (22.2% logic, 77.8% route) ========================================================================= Timing constraint: Default OFFSET IN BEFORE for Clock 'clk' Total number of paths / destination ports: 205 / 88 ------------------------------------------------------------------------- Offset: 5.055ns (Levels of Logic = 5) Source: din<0> (PAD) Destination: push_control/state_FSM_FFd2 (FF) Destination Clock: clk rising Data Path: din<0> to push_control/state_FSM_FFd2 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:I->O 2 1.222 0.981 din_0_IBUF (din_0_IBUF) LUT6:I0->O 1 0.203 0.579 push_control/dinltp2 (push_control/dinltp1) MUXF7:S->O 9 0.148 0.830 push_control/dinltp1 (push_control/dinltp2) LUT5:I4->O 1 0.205 0.580 push_control/state_FSM_FFd2-In11 (push_control/state_FSM_FFd2-In1) LUT6:I5->O 1 0.205 0.000 push_control/state_FSM_FFd2-In6 (push_control/state_FSM_FFd2-In) FDR:D 0.102 push_control/state_FSM_FFd2 ---------------------------------------- Total 5.055ns (2.085ns logic, 2.970ns route) (41.2% logic, 58.8% route) ========================================================================= Timing constraint: Default OFFSET OUT AFTER for Clock 'clk' Total number of paths / destination ports: 19 / 10 ------------------------------------------------------------------------- Offset: 5.887ns (Levels of Logic = 3) Source: size_cntr/q_fb_2 (FF) Destination: valid (PAD) Source Clock: clk rising Data Path: size_cntr/q_fb_2 to valid Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDRE:C->Q 14 0.447 1.302 size_cntr/q_fb_2 (size_cntr/q_fb_2) LUT5:I0->O 1 0.203 0.580 valid1_SW0 (N01) LUT6:I5->O 1 0.205 0.579 valid1 (valid_OBUF) OBUF:I->O 2.571 valid_OBUF (valid) ---------------------------------------- Total 5.887ns (3.426ns logic, 2.461ns route) (58.2% logic, 41.8% route) ========================================================================= Cross Clock Domains Report: -------------------------- Clock to Setup on destination clock clk ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ clk | 4.772| | | | ---------------+---------+---------+---------+---------+ ========================================================================= Total REAL time to Xst completion: 10.00 secs Total CPU time to Xst completion: 9.20 secs --> Total memory usage is 282960 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 7 ( 0 filtered) Number of infos : 2 ( 0 filtered)
heap.v
`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 12:03:49 04/03/2017 // Design Name: // Module Name: heap // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module heap( input clk, input reset, input push, input pop, input [7:0] din, output [7:0] dout, output [7:0] size, output done, output valid ); wire [7:0] maddr; wire [7:0] mdin; wire [7:0] mdout; wire mren; wire mwen; wire [7:0] pushmaddr, popmaddr; wire [7:0] pushmdin, popmdin; wire [1:0] opsel; wire pushdone, popdone; wire sizeinc, sizedec; wire pushstart, popstart; reg done_int; reg pushworking, popworking; wire top; // size counter cntr8 size_cntr( .clk(clk), .reset(reset), .inc(sizeinc), .dec(sizedec), .q(size)); // memory mem256x8 hmem( .addr(maddr), .clk(clk), .din(mdin), .dout(mdout), .wen(mwen)); assign dout = mdout; // memory input muxes pe4_2 goenc( .I0(top), .I1(popworking), .I2(pushworking), .I3(1'b0), .Y(opsel), .V()); mux3_8bit hmaddr_mux( .I0(8'd1), .I1(popmaddr), .I2(pushmaddr), .S(opsel), .Y(maddr)); mux3_8bit hmdin_mux( .I0(8'd0), .I1(popmdin), .I2(pushmdin), .S(opsel), .Y(mdin)); assign mwen = pushmwen | popmwen; // control signal generation assign pushstart = push & (size < 8'b11111111); assign popstart = pop & (size != 8'b00000000); always @(posedge clk) begin if(reset == 1) begin pushworking <= 1'b0; popworking <= 1'b0; end else if(pushstart == 1) begin pushworking <= 1'b1; end else if(popstart == 1) begin popworking <= 1'b1; end else if(done_int == 1) begin pushworking <= 1'b0; popworking <= 1'b0; end end // delay done 1 cycle to match with when all values will be written // to memory. always @(posedge clk) begin done_int <= pushdone | popdone | (push & (size == 8'b11111111)) | (pop & (size == 8'b00000000)); end assign done = done_int; assign valid = (size != 8'd0) & ~pushworking & ~popworking ; assign top = ~pushworking & ~popworking; // Push controller ctrlpush push_control( .clk(clk), .reset(reset), .start(pushstart), .mdout(mdout), .size(size), .din(din), .sizeinc(sizeinc), .mwen(pushmwen), .maddr(pushmaddr), .mdin(pushmdin), .done(pushdone) ); // Pop controller ctrlpop pop_control( .clk(clk), .reset(reset), .start(popstart), .mdout(mdout), .size(size), .sizedec(sizedec), .mwen(popmwen), .maddr(popmaddr), .mdin(popmdin), .done(popdone) ); endmodule
heap.wcfg
CLK CLK RESET RESET done_flag done_flag TOP-LEVEL label DISP[7:0] DISP[7:0] UNSIGNEDDECRADIX BTNS[3:0] BTNS[3:0] HEXRADIX SWITCHES[7:0] SWITCHES[7:0] HEXRADIX PBLAZE label address[11:0] address[11:0] HEXRADIX instruction[17:0] instruction[17:0] HEXRADIX port_id[7:0] port_id[7:0] HEXRADIX out_port[7:0] out_port[7:0] HEXRADIX write_strobe write_strobe in_port[7:0] in_port[7:0] HEXRADIX HEAP-ENGINE label dout[7:0] dout[7:0] UNSIGNEDDECRADIX size[7:0] size[7:0] UNSIGNEDDECRADIX din[7:0] din[7:0] UNSIGNEDDECRADIX push push pop pop valid valid done done mydone mydone
heap.xst
set -tmpdir "xst/projnav.tmp" set -xsthdpdir "xst" run -ifn heap.prj -ofn heap -ofmt NGC -p xc6slx16-3-csg324 -top heap -opt_mode Speed -opt_level 1 -power NO -iuc NO -keep_hierarchy No -netlist_hierarchy As_Optimized -rtlview Yes -glob_opt AllClockNets -read_cores YES -write_timing_constraints NO -cross_clock_analysis NO -hierarchy_separator / -bus_delimiter <> -case Maintain -slice_utilization_ratio 100 -bram_utilization_ratio 100 -dsp_utilization_ratio 100 -lc Auto -reduce_control_sets Auto -fsm_extract YES -fsm_encoding Auto -safe_implementation No -fsm_style LUT -ram_extract Yes -ram_style Auto -rom_extract Yes -shreg_extract YES -rom_style Auto -auto_bram_packing NO -resource_sharing YES -async_to_sync NO -shreg_min_size 2 -use_dsp48 Auto -iobuf YES -max_fanout 100000 -bufg 16 -register_duplication YES -register_balancing No -optimize_primitives NO -use_clock_enable Auto -use_sync_set Auto -use_sync_reset Auto -iob Auto -equivalent_register_removal YES -slice_utilization_ratio_maxmargin 5
heap1_sol.gise
11.1
heap2.gise
11.1
heap2.xise
heap2_prog.psm
; $ python2.7 opbasm.py -i sqrt2_prog.psm -t ROM_form_S6_1K_5Aug11.vhd -6 ; btns[0] = PUSH ; btns[1] = POP ; btns[2] = TOP ; btns[3] = SIZE ; Inport addresses: ; 0x00 => {4'b0000,btns} ; 0x01 => switches[7:0] ; 0x02 => {7'b0000000,done} ; 0x03 => dout[7:0] ; 0x04 => size[7:0] ; Outport addresses: ; 0x01 => din[7:0] ; 0x02 => {4'b0000,size,top,pop,push} (operation start signals) ; 0x04 => acknowledge ; 0x08 => display[7:0] ; 0x10 => leds[7:0] load se, 00 ; load opcnt L1: add se, 01 ; increment opcnt output se, 10 ; output to leds L2: input s1, 00 ; read btns ; add your code here
heap2_prog.vhdl
-- ------------------------------------------------------------------------------------------- -- Copyright © 2010-2011, Xilinx, Inc. -- This file contains confidential and proprietary information of Xilinx, Inc. and is -- protected under U.S. and international copyright and other intellectual property laws. ------------------------------------------------------------------------------------------- -- -- Disclaimer: -- This disclaimer is not a license and does not grant any rights to the materials -- distributed herewith. Except as otherwise provided in a valid license issued to -- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE -- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY -- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, -- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, -- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable -- (whether in contract or tort, including negligence, or under any other theory -- of liability) for any loss or damage of any kind or nature related to, arising -- under or in connection with these materials, including for any direct, or any -- indirect, special, incidental, or consequential loss or damage (including loss -- of data, profits, goodwill, or any type of loss or damage suffered as a result -- of any action brought by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail-safe, or for use in any -- application requiring fail-safe performance, such as life-support or safety -- devices or systems, Class III medical devices, nuclear facilities, applications -- related to the deployment of airbags, or any other applications that could lead -- to death, personal injury, or severe property or environmental damage -- (individually and collectively, "Critical Applications"). Customer assumes the -- sole risk and liability of any use of Xilinx products in Critical Applications, -- subject only to applicable laws and regulations governing limitations on product -- liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. -- ------------------------------------------------------------------------------------------- -- -- -- Production definition of a 1K program for KCPSM6 in a Spartan-6 device using a -- RAMB18WER primitive. -- -- Note: The complete 12-bit address bus is connected to KCPSM6 to facilitate future code -- expansion with minimum changes being required to the hardware description. -- Only the lower 10-bits of the address are actually used for the 1K address range -- 000 to 3FF hex. -- -- Program defined by '{psmname}.psm'. -- -- Generated by KCPSM6 Assembler: 2017-04-17T11:37:58. -- -- Standard IEEE libraries -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- -- The Unisim Library is used to define Xilinx primitives. It is also used during -- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd -- library unisim; use unisim.vcomponents.all; -- -- entity heap2_prog is Port ( address : in std_logic_vector(11 downto 0); instruction : out std_logic_vector(17 downto 0); enable : in std_logic; clk : in std_logic); end heap2_prog; -- architecture low_level_definition of heap2_prog is -- signal address_a : std_logic_vector(13 downto 0); signal data_in_a : std_logic_vector(35 downto 0); signal data_out_a : std_logic_vector(35 downto 0); signal address_b : std_logic_vector(13 downto 0); signal data_in_b : std_logic_vector(35 downto 0); signal data_out_b : std_logic_vector(35 downto 0); signal enable_b : std_logic; signal clk_b : std_logic; signal we_b : std_logic_vector(3 downto 0); -- begin -- address_a <= address(9 downto 0) & "0000"; instruction <= data_out_a(33 downto 32) & data_out_a(15 downto 0); data_in_a <= "0000000000000000000000000000000000" & address(11 downto 10); -- address_b <= "00000000000000"; data_in_b <= "00" & data_out_b(33 downto 32) & "0000000000000000" & data_out_b(15 downto 0); enable_b <= '0'; we_b <= "0000"; clk_b <= '0'; -- -- -- kcpsm6_rom: RAMB16BWER generic map ( DATA_WIDTH_A => 18, DOA_REG => 0, EN_RSTRAM_A => FALSE, INIT_A => X"000000000", RST_PRIORITY_A => "CE", SRVAL_A => X"000000000", WRITE_MODE_A => "WRITE_FIRST", DATA_WIDTH_B => 18, DOB_REG => 0, EN_RSTRAM_B => FALSE, INIT_B => X"000000000", RST_PRIORITY_B => "CE", SRVAL_B => X"000000000", WRITE_MODE_B => "WRITE_FIRST", RSTTYPE => "SYNC", INIT_FILE => "NONE", SIM_COLLISION_CHECK => "ALL", SIM_DEVICE => "SPARTAN6", INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_00 => X"00000000000000000000000000000000000000000000B48B4A0C230A30A30D24", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000") port map( ADDRA => address_a, ENA => enable, CLKA => clk, DOA => data_out_a(31 downto 0), DOPA => data_out_a(35 downto 32), DIA => data_in_a(31 downto 0), DIPA => data_in_a(35 downto 32), WEA => "0000", REGCEA => '0', RSTA => '0', ADDRB => address_b, ENB => enable_b, CLKB => clk_b, DOB => data_out_b(31 downto 0), DOPB => data_out_b(35 downto 32), DIB => data_in_b(31 downto 0), DIPB => data_in_b(35 downto 32), WEB => we_b, REGCEB => '0', RSTB => '0'); -- -- end low_level_definition; -- ------------------------------------------------------------------------------------ -- -- END OF FILE heap2_prog.vhd -- ------------------------------------------------------------------------------------
heap2_sol.gise
11.1
heap2_top_bitgen.xwbt
INTSTYLE=ise INFILE=C:\Users\Mark\Dropbox\EE209\Lab\heap2_sol\heap2_top.ncd OUTFILE=C:\Users\Mark\Dropbox\EE209\Lab\heap2_sol\heap2_top.bit FAMILY=Spartan6 PART=xc6slx16-3csg324 WORKINGDIR=C:\Users\Mark\Dropbox\EE209\Lab\heap2_sol LICENSE=WebPack USER_INFO=174127445_174127446_210604357_969
heap2_top_guide.ncd
XILINX-XDB 0.1 STUB 0.1 ASCII XILINX-XDM V1.6 ###5840:XlxV32DM 3fe5 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pjCJFSaxwiRWmMQKk1hhJ1Y4iRUmscLhoxgOr0kOY/k2autuAmt3dTfRC2k0y8dErt7VSNhGwjESjpGwjHLbKHeMcscot4wK26hwjArHyJQ4gRLlW7yWKiu+2g0T9dhRv9hotvzKbPmV2fIrs+VB7FZhZdO2cvb/yuz/lcPgytr/K7P/V2b/r8z+X5n9D6IJK+ywwgkrTFjhhBVW2NyEzU3Y3ITNTdjchM3tsLkTNjdhcydsboUtTNjChC1M2MKELUzYwg5bOGELE7ZwwsI+SLIF3BssB1MOl795nC2+rl/2TdQJqBNwJ5BOoJ3AOoHvs+X1CC8PzU9Kb4+g6hRN3yJww1DO4fKrYXmBVYdOuIl4cjH56rANTOByYemLWaluhJbt4b2azKDGaqm9LJ1T/7I7XqsExpVYkOzzAMkGy4bIhsqGyYbLJpZNgrPPJYWPfIMTWqRarFoiW6FwoXChcEFQtlpnq+KD5mWRKBkYyDW6+DCYlS0q89koqUt2l60quGlb3a0K0Yv6qLdYPmhhsMirimer3aapdmC0+9aIw3F3OH4BFqQ2Wf/36fxpf5b/R91Bh6OBssd11hyjiKfN4fjnxpLlwyejdW+tZOsjHAZUh3SH38dZ+79ESpc/yOtjE6lXPZWIjIiNSJTIs812Bx53bd/eZ7sq0bNQOwu9714gUypuYdzCzFVjPYu0s0gLc1dNkJrW7Pbbe/U0RZYu35WQL8D4BrAfx4H5JIDTAM4CuHo9a3M4ymdDzfZ0/PP+FMljUoRgu3nwwHTkn878cCr/g+QWbja7XRQcCdswtM/+D1womFA=###2600:XlxV32DM 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YsTo+P9tLDFaIkZLytLdPZa+jdDzfYRWK1omEL1k566w801klut6rbhbr+W367XjKxj64Ne60+pnCbkau8/QNn5vtcvQ9Vvv9DD8DwZISnE=###5416:XlxV32DM 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12fceNrVW8uSpLgO/Zn5APyGJPpXOsIvInpzZ9HLifr3a9mWJVyQWdW5uHMXVYASZMnYOkeyeRx5/xXSY3mUQ26Hox7iUg5/Ka0fctv2ci1A/LdSIN8/ftu0lhP5zw8b3UMIu/+Efx+/nXBNblb1CKmIF1fE5jhQrB9Fyf4zqyLWUXItGbQcoMWYIldw+/oIeW/a4OdlBW2rpEaqNrEYUJcDqdOL3H/CP7h/GLU+lDzK/bIZu1IzcWnNxKrOw89WMSuObgU8vWz1aU9aQwRxVboIchWUZTDZBk+mKVfuzqJattDNoDrX3rKWdYtyRdzcsHjz9ohi/xlFfROGpKAi1B50mikuPZfBNrsourd2XNBVMVMBJpe/omJjzYGK8gf3cveKERn6wh6Z3Vtee/kDIySTFp/L38dvKVtXlP4KvcuLHx/BlqEnHuJ4FJ+Pf/6jdHpsUux/KeUfm9v/0osvnWH3v7OqQzRrHKKqOFeuDV0ruLZ07eDa0bWB65WuPVxvdK33/e+jDvVfh64jv4ywellecj+6fiQ1h9hBsPUfPP2g6w+BGjhAILoqcbQmZGzXMrdr1ZtQrIkVHlRk6hGqwPc7Qz9GusHVG1JTuYZ2DK0PRaje/SrzBI7BWlAEzS7/1I5XOezlVciHcCu8ivAI1rR3UWNHpDAR9x5LWNioQaVfp71Hl34NhvMwkzHM9OvyTka8CTZCHxhuWOyGSd8NW7phYlG8c3PvEtcimIvc46J5S5PLh0GX3Z3L56g5O/jcr3D2a5v8Oiz6Fd7zy8IPmmtOXXPOXbPU3a90fpXm2hOYFSV8Yr/52fID9ceu30fWb2nqqfwVoCkdNDWjlwU7KL7TQb9tjU4lvENPQfQHj2r0V7EG4YhB2LcgLGqwbH6DvJw08FFugI+G+9cKPj/g3fYTz+GovRnZGm5wtAaQx4VarBhRpmnFjoPur/ijQjUwkCEVHJWvbgkUJ4bA1h5MPEDM2IFLW/dS5tpmJnmzRcaqJpEaCP8QxKFTNmYLNKq2gU29T4AgtGbaiee8wQ7IAx+hOVVhc4vUHEN6QkgwYyB24xOjvYztZWxvMAxjV9Ydg1nYMF762tw+lmodumc9oy9miEHJYABmvF+wAvr00CcKUJQQcoZEUui5bGqDmUkHfI8haT2nFoHdixzCuoVJgW/oir2hY69KfcA37PUrYK94qPIPsVd27F0Z9na8oMmsUjjFeZWXU5xXKZ3ivErxFA9VgjiPkN4AjyOznpC5oNmExRxRF8L4Y9nP6JzzQOcTKnfo5OhcTC5dAgLLEUdgfMPI7Nx1fAsT9OUJ+tIEffEp9PltCuQDkzNC37owQz4Hbj/pT2f99wBoX2B+mDA/To77yfGMjp/t2XaeWmicPp4HMOcXJh6TzWqcVX6jWeW8YVKcKYPRggrG80eQ8adY4JmYxR6rFbt9RFLrmSEUI6zKrM0RMJ3HaV+G2SDM1igmRcrtSHNgvF8fTIqkvQ0W1IDZgOWtEe+HWT9MxsjxEZxeSjCQ7rGVfxgMVA8G20UwiNPkT+fJzoJDSlNw2Kbg4KfgAGQpixYVKm6f2H8n/Tdc/xxIDAaSoqLx7WcE/y6oiCmo9CizzVHGn4JJjy7fofzbTOA5wz9R/zgnB9T9BwSSO65vopm5Pga4hHHFiut5n1/M+5nrb/vzgHTixE7bmetLpHz6LU5sop5j+oYub12z8BMnvuT66zVDtpwhu8qtLgO3k721sD0N3OGCEbsaH69TIfVe91QLLpEg2RcjYkaCNI2IOI0Iv7/m/k6vt8mRfNPTPA2Ekbwkg+C+XoP7tp+LZTeYPg/xeB7i221WI97KagzyPmiCpS1OC5Kz5KKlLQbktmUrML76yYon2yl/iVgYKhFkoBSVgEA6EC1z6cAjxzRQwWmUi+BeLBfZiDWr0tuEzk4lFOeGqypV7n2gm+spnxEHaeGJBOZcoIZlc84IklNyZUIiNQzNR80PbCTKMopwIKYKoWW6WcIpM2ty5FBOMY9YJtZynf7iaooDL66frHiyncqqlSuNRyw+YvERi49QXsZd4KXRldk6UlJ7GOYwVUp1z1DcKX0CntHfN6tRGkx9qm0je3KKiSkzczoyHZg+GcU1Y/JD9dxYi63VHFZ0TdiA5UVXGuy6Jev5XKGOtcpbdRHRVJF0UbXXSkEDnJVfxwiH2YD8TsqmAwht014zNZgkJVOLJXiIhORMd3IWiZzdYlfnZMeZs3EOFiYOlgYHG+TrG6VWv9/wMCrdfo17dSL1Ne7FKddxT63yoFYnBsU41jZzLD9zLOgu5FTOqRtOJWXqcV1/qZgY7zKnmRlcpXQtkuoLBiXFDUV4BZguzcwpoEbkZJt4AZg35PCVayfkNDUtv+QoMX6To2xf5SifqYmpOdklgYjhBYHIL5Lk8KI6wF81rXnBO2cgTYHR8+qgwfzQ9Fyy1+9sZGIK88qSEgay0jDdVO0bC2KYZfaEOTA5y68HNeipas+jDy6mFUTP/OFlV1xCrIGRYZ0zTA1hr2GmE/Y2aECPqMTqkDW4ROjikL1AkxTd29yv4rYq2UxqdMJJ+m3QoFUopn4AkcskJbT0mdkyCh0eOxEUDyZl3MYUI7KuCD/VCORtq5RMLyKYcZHpRUxaBXeDlvkWJu28rQShMivEowyVtfxDpDIdqdIflhG+Vz1It9UDM60d2gnQ3ARoT9YKzf7/U0rwM97lGe/cjHfbjHfrs5pCcLc1BfmnNYXvlRLOQKjlbSlhfTODtDeAKJJ4AQBztWR7UR7Oz6sl6rYc4N50Ud2WA5b/STlA35YD7Jueyls0P775MvOL0ld4Vut32tzWBcx7q52Ump02sSiHmYriC16U5/KNN0QqyugfuEKYWqSUA41sPjiWzXMp4VVYSQNLEAcqQ3OfdsfA5GaJmmWesFU3kahBVvoe5CM4tmuG8nh1nccrvs7XF9OaeWPpLhxM86jhK8/6CNHbBMN6Y1T2D27bQFnF3Gasg3J6iRm8whONJ4bn9CYMdySnUlZEcpPXSALrFcYZ3cLEV6UByagUK6hIzkflxsSDSrLihsRShsITjSfmRPjUhv2jT3USKnBJLGcpPNF4Yk7cWSGnLnJWK2OFG8nJo2Ie81IU08IqcWPVuHoySlQlCpXxVAiTBMIkkTDZTpjyBWE6ppz9j5iQntZazZSq24kpPWFGipZY7gjRm+n8H+2e2mYy8yzfDy/zffeE/7jlmBPvsWgs7tZqb9K+p8TGKHFDbMx7SyROqLsdYHbsALPXoO/358vg8QXPuQJ9o+QNvTHqTUfFjPnIbrJ8sb7/3cLBFW8zSt2wGfPe2oYz6x2ZsfGbGxf8NzcubGcP9Q2ZMe+tcVB5tbxDhjzLQWJOcRIT0yZiLLdX8cB6ysmV5OVnoelujo1ypduJPxnJ2mTrBCN/ForvI5KOxIPnEDUTipGtQQOEYkQCKzJVSmXolWkY5QuB6fpy8Co0shkQEzOTWAEqAYexDqQzcDOjT5mp+FQ0ABWMryHyV+OwRm8k8iSlTihekcR0JUBq6vtpJwpPNKc5A/jhkQrz8Eg/UXiiT8BvsMvLHGLMyEhkRkqfCAGuYMD9RGpoycasjCeswpAWvjSHQ65qoeKT5FqIVije5mBMKw7Q2h208DWYVOu4jB2XseMydhwyqRJBGvsHMoI0xHUacjAaQgh73nFQnq/j4CICSY2JWmLp1F2x97fDNMRNq3OYhzi++PcRgDmLR3qoR0bD12a4X57zp/RiDaSyAFbO6dWbz3vAO63Z5sKPn3lOuGQvRCSWGyIhFcLDpq+JRPpOxmmPuzV/qRBgXbzG+7RfLl1sX61nn8zI825li+sL8k9WLCiXA9UskoxqJXhOyZwSGI5Kz7M8EXOxevfAFPpwBUYc21aKBeN6O2EN1mNBTHCgxMrupq26B1NSC8m1FbbLuDfMIteKtffawoBEKtgWr6juPArBRTpCPZWSQdqj90fQea1zypV+x0m1tUmlNF9vPK8ojmxjzhcuv7JgGcLaj9s8pfycGNzVQet1kHVnvbqaQRpLKcldz6BMM6SPVOiHdLOmJkaZzX6dzXwUA/1sIDLtweE3+2SK301pnee5NCqCf1LzBIVzVnOg67hraukF/ZJQfcXzMOtT6DniA2xlGtuwPleB9RRTDN94pT/lDIPaD24deDnvG1Xm09Jbn3PQ4cT91Hqg+Kiz9gf4C1sH4JFIv/Wg1LjK1rYTwK2wnQBcYPvac2cOMGYG6dN5JemgjTo7bCIxxqZVJxmgmRFYtSpU0rat1uf42ppuqipTAE/7ycHjnq5lgm4/fLAHrVD8U2siS3sjFNE0GTBClK757WjaYtMWm55oHjZ99KZHpJadibevzWq31rAG20z612a4OrXqThYUzo5ycrVEf96qhwOjF1audqaeN6RO+1B7keTmy7L5g7LbwIeFj/65GBY+7j4OG9+EYQ0jmDqcBadtcW3TRqkxzwMGjuU7XTNs1AufQ7+06PUTYfrR9qPrx7Uft370/Rj6sYcUU0fB2fiIxvt/vfFxNj4taHz81xufPhmv0fj0rzd+hspk0fZhst5/+WaPl92Mdqk2h2pmgCzMoqvJ31BzzKQ/jQl4fFkN7aADfeXXvmXNVkJsi7hM9NKDJe8rk6afRDyp31bUIwjwMyyJSWR9NOKjER8dj8SxyJBx3SW3XQw/oJN8Xd+ob20YsqG2DbVtTVsJ1F3rhsmvFScfVnx0xUfX/uiCj66YfdsaTsejFh+1+Kjt7md81GI+Tzl0ho/IjvZoP4l4kupJB0QrTq15bM1jax5b8a1nyts771XF5vTSm2snEU9SPcE1hbGcBVREQceVd+/rbt0lcUscWlJO/gvrpbcu###5052:XlxV32DM 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HPMN1o0ICRmWPqYrGdQtB7v/B0eXy/g=###4988:XlxV32DM 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12f4eNrNW0mOJSkSvUwdwCemcPVVQmJyqTadi1ym8u4NmD0w9/D/I35XSZGLDPiGg02A2QMyvk1v+++fLoVScb/+48P6ts1xL5UNFYWKRsWgYlFxqPhWeZ9nXYa1YSnDLr/al/M2V3ps9BV0z/Q1F7q3CXT3ti5HodvQvp8Lff3VWM/bRBxr5X0OW+3otvJBgPwW8lvIbyG/hfwW8lsaLU7Qw5IeRPCNUOSLTb5jyL2ulf1qCt0cSbJXYK/AXoG9AnsF9orYhgT2itgSwTdCYeMKmy0uw0vzfBAbrihUNCoGFYuKQ8W3ynv9U6SPQUpvIL2B9AbSG0hvIL1h6Q9Ib1j6A9KbKn1obJxko8FGg40GGw02Gmw0s8lgo5lNBhtd2fjmi5M2G9hsYLOBzQY2G9hszKZP6Y3Z9Km9VTa2sbGYkitru9XyPVSTWp9HK09YRRP22NqEnjCRNC2ATCbqgyrWTdfyPevW6kUr+7qyzKYtgYAhDa+dpfU6ZC9ex6V8z7RwPHptNKPbejKHGguOZqKt5fs8NV7WoZciXrlpnezoRcvH1rL0Is84MSjPzCr/PLk2aBg2aaLktUm4DvlpUN0GzbYZ+hjyN0OmtpG4ODYeWqiTavQu+MqCT00yIyTLLFmuvcjXq2jmja+acJ7IwlFYOLGFi7GyakZRYyqQ/FuTPxJnLaZR5mlUOIfcWhfRyrtyZRxia91Ea+LWwrf8+/1z2WxT9T3OzHNuVDLAe3ZsSaLSLCgKBfYakatHdCGvvBlhrG12WEUOi8dhjRRn/g52W97mt8W+2fLn13/XLb0Zn/a/1tW/6VJuU9mDVrX/CFWJ/e8QqUhUZCqOVsSJirkVqbX9yBMVayNmGiUrKjQVhgpLhaMiUD8auplw/1FmR/tZHMql4dJy6bj0XAYqZ/5+jlweNN6iqVx5nJXHWXmclcdZeZyV+6+JS1JyttxOVgrOVjlr2/SrmXKNZi/GXd4WE/a/ctmqtmrj8BbKQm1GPo4vGZcl/7vsUY1zWRztd9nyuFRcai4Nl5bLxuN3EbF+ME9SRgsZ40VGyxNhml6ZAUPWmWRdpxdldVeZzdWsASK7JnLZir7brPaDWSNk9BcZ/xizuqtZD4hsmsh1V/5uu/qrXdMEIe1VyD/GsOFi2LRCZkUyl7z0uw0bPxh2g5D6KuSfYdiBg+pG2xBN3c64YlCxqDhUPCoBlXjCQZ7TkfqlxEE+gR7POEiBHk44yAeK+JV1SyvrB3c4iOS3kN9Cfgv5LeS3kN/SaHGCHpb0IEI84yAz5L7DQcRegb0CewX2CuwV2CtiW/MYYq+ILRHiLQ6qbBqiqWy4YlCxqDhUPCoBlXiLg0h6A+kNpDeQ3kB6A+kNS39AesPSH5D+Iw4iNhpsNNhosNFgo8FGM5sMNprZZLD5iIOIzQY2G9hsYLOBzQY2G7PpU3pjNn1qf8RBlU1gVwgcJFp5whqJg7zHRLJ3OKh+TbrZGxzUWtnXAgf1uelucVDrxetY4CCNXvoOB9XBaCb6Ew6a0cvc4aDai5aPv8NBbVCemRIHrcMmNzio8qJBrcRBbsgvcZAdG88JB/UNRt3hoCZZZsk+4qDWzBvfDQ5qFk5s4Q84qLIk+fUNDmrTKPM0+oCDWivvyh9xUGtN3DpwUBw4qPEkaJMGDmqWJGoWOKh5jciHwEFtT5yxnBxWkcPicVgjjINcxUE1tBVDAwgFBkJ5AKH/HwERMS//BAj9OCaBh/59HLQwfcn/Bh76MYf1jItocctMU1OuEQNSjMh5kK3iQQxDeYPhpMUb/Qhf2XTBLu578ipvzEN8ZfNFRv9n5Kve5Kt7HLvHQ9QNoq5P/OMo2siBPA9kX/OzfQT4bLiAqW/zs3sI+Gy8yPin+HlxV/ckdo95yc9WqetAmQYaOn/Nz/4RArXuCu6+zdHhIQK1/irkH+Jpq5eLg9LMDppf87S+Tpm00EDpeM3T8REktuaKNr/N0+khJLb2KuQf4+nr3p0UOyi94umf7sDlXokGhVrywppcqQlH9SZIbOybwJVeNpX2+VETRa9mvt4xuMMxuMMxuMMxuLsxHpWACqGYWjIhMSFJWEMQc55LUnlU2FhP5g1u1gxu1ooiramGJf4Gd20Gd22Lo6a6pfE3Ht8wDq2Lib7RDt9EfJPwDfFirOqVl2bQMIOGGTTMoGEGDTNoNkOGGTSbIcMMHUS6zLCiiticUDK5xl5J9grsFdgrsFdgr8BeMfsE9orZJ7DvQN97xReeBnfPBnfPBnfPBnfPxqMSUImoJHkcoyaNKef59GRpaEnjQsXw9a8JArd5vYzmwA4cuM0dAJ5lNtD8rp5yHYIdtLybMhVz1S5utFEXmuOrYMQaDZzlDtye10nWQbPrF4CFXLEezb12MOM1rpmMZc3cAI9emdFKbnADuLnM1qozmOeAbr2i6JW5F0C63/RY1k2aNstJGpWEfpn16zDTpr5RaHJPXmqvqEA2EuIqKwZLPFiH6AQ7F5JyHDz4bR1KsVc8e8WrSSjGU6yfFDjcmLZFTz0t/NmvF4uI5IK6RbALZjEqbxHj1EL1qadZCzMwrFdOtGZuBTr2eh2t5FwzkLVXWfTl7asf0PgGbdHKC6wjazVl6BNPx4x8t9gWFju367kZbBkO9omwT/ajjaZSO9dU8zTGk+eg+rTNWKx/i/Vvsf4t1r/F+rfEmOwRQUhMSPI40+UAsTgyFXzZTHdI9gbsDdgbsDdgb8Ce9SaDRxASE5I8EFzUJG5qq+/aoYOaxU1tXa5EXeRNbd2fiLzKm9qq5gxpHYR0kM1BBDqhWOsJRYnaZVUddEDhNhxQHDig0Oeb2r/WbSuZQNg5KaHfZffi7ITb3c5pCv9OO+cr/DvunLjwb7/z0QWPp3Y+w+Df286HGfzb7Hyqwb9bfzd+6x0nG5crXm4/dpxxEOGYdhx28Bd5x6kHE9J+d/zx7NqXh66ync87uMHsOPhggts/nIDg5CO49qTKiHQsc+LtgYC3ldPbLJ21uLOzFpdPzlrc2VmLOztrcWdnLa4ohPSyIPN2cqKlXIyoPRCbSUKudJErn8Z9Kke+yBHPclyRY2bUfLwGTJy7KnQAUBxAJktgjdLZ0vpiaXPRUF003KBhBxeVv7k4+lDgn5m/X77m6fiJhd1+gRHCnjpezZAghoYZ/L0ZzH6GLEJbyV3faa/TVXsA9wNYuOzkt9rHe7bX6R0eKv3TGaRyRgns4QxSOUOXBK2dr74yDrA13/roRMlh2+OdPkbXWFO2mjKa5EWnxJ0S0l+nOfxWsrhmcwZpo47yetCkTQwXebjYr2r6tYSjLKJOsZF2uYMfa9ZmeXGSJtEtcbeeYJk8CaaZmeZ+DZWFiu3YXyfKqVvoNSmLwQ8evOfUJkbRHLm5Z8KE0thPAh2ZvI1ujakzIpF3/fbDGXkrYqIZThr5r9kEFQmbSfi2bMgjFUOO2qhI33pC26j92iLbQa1TokVykxdB7UmcV2L6IG93OgjJkHm7MI8RxFXWSQjkf4va5I2H68mHYvLKs7KS623GXG8zpvqqa0KuEClXMNPzXMGfc4UUL7lCuuQK7pIrhL0v1Ju3XzJhUKcE4JRArJ8kEBsSiH4x8knecE4XSox5mC6cMozwhWdip2xAjGCv+ULo+cIp1bgkDo3HJs9xsKNmHOQU5H27kaubeCYjck2zxtbdlFA3GcqSIwKXTAXyOdTfBia5Z18j1JwuimW+XFhS/kQx/Yli6qRYSxXUTYqz9KOwR4p9llv5O8Wmq8d6BhKPryp2ZmNO+kxXR/UMI+Z/6Kh4o49tK2q7SyVqKL/X5+wfvT/Rx7ZMX93lDOH4RB//1dxXZAl25pPLqph8pbPwBlwFkq9jchz0kRrYBY+DJnuORoh9K1/4r1ZEBMSwylzE+ANBZbVjlzcZe/8kQ3d/Jd0+HpfteAqxiiMIu5gxhMwOch7Si8Ddk4k5jVBqIqL9xCpN8oH4eK0wnZ5fRz6jqKrWXtV+I4UYDz4mmRt4B53LspXPKJwQrD//8MuwhIiZSAiakXteZtdpjDGeffQ3JM2/IwOKfNpVv25KF4HG2Vs/TirU8cTl2AS1HxL5eXhmvNroL/+bw5BeLEqLdw8rXjgoI949VEGIamUWMPWPncgCmtU5C0j1xCDVE4OELIDfdtenfR+ygHQ5MciXE4OPFxkjZ+hR/klUvx4LqP3y2OFZMOeI/JVgflyCOUf38Dn4d/slqptrVPfXqG6fnQK0maDvTgFwf5SWr6Ht/MQBV4zvjmsA5Ei7TgvAdRYb+AsQ+BYE+uka2QP4AcwHJ9T8EroLtj35vY2rPnwSV819XN1Ocag56Tauev9iXA2XOOTu4mpb6bdx1R0vJkB3JxG27Rm3cdV9lifEiz7+CeiOE47ktQynLptBF+AY8KmKN6IpPQ4EuW/CLs6DLGNyjy2KkGJtF/D0wGinl24O/x+xroi2pftpbOn0ehECi9CM8G/lbQeBUR6rIWA/jS3fHZMQoEdu1x8Ul41AxKsOHgu5pwqum8QGmWC46MbYMqQjSlt6ttj6CfTcY6U7RPSjdIV597RhwORK7SlGx6KViizF+f7tJCI2xU/mN1KJjp6rqkDP7piFjcXVnBC5B9lFeREL/YSgF0QsbKoTOcpYqEyPhfEjIs4cC81Lp+eEgPMFIR9nBC0RsXuKiM+PAGXkfD1SPjwlvwTI/PFw/HlcDPvLaNd8Be3a9uLsFu32c/Kv7ol2f7bZm+MR2u2h+OXN8dlmb5ZHaNerT0DUzdZu1keQ1m8vSv8s4mr9MOIuX0N+5i4wafMw0M6PpP9qPCphb3kYVuMnU8jur+BWtT6Mr+FF3PoFHF6i14H49D8y6PiN###6800:XlxV32DM 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1a78eNrNW0uS5TiOvEwdQPxTEZZXSTPqZ9abqcUs0+ruQzjcJUWU9XTnqnuRSQUEEU6ABAGQL36keH3+DH37/Ot/1z1+LB/x149e0kdKy6SnZvRzfeibsSdnzyTXRvalTHrb90lPk97Oj335nO1l7c/5z942dRY/tt0665BxkTyZTcb8Z9QhEfVjO0yCAWpXfzGfk/kE8ynqCeb5z1CmpwsfbKzg3h70GNSygryrk4hOTh/SySHNTjCk+dGOEQ97fUu2vk4jd3x18as5VHw19Yev0o6vjtfgTBMLgO1VCGiFM2HM8QVscp8ZzC9NgHkD+awvJZveEga3l6cP6OK8AGR/2dfgJ4xqP2RHwm8O/8TgrvzAtI9O1+rxopoATKDb5tMyLhdT4aovg80hbaaWWLyLn3vg1Amguop/niuBONVnzVTdRqOAXBeS00GtT/JfW8/jI3zE+d8cV/z1PykfH23sn3+kND5a//wjL/NdKp//2Ewjszm8Ob250OyLNwHNgXd/nos3TjyjN9mb4k31pnnTvVm92fxzSPjzcgmXfz6nBdvGtrNd2Q62m7eB/GFn673Oec+W9OjDmguQLftL7C+xv0T+dLD1IU+n4e2WnL4B79abjddoyy9oNu31c+o6fhybqXr72JbddX11gycYGN6fqUHcX9uo9uJ899O8n9jz5x/TNcy5zv5W9nf9W6ajRv4RslttTkn8nUNmW9hWto1tZ3tDtA/D8sbYhbF8wzg4v5bld+bXgzU41rT8Jtb1K+bexnfzrDTPKqhZUNP/Y5/ew/eOBjtqv2Xntny38yYdRuhwOsD/sJ1b+Judd2FM3zD+t9i51+/mOWie8pt2Pr53dLKj9Ht2jt/tfEmHC3Ro8cN/2tDpu6GPRSDDd5D/LZZe4zcDHYEGCr9n6bJ+7yh6R9NSv2Xp/M3Sc6a4EtvpSkztP27p8jdLZ4G8voP8b7E0oqAvBio00PE7ln7HabOTZuGkBU4lMBK0dTBRz1Aw7F+i8+lUwH5ZADeKjWub7HOrnoP6/GEboj9Mp86HoIeoh6SHbGEfWhIKCQUE5gYZeUkIhrbM9vyEwKldF4gHGwhe2bbkPG0hTwvkmejJc4gniieRZ43kmYuBPFk8hTzlxKuf9pepYbzVUKWGKjVUqaFKDVVqqFTDKTVUquGUGqri8fUKNMKECCPMSA7iy1t8kfgi8UXii8QXiS8Uf0h8ofhD4ouShzFMzCoxu8TsErNLzC4xu8TcRr6Na+hDxZQbmnJT8dmyo2jZ3KjZs4/B7GMw+/CUa9T4vN5owHcap4xszgaf37BUViZrppzLG4OxjORL5lf4ic/x9BLEET3ZWgld8IOvmHODoP0hW17mcw/p9KhVPS4cWXjyqlHa89bNEJ5EdL0WjevQHKj4an99dfIrZWUjn8+ydjQ2yx1NOV7jOzm+O4ctgWknVpyZ54wgZ5EvH/YBo5X+6uxgZ3feXkIVjsU7uzLgHc+g3CrMT63H5TUwTrE7/R15e8zMLxd9mccD0Qfdxm2C8OqVLuJOV0fR1Kunj2L2cBcUhm+SfHvyrYoQo6bnLYxbX8WPUc7Xt3Rfd7Vj5Ov1lgvszovLcs+0zIWyuQ6K6IXjNPfk48xK0s2ZuX7yPd/b886nEqpAZRlPf74HJB/ZFzfTtf671n/X+u9a/13rv7tgn+xZhEJCAYFVkfVURWOOwmFtCaq73uKbxDeJbxLfJL5JPMfths4iFBIKCCxqxRqe6gNs5wWF+FQfsFydml7Vh3EXJeC5KqsPGGYQ2lUgV2FbBWG1CkWeOXj4KB/xo3h5Ys0XyxOryhP180/PtD3o+CNNI6eZWn+LPliS2OL1PR0/GHaHrKhuGtiDsOPdaVzr3akCrb9mf7aI86u/M6i/k/3NhN/7O7/293eQDInmJp/omq3/p5KVUWRIRvbpYq/v9ZTT0EflVVjKvT0fmZHto3uZxVoeE6O74Krfvqm+LFT9+DdVz7/3z7/boP8zGxSF6Kn/Cxvw7/b5xRjtnxnD0Zsxyr8wBv9+wX5ZZZOC29sqaRe5f9H7baxOY7WXsR6rdFqlva1S31bxSt78qLkH+zkfPn/YXynZlpZbFD0aPd70IHowerjpi+iL0RfRKyuI82HSsVVgy2SJ+ed8mCvUhkl6Fd0iNcxVpxfRLYSy6Uh6Ft0C3Cvf9CR6Mnq66VH0aPR404Po5kyucNMX0c2XXhpXiOxnPnz+sL843sRxzYc53tRvehW9Gr3e9CJ6MXq56bJLMruk2y7HSvoxPZv9JXoTvRm93XTJPUzuccs9JPcwucct95Dcw+Qej9wkejJ6uumaJ4fNk+PWw6F5ctg8OaTPsOzy6XMDtr9IDyoph6ln+0t06TmYnkO86Vn0bPR806vo1ej1pnfRu9H7TR+iD6MP0Tfh2QzPJjx1MMSqGbXHH2lJH4iVKgLZzjdzZ6pl+5jewtvVWwtq/cH2rrpV+/ZHtbhsMZbRPxDm1BSwx/0oqwXSc/tDr6e35zRBGe6vrZ1BKHAgfqqIyw59OvjpxU+zty7OHmaOQ2ib92as6LUQ4creT28tjgBkE2uIzxVibaEPiWXvhtA6V3suEjYoTGoo3rkxupDunfuh1hgoJvz60bbwMYNItLYi0dqYjteYzMWVdQPAFj0usnYmAG4v42sVI2rFldIKwZhM+77NwHsxEHPuoue25w+e3IyFCbM9wTx4mIEUH25EtJwNr4WnRc8Yb3AIDjlQ5MyuLKJ3UJeDwtRxVMNRWQhrrcHvpjMkATU3D+Qgt8rcXYqf3dZ0+kSw9qIBOIcgxi2w0szzi9LHYxLKwTHFQTlNcjbJ6ey/eOvGsQdMOJNo30zHg/G46E2ih4vGVIToIdEbhmhLbafoLtFDoinp5FBtnjiESsldAvWAFWYCTwncJBCTeyzPqjeNYRZZwhjhz1qb8fT00ThSmy0O0Wbrx2b2gIOyVMhRyFHEUcSxkWPTm01vuiidlNycd7bobbbOYQ/O0cmhT2ZY4YJ3Z7XJahx5pLs1BmvBgAf7NI+LHBc5LnFc5OiOx1pwdOLBAzhW15C14FipITw4h68E+NtI1yXfqVV9OyojwM6aWZh89iDnigdbb1hmtu7w5uLosPZXLjy8mVMAvdq0X+WYN1+RRrAFyd412TeOv+XFR3XKUpTrDmQS4ll9/LU7Z/Uv+kK9VJcaz3C3tPnBaXHQfsfzwhV3uUpDcCNY63+vnBycnDnff3Oy3JNzqE+qKYTEbzQZsyZj1pvE3pI4kjgiOSI5ojiiOFZyCOEqjlWIREmi5MBvAr+RgnIQBzWUpaF86M3Ob7kG8i6OXRyDHIMc0kimRiyHgqF8mdoRPv2C6d+cfk/wpDPLr8038DpDZ9ugjOC+9vINa+P+0qa+jYAucG9htRAjRN9dsNnNFpudtdxasHeFpwVf4CboU13eFI6x+cUK7DWLT2RMzo1hBXzd8B0GW84RfD+0DaYQnsUXPdrIQvpFD2d77I70byrKC6vW2n5iLcaIB/PhPVdyVHJUcVRyyC9D4OnbrnXu26+ZYznhwa3FJylmqnKnK8d8QOGuo+IeiqO1HdPA4rZF9mI4wGaBFepETM5RyVHFUckBsCsftBANLRZkc9TQN9DvRL3cqFc+wIPsDK4AH8WiHnEwujp8xCmcx43lRGuxBV68DBQ82DM7Yvc375NWjjtw3AfHXTTupnGvHPfBcReNu2ncGq4Nwoap4QHVLney0B/7MIdGd2ixWgiRLxYCS5yexQL2khZ/gP5Ql7pULps5mR0G+6uCnJOvcjsQaeMNsjaUp2cMZNqC0VnkhrZWaivQRy/UVpO2Bn3ywi7vyba7E8ThTGmWic2JhT6r93k7fi0djwTDB68kreYvLl/ZmNS2wgNXNPcqtYheg4Kfo7zio4UBrKJHdFXKPRSs6CPcLZbagojIQOwKpi1Whb+wB4vL/OFU9DqIpAvJKgCNgk9Fq6sHTh5Sl5dP6YpaN2KiczF1++QAqFFeET7GY5F+YBuFSEgMAJKSSxHcQUSH7+ewCJB1ItqZrdyAVgeC3MQA3R4EMT4KGoVT6OKC22VmxuInEwS/Qjaszn76EFyv9gC94uHWa/VIBsqK+W4xA5svPsMusyKGttTwEHQtbPd62ZNGE4KIHNKQldiDZSUm1uc3dWfxk+ssZtdVc2dncrExnKeU6s7cBWuN+IquLviuYqGuYXGbUVhfbJ4VexSocNAwxeOARMQsi7cQYEGLvbDtFr7UOrvu+tfMMS1gxBuLJAO7Orw1Jxn3Q12hBMa+K/vWVr5wK1/eJTfUbDQGlN3iyYNBC9BQdkNgZi6olMi92oI7U5O1Ps7KnA0PtlvEgxQ8oD5U/QwqFz8jLKX7fEEoWHwgKNjZgBJjQtT2AMF6L6rbRhb9ok8LPOB8t+CwzHZsAwe9WQQqaMsqjEMYBdbH4UGIYUQIPjFaMBIParA+OgcQQB0MY7ugNocKK13xbl0fgIrDERxwWWaNYHkh1C6oejBgDlWYkwLqTnVeVKdNNWCsmhfE5NbiIsr0WcB2ClsTtgE1xrcaT2Jrwiab2y7h2JqwDWKrVKO5aQuEfRmsT/TfHKPNftfjTqxNWFdi3Yl1F9ZVWFdgbS+smElnlZK6B3SV6nPQq0DrIe2cnycVerpCfb1xFRnmTsyHMB+cprswD2Lm9NR09YPoeKZndd1T209dcQNuOo+e/XASMZxil6j8pyuNGZ69OKdvW0hAcPjXrT6FPP0V5gQP2g8Gpew9jbu90xu/qX3pfDsNfrK6j/AryhPq2GeyshamXAtTLkFchrASo4fNNKznJP2+gT3U3Z3zMXXLS/TPXUBiNwpGcyQhihBI2LlT4ALt9YuFhqFCw+7FAofL9WbFAk8+mScB0iB+fzPUyXiCJJdMN+u53FAux8QMjne9dJUg7Y/pLLsaC+8gwDCXNNfJku7b7vUX4Vai6+omu0SPYoPsvtMx+sXsTC13mfxmvrPDcV8nF/OayVxlvyb7Ie04DuJKvs2j9EJd2WJ2VXXOoOgwPf07FkZC+PaQbVbapqigMzjYlZUB17MvSJ8tQytkl5FuyasbyRfTxl5Zn3ZjNRkLmsLxwj1hukANgqo+QhgJ82QTuCjRXaIHRZ8UXSWaEl1dqz5Zhfbg3IVqD0FZBWUjlMYpuwjKLihJUFZBUVFDkhz/+sxdoj0Yf+CiVM4mm/ejetL9qLyIkvWg60yGzx+6mJseRDGouARlUCOTfVAQxNmDiUdkUnQpC+FcYGnfHwplIcADRVBREMPDyQ4RSeMhZnWorxqZLaZ2Cu50XYwMnYeXu+pO5lLJU3Q3rNT7VdPDqodNIijUQm1CldDt0itpQ0KtbuL9RPaDyByKOrtEnMLDfjzBZArizE2YM3tG2ACjLFRLu24ry6a5ikcX2xZNiXxPgCGKJkAWs2Sh2hU07ZziX03/1/T7Fusocp24y98+/DbT9nKeXLx+pjN90Kaff1jpQOsQ+1gf0e+aWb3KXXhlZbGq5lZVhWOZObHMnFRmTu1VOfQfOF3bC81GF+n3S9breLZOf2eeL+AMjhEAjvfi8NKjpw+4fFN+eUGzKpAvfPAy5QqXh28OfMPMDVlBZjG06ZONnxR+ggQGoZ3EMBfxTpt7EHzS+Al8AX6toU9uQIMpRuYnlXXUBeMMGufyjBPhw/M7I/Mn2qWgAv8Vzx1Z3M69cec/tfMz2nFCFCHQx+++uzwX94zCqud5fbmDyoTX3lzL/YMz3A81B5u1Aa1yrItqw9rgF+6KPlcDA4qg+CcoSjgI4eAGpE0ra9PKdORWtO3aYIe25f3Lb5/S9ezCVGp9XrmA/eP1Y69bp1X7JIM9L/oljSOSEJ+B3b3lLzcbjVKo0+X+Edctp0kOS+XbITmNcg7JaZSj8Xz98ZdRGuWELz88S9dtb7fq/SNCnIvcQWb58us/c0Jd0c7Svvx8z95ZnuLv1i8/+UvnK/Dxn/3dv3Hk2Z9bqn350Zx16e5sZ77y/AQS73a9g1fZrqdLDc4dTjw5bmQ3C9MsLJuC9WlhFDKgrAxIGaQVY5DnxJNf7cxzdm4FcWeic3miowQHOcpOMyLROZmGB+Y3QTnZUE4Gv6QrtQC0CJDSLDgV3HTOzDCJ2Y+C6I6N1esVuAVH1pO1BM8jFxw0GDJyLi+5TZ0pJ03Q4/LKwViTgRrjmV9v6EzhZqNMhu4ifTPcaQhFji7L0TWXFMKmV+P1yn8m2bkpZT8f80SDEerGfdTnvbKWrMiPJzMes9G34IjGr1XDeSEQqorZqmK2qtPVxgefmo2etDFCbfKo7Yl7naM/x2M6LztXgdu1xzOwdjc2Pvx29gj6DSgCC50tBO71vrh119ljRIXLvuMem77ftEyTmCKF1AXrdaqg+EVbtLY4EUiiHFi57RRO9MICFCI656CDLLw3bS04LNQDhz14H5V9VPZR1UcVRyNHI0cTRxPHSo6VHKs4VnFs5NjIsYmD6RLOtrJHgc55kvMU50n/05rqeKjL7rw/khlHe8HWb1r4LY3qUS8qpjuPhVD/3hnG+l0DJ1iLaj7LGAhmcXDGy/U4QuChjr9gGQNBLjLKijT5RngQYRHCQYRFCBsRHkLIaxw4XqCfd4Q8zkb9Oy9koFEdUSOiQ4ia6uA8S/GIs+JSmZ1W4Txj18UM3nm6L0UVlr8vDoL1aKh96L5T8lM+P8/vOs/vnqP4mQktg9I1UxX0tYa7dYTds2Mc63cd6w8lLjIdE4/tTkCqEhCc6HY6Nb/EQvPCw5brei+wnQssf/4fu/OkFw==###7156:XlxV32DM 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8x+5fOug8hz/yOVbB3UVHWlTvWm+eRmrt9EFbljvnDWJJlfLvOC2u7fc9nDdRgYj5IYC8YTmVc3lq1nJUOfukU0iX7W1oV27x4oMpaE5K3d7s4X6l1OEC42S0aiBjWYNd1shwN/fd3sO3EKrjVdamz/6fMe8mvUKmorEvFYB2ZARlnmtUQMbqJsM+cVXdHxLxL0ghwU5tLp7TA6Lchi7B3JYkMPd76NP+VD2jY919HnyaHx844q5A/kaHT3uHqWjZNBRwu4xOkomHR9fBSbUpG9rT1lXO4TJ1zBWt3sMYw0fxnb0GcZGjDUcfZ6zGWc1s8+Mr3yhaThE6T/ZesRJhTc2vYvsOHdBZO4aVhcimUg1io6R8Kv07MrYHY5xpnsj2T1M7eVCV1umA3oCQP53dfbd1qeBt/mFxT38RhwY57++yb5gfRb6qo1atAsrsi98fYt9affpwa1fNFGrsAtnz0yMYTpjTi9RVaKZupKWjQp5WqIkc67wGncdZXfBenvLycL0G6NpRObqZbcxWpLkorLMcGBUZQm5cNi9h1mmo1xU9Rn3bBzHTZfDMc6ySxfNwEwcB8tUmDEPMx8owRxlMusepuJyN7rcDSrFIJnmJUvQs073QWkkn75cLHf2KGI2iAmISQhcnWt5Lks++fTlYpmzx5OQjrcvnbWgfAJzsdzZo5i5sziUT2Auljt7FDN3VovyCczFcmePYubO8lE+gblY7uxRzNxZT8qnLxfLnTVME9qtSF9vfwJvf/igo+Oxz8N7Jr3iGsmOLckhdyNi1PKXFne188LYBZEsPPpZeNqz8IBn4XmOamTS2kqgtHqk5b+iVasizHCXKk5H8TlKyVEYjjzbvZRePCZU9y5ceOmjjoWyU2X5fsCqNkYAqzfrmROuFOxCLirmZwtxQYZa7zXsdw7Xx6VKcgS+vXDY0naJF0GwZf3S3GitAMPKZLVsDFXIXBgNLYb/0PIiFwdUFR6wdmJFTY0q0LLXClas0cGiXuqxzMtyRclNyqFvIGCuB+av1JmY7WUMLmYUszQsLWKYWQqY6jG9Sjjx6K4rbdes45N+2tOy9NpmbSa2jpIGLYy76S1szka8UHa7QxW8ISEBJQ1RQPnqzrhnUX0RmHbALMDIxbnC6E3rzShd+6QoQi/17Cau8Cbu6NJ7tvuBnPUiT7rsIk9T0hmJFq0Ziv/huq6gNMeBQ509B8afMeIh2MD99EQ6RW7ynpuXwx0NNbzp4YWg1MGgFkeV/3nwUo6JbK11XKh1RI2jCjQ2FPz0vB9MCaQWEmhNUMS7An95K/OILDPVGiNn95vGfMq4hDAtG7a+coa2deYTMSsYYnZVYSIVcBBGX3OkZyPUQu8w+Gxs4YnfQpooMetrMAUw2b7qx1IaG52WG/WFV0+o6DEVM/Io3t427HeTr9R9teurfhPhBRpTu/ZX58b12JNaV5BvwOhu9xwPCdiVLo/qYmk7t6uVS+Swaxj0eVe2pJxSw3t74yX7Daq1BtnygwqKYlebL8ezMKLSEg9aYlZIGF4+fVDl8FBB5S1F8saXe88Dy37D6Iv2Qf3NlqC0VhYzRIzXe/B3uPxhhQYV5Q6e5Q4ez0d822UKmvSUxgaJ1qNPi+7OW/27bhArhLj7rozQoCn7csB8CupZfqeG7s6H8n14WDNoBP8DMg3NAjmaX403uLZ6YWJx+GohrU8nCLB8ICq73BnkWbWMRdkW/43dZQmly3998+jrX+Sue/5+dk3IR5huaK2uNf7mhrG9em0pGZ7sceuibpJvSh1BNOq55wES2dVtJo0rs18bxGTACzorUdFbvPsfIJKs9PiLh64BBTYbFqFfGutrik/cR7RktWpiRq3GUg9Rj1qNgsIPMd83a+2ksctjdMsMzzIO/9UOfdIyszLcBlHDPuz5iEpEK5uW31bhK920qDGNsEebGRzp2LjKd2xhl1rhUTIjptS4ALN9tZ4G0wrcE8vpZHfT5cBrM4cjo5Xo+QUKTP1ohahD0afuQmY+9OWUszdAdgUZa99d+oao8hpRaN9MqIY0PjlIhY+yOt6AaEMN582jmj0KaHgUYEY1tcPeBhSt6sp5nsfE2EmXGj2drJ09w3qMRs9DlQIndCmJsSZyZq8Y4v/A+J5V###3308:XlxV32DM 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f80eNq1m8ly48gRhl/GD1D7Al0m7Msc5uAJ2w9QqAKOE9EH+6Lod3cWSIlfktCI3bJbESCIv5bcMyvBDjnU4MMeYwze+mhM6GEPl6c1bHEPzgdf5LkXJMYSRtxjkbEuVrkGjXw4e2J+jv7+/Q830ljM4l//8MEtLu4v//bBLu7lXzJgSe3Ve9/eV+3X/fyx30HhXBf7drUveZk0hMf5p2MfKZd/epe7dc7317Mndoy+8L2Rb/enfL/JObzLedzxPZ7i+zb/5/h+pOPP9X2ZPTTfO/muP8B3fFvrU77dKd/n+nYf2Hn8kO/4hJ3Hdzu3V76zId/tJ/gOn/Dt5l5P8n0Z+0h5FIX9PN+X2Re+0xvflnwHzXf6xM5jecLO/dNW7s91/QULf6PxZt/Zkd+o+a1P8SvPBf2E6/A01+GUa/cFrt071/6Naw+u06a4LuNVPOIxikfZ7RYZwydR/NG6Mf9J605PraFHn3l3PckFt5X+PBdcZvfDR95tJkB6+S4XrOc58LLfRRPnVtOfsJr3VX7Cah4o+YTzG62wm0jO41PZ/7JffF/Nf8JzOuX5LCqmU56tiokPVHzC9TH7TUfvVU9Ownd441tHxZFfxfbakzTbH7T1+EO27u45/EHew01L3n5hJQd9f2TFPyIdHeU+sqwQ7ae15Xt+z7Rkoy25nMf99BYzLrt9EvHrHdfpw/hXP+C5nsT89BC3xge6rFc6kdvLjWdv7FNRP4Pnn/He/CHX6YOKxj+xgh79rB/kJ2P+g/VepFcpvbuoP85j34P0nor6+WkZ5g+4D1/iPoD798jfbtxbtz9VF9Yv+Uv9QX85O+nWJ72lvNVyM+td+F3J7/ZUXaj5dfGzk098muP4QYSwX+D5mH3l+lLZtJnd7euVVfleju+HDNr6cnu+4fmO5zueb7fna7w9XwOeY53V3Z53j3U6nieMt3gOOld/e25DuAF1J9CxQyFA1kCSjZSFIVABJALcg1RF7hEBJAOgAhgQSCVVYwWgZgwAA8AGXdRAIAPIBKDVSgZ3kFsbAXBeoT+XQFXxBLBHwR4ug9xSCTQAGwFsXlYC2GPAelyxmNEIwHxKJABDLIMAhFgyAShqkPNCqqAPb2BwORGAELMnALvKEIm3IDdXAtijWAKQbs4EIN0cCYCPDCFKQAWwE3AABgGIPa8EqHO4gb8qCg8gCkvV+RoW+zbUHA9oYaSvwrE7gT1ycfK6ZyKU9A6lJegmGEjBkttgPBcrRDqRRGTX3IWCRVYIOdBSuyEwtCwDLbSD21Ch2Z4JwKE6Ca8wxB4JkBpLAKx2T4C5A9oJjZtTng1m1SsB6LPDBSO9YF0JQCQrGIw0dus5xYHDFVKMhWa2ESDrUF28yh0PqOTEkVGbQ6TUBtdsIHx0ApBa2glUvXbuNP4K3nOvRHYicAvbLBF6MLNkHpZIJUKPYcrNI5ECMJ43tVojQs9ssO/iVQDoRAqRjYiSgSVCTqsnshMhBYF2ViORQKQSUVRDC4XeZx2BOx2XijRmDUfCWH0hAB4ojwbpkpYGHQ4+J/UUX0s3Gu3xIN8RfS1jMYVVE5fqdzN3ZYS3kdXQagoBp5eoEsXvHpCRyqn5fmRjauDI9X4kE0LkSPqXJ0DOEDKqpWUhGNYEF3KOACzbGQLtjsx0TzfrQWc59S6P1UxnhL3UfC/fTAcYHEnBrwQYHDYC9Ga4eWVwcrQLxiZHuxj3djHu6R4gz9Euxr1dDNiFo12Me/kO2IWjXfB44GgXg5zRLjbYhYNdNAvNOB4SLRnaCNCSOoE7ThvrUwddtkr6WQQ3+rbLsKm20k6Zyhozl5xRgCil+MYjsCdSeQimDTAWtn0nwoOwBQVwodWx0MDzgPGeB22Mh77XjPGwmJXR1o3CIzjcSI4cRFYiK5GNCFTeQyLCI32oRCDHHh0RyL43mjWjwTDUJFPZYLHqGLJHpQEz5A0eDRyj5MY87ww0sLH8dJTOxm6KY/LcGh2actuULVE6u6Wjdkh0L4xaIxNh0B+wj50VpGVhuFMGdoCfvalAS9qG2gc+uDOKWFa71npFAvslqmfhTFQQY4nJCmL1tLP7Y3eVTZqC1IJWQSzhdjZVHP3LMaBa1XZwTHJyPqC/sBawvkdCWUGFEIn3wxAqCvKEooJYu9HMbYjKo0lGSKRQKSUkUmhUey2TQqP2yqTQqDYeezresGsVVTTyFG8MDCBuVxCJ96rPFwYh1emLJJ75SCCGMWY7G9mj88yQNm6KwqogUsgsKRApZPlh464ozApSFFIpKSsKVUeyKAq9ghSFSUGKQuorVUWhVZCikErJlhQy4tvMNpJnwSeQotAoiBSy6LPZKydaFUQKWRHarGJrV5A6urCDYquqPDpl2NhEdWyW2JWhkmWEIMwku0KUSoh0xa9XEMsMnroEaoQUEUNpRO01VNBQBA4VDKmsrs7OSkp9ZXRVGhmsRtzggiMwrbK3J3mMEHOXHeyRuKHa8J1VJ9u4kkyZvFTr19CqbWCv2jgF7QpiXotsZBvVmAhsTJuVVUFQZHQFZQXxYBnYfzfUsiQKQFbVxkNDNNDBTr/rrMPYh3MqodhQFETbCE1BlGF0hDLP72FTEPmKRkGKDL7YCHwjYIMivigKyXIMql3EWTFyQZ8VxFCTFTRUZ5haVrnGstkvEPdiK97FnVUZ2/euqPN01G9ByHIsClLEUymFr1tsDgoihVG9o2Ej28auIHoKu+6uMA3ZTC2XjWbDUOlWq7om3GtlGrIpKYgUJrUg05BNQUGKeMpwZYayqSmIFhU3BVEp6cby9//8012yl/yZ139YIcrJwVDqIuHf97TaGT9zffnVlf3lm6vuZQ19zNGLuPPrr67al7+40pdte1mTP9aZf2+ICLtt7yO+r2EPZ0MGh8R2NmTFkNk4PRlSOSTksyFNDaknQ1aPIa2fDWmB5DZ/NqRgSPSnq3QMSe10yH4bMv/98svfXv2MzM1El4ft8uSvrza+iq4OLc7IKiu5Xc4o37yXaQKVi4Lj4rZiBOvHZY6SaO32sUs+NnZO2uYlza9xXsK81HnJ80dDdl7MvEzU+nkZ89Lnj2IOdC4lxex16+Dm1m4p8je7jmLWs8coC5nZOpIVjJQPfwmuzbfk31+vr0qXo1Fgl31a3cDzuW2fr3bCMmpeNvm0Jvr7YWIcMs4vPY1lSKIdm102MfjdtGUXEvc2ln0rMtd0uczWr5HTtpXcKBcpYOW8JxfnZHknVYakHVk2SxklBV2bsTDOkF1nm7/P7nyaLxb8fFchM9qQyzqbwes2axYjc7tERSkHZMvNyOBNxCaZUsZtc/ltzt2ny+1yspL02mcDo86OhJlNjjzPlQK4FOQiVYokzH1x852o80VU6FdB/ZAZXk4Bbr6Ec0HSrYspyaXMhmSVr1WU6Sa5rs7Bq/Dr1pjv5TeV3cM8Ui3RCYNjsjCiMD3k4O+EwweJzxminXAcjs/AtAQ73yene3RajNSa6ypymT+wsX4zsyISCcU4L1MVqcplvZzYj67LPv8Dyrq4JL7gcp1RKzwsfZhRWaI42hlSF9HhPTKNX+pbO73P9iB3fUxlJbGPrZrThVYxhDW+QZeXtyKnQ3jGTfsW7Ztt3gij9eW34ITZ19/kMOdfv2395Y8wjyvyMaP79HRZJByL+CmyJc8T4cNC6bKQ+3ihc8Bed4jHDmFqTczJzmrqYY982cP/xB7ngLtufvyoVqQ93aisbqm2LVUMtc4q8YGMeCEj/i/JOAf8R0C4Ep6vepnmHOavnh6IXb+ol3LVywxC4q2Ln4ePh13K/0sz9Wq90/0ft21PWK8kpb+//i56NC+/i5vYl28z6hv5sMc3cRmzlOOzS5Cfn+PyOcx0muPusPzjLk77P+7KPPLOmzZ/lTFv+rTb424/vFnuJNiLQR13fprVcRencR13eZrYcdemDo+7PjV53O1HAJM7yQci++POTw0cd+loMwl7/wW7eU9S
heap2_top_summary.html
| heap2_top Project Status | |||
| Project File: | heap2.xise | Parser Errors: | No Errors |
| Module Name: | heap2_top | Implementation State: | New |
| Target Device: | xc6slx16-3csg324 |
| |
| Product Version: | ISE 14.7 |
| |
| Design Goal: | Balanced |
| |
| Design Strategy: | Xilinx Default (unlocked) |
| |
| Environment: |
|
| Detailed Reports | [-] | ||||
| Report Name | Status | Generated | Errors | Warnings | Infos |
| Synthesis Report | |||||
| Translation Report | |||||
| Map Report | |||||
| Place and Route Report | |||||
| Power Report | |||||
| Post-PAR Static Timing Report | |||||
| Bitgen Report |
| Secondary Reports | [-] | |
| Report Name | Status | Generated |
heap_envsettings.html
System Settings| Environment Settings | ||||
| Environment Variable | xst | ngdbuild | map | par |
| PATHEXT | .COM; .EXE; .BAT; .CMD; .VBS; .VBE; .JS; .JSE; .WSF; .WSH; .MSC | < data not available > | < data not available > | < data not available > |
| Path | C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64; C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64; C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64; C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64; C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav; C:\Xilinx\14.7\ISE_DS\PlanAhead\bin; C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64; C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64; C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin; C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin; C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin; C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin; C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin; C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin; C:\Xilinx\14.7\ISE_DS\common\bin\nt64; C:\Xilinx\14.7\ISE_DS\common\lib\nt64; C:\Xilinx\14.7\ISE_DS\EDK\microblaze\nt\bin; C:\ProgramData\Oracle\Java\javapath; C:\Windows\system32; C:\Windows; C:\Windows\System32\Wbem; C:\Windows\System32\WindowsPowerShell\v1.0\; C:\Program Files (x86)\ATI Technologies\ATI.ACE\Core-Static; C:\Program Files (x86)\PuTTY\; C:\Program Files (x86)\MiKTeX 2.9\miktex\bin\; c:\Program Files (x86)\Notepad++; C:\Program Files\MATLAB\R2016a\bin; %SystemRoot%\system32; %SystemRoot%; %SystemRoot%\System32\Wbem; %SYSTEMROOT%\System32\WindowsPowerShell\v1.0\; C:\Program Files (x86)\Microsoft VS Code\bin; C:\modeltech64_10.4a\win64; %USERPROFILE%\AppData\Local\Microsoft\WindowsApps | < data not available > | < data not available > | < data not available > |
| XILINX | C:\Xilinx\14.7\ISE_DS\ISE\ | < data not available > | < data not available > | < data not available > |
| XILINX_DSP | C:\Xilinx\14.7\ISE_DS\ISE | < data not available > | < data not available > | < data not available > |
| XILINX_EDK | C:\Xilinx\14.7\ISE_DS\EDK | < data not available > | < data not available > | < data not available > |
| XILINX_PLANAHEAD | C:\Xilinx\14.7\ISE_DS\PlanAhead | < data not available > | < data not available > | < data not available > |
| Synthesis Property Settings | |||
| Switch Name | Property Name | Value | Default Value |
| -ifn | heap.prj | ||
| -ofn | heap | ||
| -ofmt | NGC | NGC | |
| -p | xc6slx16-3-csg324 | ||
| -top | heap | ||
| -opt_mode | Optimization Goal | Speed | Speed |
| -opt_level | Optimization Effort | 1 | 1 |
| -power | Power Reduction | NO | No |
| -iuc | Use synthesis Constraints File | NO | No |
| -keep_hierarchy | Keep Hierarchy | No | No |
| -netlist_hierarchy | Netlist Hierarchy | As_Optimized | As_Optimized |
| -rtlview | Generate RTL Schematic | Yes | No |
| -glob_opt | Global Optimization Goal | AllClockNets | AllClockNets |
| -read_cores | Read Cores | YES | Yes |
| -write_timing_constraints | Write Timing Constraints | NO | No |
| -cross_clock_analysis | Cross Clock Analysis | NO | No |
| -bus_delimiter | Bus Delimiter | <> | <> |
| -slice_utilization_ratio | Slice Utilization Ratio | 100 | 100 |
| -bram_utilization_ratio | BRAM Utilization Ratio | 100 | 100 |
| -dsp_utilization_ratio | DSP Utilization Ratio | 100 | 100 |
| -reduce_control_sets | Auto | Auto | |
| -fsm_extract | YES | Yes | |
| -fsm_encoding | Auto | Auto | |
| -safe_implementation | No | No | |
| -fsm_style | LUT | LUT | |
| -ram_extract | Yes | Yes | |
| -ram_style | Auto | Auto | |
| -rom_extract | Yes | Yes | |
| -shreg_extract | YES | Yes | |
| -rom_style | Auto | Auto | |
| -auto_bram_packing | NO | No | |
| -resource_sharing | YES | Yes | |
| -async_to_sync | NO | No | |
| -use_dsp48 | Auto | Auto | |
| -iobuf | YES | Yes | |
| -max_fanout | 100000 | 100000 | |
| -bufg | 16 | 16 | |
| -register_duplication | YES | Yes | |
| -register_balancing | No | No | |
| -optimize_primitives | NO | No | |
| -use_clock_enable | Auto | Auto | |
| -use_sync_set | Auto | Auto | |
| -use_sync_reset | Auto | Auto | |
| -iob | Auto | Auto | |
| -equivalent_register_removal | YES | Yes | |
| -slice_utilization_ratio_maxmargin | 5 | 0 |
| Operating System Information | ||||
| Operating System Information | xst | ngdbuild | map | par |
| CPU Architecture/Speed | Intel(R) Core(TM) i5-6600 CPU @ 3.30GHz/3312 MHz | < data not available > | < data not available > | < data not available > |
| Host | DESKTOP-VFMPJUQ | < data not available > | < data not available > | < data not available > |
| OS Name | Microsoft , 64-bit | < data not available > | < data not available > | < data not available > |
| OS Release | major release (build 9200) | < data not available > | < data not available > | < data not available > |
heap_isim_beh.exe
heap_soc.v
module heap_soc( input clk, input reset, input [3:0] btns, input [7:0] switches, output [7:0] leds, output [7:0] disp ); // btns mapping => btns[3:0] = {size, top, pop, push} wire interrupt; //See note above wire kcpsm6_sleep; //See note above wire kcpsm6_reset; //See note above // Generic KCPSM6 I/O wire [11:0] address; wire [17:0] instruction; wire [7:0] port_id, out_port, in_port; wire write_strobe, k_write_strobe, read_strobe, interrupt_ack, bram_enable; // // Some additional signals are required if your system also needs to reset KCPSM6. // wire cpu_reset; wire rdl; // // When interrupt is to be used then the recommended circuit included below requires // the following signal to represent the request made from your system. // wire int_request; // Heap engine signals wire [7:0] dout; wire [7:0] size; wire [7:0] din; wire push, pop, valid, done, ack; ///////////////////////////////////////////////////////////////////////////////////////// // Add your own declarations here ///////////////////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////////////////// // Complete: Instantiate KCPSM6 and connect to Program Memory ///////////////////////////////////////////////////////////////////////////////////////// // // The KCPSM6 parameters can be defined as required but the default values are shown below // and these would be adequate for most designs. // kcpsm6 #( .interrupt_vector (12'h3FF), .scratch_pad_memory_size(64), .hwbuild (8'h00)) processor ( .address (address), .instruction (instruction), .bram_enable (bram_enable), .port_id (port_id), .write_strobe (write_strobe), .k_write_strobe (k_write_strobe), .out_port (out_port), .read_strobe (read_strobe), .in_port (in_port), .interrupt (interrupt), .interrupt_ack (interrupt_ack), .reset (kcpsm6_reset), .sleep (kcpsm6_sleep), .clk (clk)); assign kcpsm6_reset = reset; assign kcpsm6_sleep = 1'b0; assign interrupt = 1'b0; // Using non-JTAG, simplified memory heap2_prog program_rom ( //Name to match your PSM file .enable (bram_enable), .address (address), .instruction (instruction), .clk (clk)); heap heap_eng( .clk(clk), .reset(reset), .push(push), .pop(pop), .din(din), .dout(dout), .size(size), .done(done), .valid(valid)); ///////////////////////////////////////////////////////////////////////////////////////// // Add all of your logic below this point ///////////////////////////////////////////////////////////////////////////////////////// endmodule
heap_soc_summary.html
| heap Project Status (04/12/2017 - 13:36:27) | |||
| Project File: | heap2_sol.xise | Parser Errors: | No Errors |
| Module Name: | heap_soc | Implementation State: | Programming File Not Generated |
| Target Device: | xc6slx16-3csg324 |
| |
| Product Version: | ISE 14.7 |
| |
| Design Goal: | Balanced |
| |
| Design Strategy: | Xilinx Default (unlocked) |
| |
| Environment: |
|
| Detailed Reports | [-] | ||||
| Report Name | Status | Generated | Errors | Warnings | Infos |
| Synthesis Report | |||||
| Translation Report | |||||
| Map Report | |||||
| Place and Route Report | |||||
| CPLD Fitter Report (Text) | |||||
| Power Report | |||||
| Post-PAR Static Timing Report | |||||
| Bitgen Report |
| Secondary Reports | [-] | |
| Report Name | Status | Generated |
| ISIM Simulator Log | Out of Date | Wed Apr 12 11:38:05 2017 |
| WebTalk Report | Current | Wed Apr 12 13:36:24 2017 |
| WebTalk Log File | Current | Wed Apr 12 13:36:27 2017 |
heap_soc_tb.v
// Verilog test fixture created from schematic C:\Users\Mark\Dropbox\EE209\Lab\sqrt2\sqrt_sys.sch - Wed Nov 25 15:46:16 2015 `timescale 1ns / 1ps module heap_soc_tb(); // Inputs reg [3:0] BTNS; reg [7:0] SWITCHES; reg CLK; reg RESET; // Output wire [7:0] DISP; wire [7:0] LEDS; // Bidirs task do_pblaze_push; input [7:0] val; begin BTNS[0] = 1; SWITCHES = val; #260; // leave enough to time for Picoblaze to poll and see this input BTNS[0] = 0; for(i=0; i < 80; i=i+1) begin wait(CLK == 0); wait(CLK == 1); end #5; end endtask task do_pblaze_pop; begin BTNS[1] = 1; #260; // leave enough to time for Picoblaze to poll and see this input BTNS[1] = 0; for(i=0; i < 80; i=i+1) begin wait(CLK == 0); wait(CLK == 1); end #5; end endtask task do_pblaze_top; begin BTNS[2] = 1; #260; // leave enough to time for Picoblaze to poll and see this input BTNS[2] = 0; for(i=0; i < 32; i=i+1) begin wait(CLK == 0); wait(CLK == 1); end #5; end endtask task do_pblaze_size; begin BTNS[3] = 1; #260; // leave enough to time for Picoblaze to poll and see this input BTNS[3] = 0; for(i=0; i < 32; i=i+1) begin wait(CLK == 0); wait(CLK == 1); end #5; end endtask // UUT instantiation heap_soc UUT ( .clk(CLK), .reset(RESET), .btns(BTNS), .switches(SWITCHES), .leds(LEDS), .disp(DISP) ); integer i; // Initialize Inputs always #10 CLK = ~CLK; initial begin CLK = 1; RESET = 1; BTNS = 3'b0000; #105; RESET = 0; // SIZE op do_pblaze_size(); // PUSH op do_pblaze_push(8'h07); // PUSH op do_pblaze_push(8'h04); // SIZE op do_pblaze_size(); // TOP op do_pblaze_top(); // POP op do_pblaze_pop(); // SIZE op do_pblaze_size(); // TOP op do_pblaze_top(); #5; $stop(); end endmodule
heap_sol.gise
11.1
heap_summary.html
| heap Project Status (04/12/2017 - 13:36:27) | |||
| Project File: | heap2_sol.xise | Parser Errors: | No Errors |
| Module Name: | heap | Implementation State: | Programming File Not Generated |
| Target Device: | xc6slx16-3csg324 |
| |
| Product Version: | ISE 14.7 |
| |
| Design Goal: | Balanced |
| |
| Design Strategy: | Xilinx Default (unlocked) |
| |
| Environment: | System Settings |
|
| Device Utilization Summary (estimated values) | [-] | ||
| Logic Utilization | Used | Available | Utilization |
| Number of Slice Registers | 68 | 18224 | 0% |
| Number of Slice LUTs | 212 | 9112 | 2% |
| Number of fully used LUT-FF pairs | 60 | 220 | 27% |
| Number of bonded IOBs | 30 | 232 | 12% |
| Number of BUFG/BUFGCTRLs | 1 | 16 | 6% |
| Detailed Reports | [-] | ||||
| Report Name | Status | Generated | Errors | Warnings | Infos |
| Synthesis Report | Current | Thu Apr 6 07:03:49 2017 | |||
| Translation Report | |||||
| Map Report | |||||
| Place and Route Report | |||||
| CPLD Fitter Report (Text) | |||||
| Power Report | |||||
| Post-PAR Static Timing Report | |||||
| Bitgen Report |
| Secondary Reports | [-] | |
| Report Name | Status | Generated |
| ISIM Simulator Log | Out of Date | Wed Apr 12 11:38:05 2017 |
| WebTalk Report | Current | Wed Apr 12 13:36:24 2017 |
| WebTalk Log File | Current | Wed Apr 12 13:36:27 2017 |
heap_top.v
//////////////////////////////////////////////////////////////////////////////// // Copyright (c) 2004 Xilinx, Inc. // All Rights Reserved //////////////////////////////////////////////////////////////////////////////// // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: 1.01 // \ \ Filename: embedded_kcpsm3.v // / / Date Last Modified: 08/04/2004 // /___/ /\ Date Created: 06/03/2003 // \ \ / \ // \___\/\___\ // //Device: Xilinx //Purpose: // This file instantiates the KCPSM3 processor macro and connects the // program ROM. //Reference: // None //Revision History: // Rev 1.00 - kc - Start of design entry in VHDL, 06/03/2003. // Rev 1.01 - sus - Converted to verilog, 08/04/2004. //////////////////////////////////////////////////////////////////////////////// // NOTE: The name of the program ROM will probably need to be changed to // reflect the name of the program (PSM) file applied to the assembler. //////////////////////////////////////////////////////////////////////////////// // Contact: e-mail [email protected] ////////////////////////////////////////////////////////////////////////////////// // // Disclaimer: // LIMITED WARRANTY AND DISCLAIMER. These designs are // provided to you "as is". Xilinx and its licensors make and you // receive no warranties or conditions, express, implied, // statutory or otherwise, and Xilinx specifically disclaims any // implied warranties of merchantability, non-infringement, or // fitness for a particular purpose. Xilinx does not warrant that // the functions contained in these designs will meet your // requirements, or that the operation of these designs will be // uninterrupted or error free, or that defects in the Designs // will be corrected. Furthermore, Xilinx does not warrant or // make any representations regarding use or the results of the // use of the designs in terms of correctness, accuracy, // reliability, or otherwise. // // LIMITATION OF LIABILITY. In no event will Xilinx or its // licensors be liable for any loss of data, lost profits, cost // or procurement of substitute goods or services, or for any // special, incidental, consequential, or indirect damages // arising from the use or operation of the designs or // accompanying documentation, however caused and on any theory // of liability. This limitation will apply even if Xilinx // has been advised of the possibility of such damage. This // limitation shall apply not-withstanding the failure of the // essential purpose of any limited remedies herein. ////////////////////////////////////////////////////////////////////////////////// module heap2_top( CLKPORT, btn, sw, CA, CB, CC, CD, CE, CF, CG, DP, an, led ); input CLKPORT; input [4:0] btn; input [7:0] sw; output CA, CB, CC, CD, CE, CF, CG, DP; output [3:0] an; output [7:0] led; wire reset, reset_raw; wire clk; wire [9:0] address; reg [3:0] an_int; reg [4:0] btn_r; reg [3:0] bcd; reg [25:0] clk_count; reg [3:0] curr_count; reg ws; reg [1:0] reset_edge_detect; reg [2:0] reset_cnt; wire [7:0] DISP; wire [3:0] THOUS; wire [3:0] HUNS; wire [3:0] TENS; wire [3:0] ONES; wire size_btn, pop_btn, push_btn; //assign led[6:0] = 7'b0000000; assign DP = 1; //assign clk = clk_count[25]; assign clk = clk_count[17]; //assign led[7] = clk; assign reset_raw = btn[1]; always @(posedge clk) begin if(reset_raw) reset_edge_detect <= 2'b00; else if(reset_raw == 0 && reset_edge_detect[0]) reset_edge_detect <= {reset_edge_detect[0], 1'b1}; end always @(posedge clk) begin if(reset_edge_detect == 2'b01) reset_cnt <= 3'b001; else if(reset_cnt > 3'b000) reset_cnt <= reset_cnt+1; end assign reset = reset_cnt[2]; always @(posedge CLKPORT) begin if (reset_raw == 1) clk_count <= 0; else clk_count <= clk_count + 1; end always @(posedge clk) begin btn_r <= btn; end assign {size_btn, top_btn, pop_btn, push_btn} = {btn_r[3],btn_r[2],btn_r[0],btn_r[4]}; //picoblaze_rom #(.ROM_FILE("cntr.mem")) program(clk, 1'b1, address, instruction); heap_soc student_design( .clk(clk), .reset(reset), .btns({size_btn, top_btn, pop_btn, push_btn}), .switches(sw), .disp(DISP), .leds(led) ); // Custom logic bcd_display bin_bcd_conv( .DISP(DISP), .CLK(clk), .RST(reset), .THOUS(THOUS), .HUNS(HUNS), .TENS(TENS), .ONES(ONES) ); always @* begin an_int = 4'b1111; if(clk_count[12:11] == 2'b00) begin bcd = THOUS; an_int[3] = 0; end else if(clk_count[12:11] == 2'b01) begin bcd = HUNS; an_int[2] = 0; end else if(clk_count[12:11] == 2'b10) begin bcd = TENS; an_int[1] = 0; end else begin bcd = ONES; an_int[0] = 0; end end assign an = an_int; sevenseg_decoder bcd_dec(bcd,CA,CB,CC,CD,CE,CF,CG); endmodule //---------------------------------------------------------------------------------- // // END OF FILE EMBEDDED_KCPSM3.V // //----------------------------------------------------------------------------------
heap_xst.xrpt
iseconfig/heap.xreport
2017-04-12T11:56:01 heap2_top 2017-04-12T09:53:21 C:/Users/Mark/Dropbox/EE209/Lab/heap2_sol/iseconfig/heap.xreport C:/Users/Mark/Dropbox/EE209/Lab/heap2_sol\ 2017-04-12T08:41:12 false
iseconfig/heap2_sol.projectmgr
2 /heap C:|Users|Mark|Dropbox|EE209|Lab|heap2_sol|heap.v heap2_top (C:/Users/Mark/Dropbox/EE209/Lab/heap2_sol/heap_top.v) 0 0 000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000001d1000000020000000000000000000000000200000064ffffffff000000810000000300000002000001d10000000100000003000000000000000100000003 true heap2_top (C:/Users/Mark/Dropbox/EE209/Lab/heap2_sol/heap_top.v) 1 Configure Target Device Design Utilities Implement Design Synthesize - XST User Constraints Generate Programming File 0 0 000000ff00000000000000010000000100000000000000000000000000000000000000000000000175000000010000000100000000000000000000000064ffffffff000000810000000000000001000001750000000100000000 false Generate Programming File 1 0 0 000000ff000000000000000100000000000000000100000000000000000000000000000000000004e3000000040101000100000000000000000000000064ffffffff0000008100000000000000040000005a00000001000000000000004a0000000100000000000000660000000100000000000003d90000000100000000 false adder8.v 1 work 0 0 000000ff00000000000000010000000000000000010000000000000000000000000000000000000109000000010001000100000000000000000000000064ffffffff000000810000000000000001000001090000000100000000 false work 000000ff00000000000000020000011b0000011b01000000050100000002 Behavioral Simulation 1 0 0 false 2 /heap2_top C:|Users|Mark|Dropbox|EE209|Lab|heap2_sol|heap_top.v/student_design - heap_soc /heap_soc_tb C:|Users|Mark|Dropbox|EE209|Lab|heap2_sol|heap_soc_tb.v /heap_tb C:|Users|Mark|Dropbox|EE209|Lab|heap2_sol|heap_tb.v /sqrt_sys_tb C:|Users|Mark|Dropbox|EE209|Lab|heap2_sol|heap_soc_tb.v heap_soc_tb (C:/Users/Mark/Dropbox/EE209/Lab/heap2_sol/heap_soc_tb.v) 0 0 000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000163000000020000000000000000000000000200000064ffffffff000000810000000300000002000001630000000100000003000000000000000100000003 true heap_soc_tb (C:/Users/Mark/Dropbox/EE209/Lab/heap2_sol/heap_soc_tb.v) 1 Design Utilities ISim Simulator 0 0 000000ff00000000000000010000000100000000000000000000000000000000000000000000000175000000010000000100000000000000000000000064ffffffff000000810000000000000001000001750000000100000000 false 1 Simulate Behavioral Model 0 0 000000ff00000000000000010000000100000000000000000000000000000000000000000000000175000000010000000100000000000000000000000064ffffffff000000810000000000000001000001750000000100000000 false Simulate Behavioral Model 1 User Constraints 0 0 000000ff00000000000000010000000100000000000000000000000000000000000000000000000175000000010000000100000000000000000000000064ffffffff000000810000000000000001000001750000000100000000 false
iseconfig/heap2_top.xreport
2017-04-17T11:55:31 heap2_top 2017-04-17T11:45:05 C:/Users/Mark/Dropbox/EE209/Lab/heap2/iseconfig/heap2_top.xreport C:/Users/Mark/Dropbox/EE209/Lab/heap2\ 2017-04-13T07:24:08 false
iseconfig/heap_sol.projectmgr
2 /cntr4 C:|Users|Mark|Dropbox|EE209|Lab|mmind_sol|cntr4.v heap (C:/Users/Mark/Dropbox/EE209/Lab/heap_sol/heap.v) 0 0 000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000129000000020000000000000000000000000200000064ffffffff000000810000000300000002000001290000000100000003000000000000000100000003 true heap (C:/Users/Mark/Dropbox/EE209/Lab/heap_sol/heap.v) 1 Design Utilities 0 0 false 1 0 0 000000ff000000000000000100000000000000000100000000000000000000000000000000000004e3000000040101000100000000000000000000000064ffffffff000000810000000000000004000000420000000100000000000000240000000100000000000000660000000100000000000004170000000100000000 false adder8.v 1 work 0 0 000000ff00000000000000010000000000000000010000000000000000000000000000000000000109000000010001000100000000000000000000000064ffffffff000000810000000000000001000001090000000100000000 false work 1 Configure Target Device Design Utilities Implement Design User Constraints Synthesize - XST 0 0 000000ff00000000000000010000000100000000000000000000000000000000000000000000000175000000010000000100000000000000000000000064ffffffff000000810000000000000001000001750000000100000000 false Synthesize - XST 000000ff00000000000000020000011b0000011b01000000050100000002 Behavioral Simulation 2 /heap C:|Users|Mark|Dropbox|EE209|Lab|heap_sol|heap.v /heap_tb C:|Users|Mark|Dropbox|EE209|Lab|heap_sol|heap_tb.v/uut - heap/pop_control - ctrlpop /heap_tb C:|Users|Mark|Dropbox|EE209|Lab|heap_sol|heap_tb.v/uut - heap/push_control - ctrlpush heap_tb (C:/Users/Mark/Dropbox/EE209/Lab/heap_sol/heap_tb.v) 0 0 000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000013d000000020000000000000000000000000200000064ffffffff0000008100000003000000020000013d0000000100000003000000000000000100000003 false heap_tb (C:/Users/Mark/Dropbox/EE209/Lab/heap_sol/heap_tb.v) 1 Design Utilities 0 0 000000ff000000000000000100000001000000000000000000000000000000000000000000000000f5000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f50000000100000000 false 1 Simulate Behavioral Model 0 0 000000ff00000000000000010000000100000000000000000000000000000000000000000000000175000000010000000100000000000000000000000064ffffffff000000810000000000000001000001750000000100000000 false Simulate Behavioral Model
iseconfig/mem16x8.xreport
2017-04-05T09:42:49 heap Unknown C:/Users/Mark/Dropbox/EE209/Lab/heap_sol/iseconfig/mem16x8.xreport C:/Users/Mark/Dropbox/EE209/Lab/heap_sol 2017-04-05T09:42:48 false
kcpsm6.v
// /////////////////////////////////////////////////////////////////////////////////////////// // Copyright © 2010-2012, Xilinx, Inc. // This file contains confidential and proprietary information of Xilinx, Inc. and is // protected under U.S. and international copyright and other intellectual property laws. /////////////////////////////////////////////////////////////////////////////////////////// // // Disclaimer: // This disclaimer is not a license and does not grant any rights to the materials // distributed herewith. Except as otherwise provided in a valid license issued to // you by Xilinx, and to the maximum extent permitted by applicable law: [1] THESE // MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY // DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, // INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, // OR FITNESS FOR ANY PARTICULAR PURPOSE; and [2] Xilinx shall not be liable // (whether in contract or tort, including negligence, or under any other theory // of liability) for any loss or damage of any kind or nature related to, arising // under or in connection with these materials, including for any direct, or any // indirect, special, incidental, or consequential loss or damage (including loss // of data, profits, goodwill, or any type of loss or damage suffered as a result // of any action brought by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail-safe, or for use in any // application requiring fail-safe performance, such as life-support or safety // devices or systems, Class III medical devices, nuclear facilities, applications // related to the deployment of airbags, or any other applications that could lead // to death, personal injury, or severe property or environmental damage // (individually and collectively, "Critical Applications)). Customer assumes the // sole risk and liability of any use of Xilinx products in Critical Applications, // subject only to applicable laws and regulations governing limitations on product // liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. // /////////////////////////////////////////////////////////////////////////////////////////// // // KCPSM6 - PicoBlaze for Spartan-6 and Virtex-6 devices. // // Version 1.1 - 4th March 2010. // Derived from kcpsm6.vhd Version 1.1 (9th February 2011) by Nick Sawyer. // Version 1.2 - 4th October 2012. // Addition of WebTalk information. // // Ken Chapman // Xilinx Ltd // Benchmark House // 203 Brooklands Road // Weybridge // Surrey KT13 ORH // United Kingdom // // [email protected] // /////////////////////////////////////////////////////////////////////////////////////////// // // Format of this file. // // The module defines the implementation of the logic using Xilinx primitives. // These ensure predictable synthesis results and maximise the density of the implementation. // The Unisim Library is used to define Xilinx primitives. It is also used during // simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd // /////////////////////////////////////////////////////////////////////////////////////////// // `timescale 1ps/1ps // /////////////////////////////////////////////////////////////////////////////////////////// // // Main Entity for kcpsm6 with WebTalk Attributes // (* CORE_GENERATION_INFO = "kcpsm6,kcpsm6_v1_2,{component_name=kcpsm6}" *) module kcpsm6 (address, instruction, bram_enable, in_port, out_port, port_id, write_strobe, k_write_strobe, read_strobe, interrupt, interrupt_ack, sleep, reset, clk) ; parameter [7:0] hwbuild = 8'h00 ; parameter [11:0] interrupt_vector = 12'h3FF ; parameter integer scratch_pad_memory_size = 64 ; output [11:0] address ; input [17:0] instruction ; output bram_enable ; input [7:0] in_port ; output [7:0] out_port ; output [7:0] port_id ; output write_strobe ; output k_write_strobe ; output read_strobe ; input interrupt ; output interrupt_ack ; input sleep ; input reset ; input clk ; // /////////////////////////////////////////////////////////////////////////////////////////// // // Start of Main Architecture for kcpsm6 // /////////////////////////////////////////////////////////////////////////////////////////// // // Signals used in kcpsm6 // /////////////////////////////////////////////////////////////////////////////////////////// // // State Machine and Interrupt // wire [2:1] t_state_value ; wire [2:1] t_state ; wire run_value ; wire run ; wire internal_reset_value ; wire internal_reset ; wire sync_sleep ; wire int_enable_type ; wire interrupt_enable_value ; wire interrupt_enable ; wire sync_interrupt ; wire active_interrupt_value ; wire active_interrupt ; // // Arithmetic and Logical Functions // wire [2:0] arith_logical_sel ; wire arith_carry_in ; wire arith_carry_value ; wire arith_carry ; wire [7:0] half_arith_logical ; wire [7:0] logical_carry_mask ; wire [7:0] carry_arith_logical ; wire [7:0] arith_logical_value ; wire [7:0] arith_logical_result ; // // Shift and Rotate Functions // wire [7:0] shift_rotate_value ; wire [7:0] shift_rotate_result ; wire shift_in_bit ; // // ALU structure // wire [7:0] alu_result ; wire [1:0] alu_mux_sel_value ; wire [1:0] alu_mux_sel ; // // Strobes // wire strobe_type ; wire write_strobe_value ; wire k_write_strobe_value ; wire read_strobe_value ; // // Flags // wire flag_enable_type ; wire flag_enable_value ; wire flag_enable ; wire lower_parity ; wire lower_parity_sel ; wire carry_lower_parity ; wire upper_parity ; wire parity ; wire shift_carry_value ; wire shift_carry ; wire carry_flag_value ; wire carry_flag ; wire use_zero_flag_value ; wire use_zero_flag ; wire drive_carry_in_zero ; wire carry_in_zero ; wire lower_zero ; wire lower_zero_sel ; wire carry_lower_zero ; wire middle_zero ; wire middle_zero_sel ; wire carry_middle_zero ; wire upper_zero_sel ; wire zero_flag_value ; wire zero_flag ; // // Scratch Pad Memory // wire spm_enable_value ; wire spm_enable ; wire [7:0] spm_ram_data ; wire [7:0] spm_data ; // // Registers // wire regbank_type ; wire bank_value ; wire bank ; wire loadstar_type ; wire sx_addr4_value ; wire register_enable_type ; wire register_enable_value ; wire register_enable ; wire [4:0] sx_addr ; wire [4:0] sy_addr ; wire [7:0] sx ; wire [7:0] sy ; // // Second Operand // wire [7:0] sy_or_kk ; // // Program Counter // wire pc_move_is_valid ; wire move_type ; wire returni_type ; wire [2:0] pc_mode ; wire [11:0] register_vector ; wire [11:0] half_pc ; wire [10:0] carry_pc ; wire [11:0] pc_value ; wire [11:0] pc ; wire [11:0] pc_vector ; // // Program Counter Stack // wire push_stack ; wire pop_stack ; wire [11:0] stack_memory ; wire [11:0] return_vector ; wire stack_carry_flag ; wire shadow_carry_flag ; wire stack_zero_flag ; wire shadow_zero_value ; wire shadow_zero_flag ; wire stack_bank ; wire shadow_bank ; wire stack_bit ; wire special_bit ; wire [4:0] half_pointer_value ; wire [4:0] feed_pointer_value ; wire [4:0] stack_pointer_carry ; wire [4:0] stack_pointer_value ; wire [4:0] stack_pointer ; // // // //********************************************************************************** // // Signals between these *** lines are only made visible during simulation // //synthesis translate_off // reg [1:152] kcpsm6_opcode ; reg [1:128] kcpsm6_status ; reg [7:0] sim_s0 ; reg [7:0] sim_s1 ; reg [7:0] sim_s2 ; reg [7:0] sim_s3 ; reg [7:0] sim_s4 ; reg [7:0] sim_s5 ; reg [7:0] sim_s6 ; reg [7:0] sim_s7 ; reg [7:0] sim_s8 ; reg [7:0] sim_s9 ; reg [7:0] sim_sA ; reg [7:0] sim_sB ; reg [7:0] sim_sC ; reg [7:0] sim_sD ; reg [7:0] sim_sE ; reg [7:0] sim_sF ; reg [7:0] sim_spm00 ; reg [7:0] sim_spm01 ; reg [7:0] sim_spm02 ; reg [7:0] sim_spm03 ; reg [7:0] sim_spm04 ; reg [7:0] sim_spm05 ; reg [7:0] sim_spm06 ; reg [7:0] sim_spm07 ; reg [7:0] sim_spm08 ; reg [7:0] sim_spm09 ; reg [7:0] sim_spm0A ; reg [7:0] sim_spm0B ; reg [7:0] sim_spm0C ; reg [7:0] sim_spm0D ; reg [7:0] sim_spm0E ; reg [7:0] sim_spm0F ; reg [7:0] sim_spm10 ; reg [7:0] sim_spm11 ; reg [7:0] sim_spm12 ; reg [7:0] sim_spm13 ; reg [7:0] sim_spm14 ; reg [7:0] sim_spm15 ; reg [7:0] sim_spm16 ; reg [7:0] sim_spm17 ; reg [7:0] sim_spm18 ; reg [7:0] sim_spm19 ; reg [7:0] sim_spm1A ; reg [7:0] sim_spm1B ; reg [7:0] sim_spm1C ; reg [7:0] sim_spm1D ; reg [7:0] sim_spm1E ; reg [7:0] sim_spm1F ; reg [7:0] sim_spm20 ; reg [7:0] sim_spm21 ; reg [7:0] sim_spm22 ; reg [7:0] sim_spm23 ; reg [7:0] sim_spm24 ; reg [7:0] sim_spm25 ; reg [7:0] sim_spm26 ; reg [7:0] sim_spm27 ; reg [7:0] sim_spm28 ; reg [7:0] sim_spm29 ; reg [7:0] sim_spm2A ; reg [7:0] sim_spm2B ; reg [7:0] sim_spm2C ; reg [7:0] sim_spm2D ; reg [7:0] sim_spm2E ; reg [7:0] sim_spm2F ; reg [7:0] sim_spm30 ; reg [7:0] sim_spm31 ; reg [7:0] sim_spm32 ; reg [7:0] sim_spm33 ; reg [7:0] sim_spm34 ; reg [7:0] sim_spm35 ; reg [7:0] sim_spm36 ; reg [7:0] sim_spm37 ; reg [7:0] sim_spm38 ; reg [7:0] sim_spm39 ; reg [7:0] sim_spm3A ; reg [7:0] sim_spm3B ; reg [7:0] sim_spm3C ; reg [7:0] sim_spm3D ; reg [7:0] sim_spm3E ; reg [7:0] sim_spm3F ; reg [7:0] sim_spm40 ; reg [7:0] sim_spm41 ; reg [7:0] sim_spm42 ; reg [7:0] sim_spm43 ; reg [7:0] sim_spm44 ; reg [7:0] sim_spm45 ; reg [7:0] sim_spm46 ; reg [7:0] sim_spm47 ; reg [7:0] sim_spm48 ; reg [7:0] sim_spm49 ; reg [7:0] sim_spm4A ; reg [7:0] sim_spm4B ; reg [7:0] sim_spm4C ; reg [7:0] sim_spm4D ; reg [7:0] sim_spm4E ; reg [7:0] sim_spm4F ; reg [7:0] sim_spm50 ; reg [7:0] sim_spm51 ; reg [7:0] sim_spm52 ; reg [7:0] sim_spm53 ; reg [7:0] sim_spm54 ; reg [7:0] sim_spm55 ; reg [7:0] sim_spm56 ; reg [7:0] sim_spm57 ; reg [7:0] sim_spm58 ; reg [7:0] sim_spm59 ; reg [7:0] sim_spm5A ; reg [7:0] sim_spm5B ; reg [7:0] sim_spm5C ; reg [7:0] sim_spm5D ; reg [7:0] sim_spm5E ; reg [7:0] sim_spm5F ; reg [7:0] sim_spm60 ; reg [7:0] sim_spm61 ; reg [7:0] sim_spm62 ; reg [7:0] sim_spm63 ; reg [7:0] sim_spm64 ; reg [7:0] sim_spm65 ; reg [7:0] sim_spm66 ; reg [7:0] sim_spm67 ; reg [7:0] sim_spm68 ; reg [7:0] sim_spm69 ; reg [7:0] sim_spm6A ; reg [7:0] sim_spm6B ; reg [7:0] sim_spm6C ; reg [7:0] sim_spm6D ; reg [7:0] sim_spm6E ; reg [7:0] sim_spm6F ; reg [7:0] sim_spm70 ; reg [7:0] sim_spm71 ; reg [7:0] sim_spm72 ; reg [7:0] sim_spm73 ; reg [7:0] sim_spm74 ; reg [7:0] sim_spm75 ; reg [7:0] sim_spm76 ; reg [7:0] sim_spm77 ; reg [7:0] sim_spm78 ; reg [7:0] sim_spm79 ; reg [7:0] sim_spm7A ; reg [7:0] sim_spm7B ; reg [7:0] sim_spm7C ; reg [7:0] sim_spm7D ; reg [7:0] sim_spm7E ; reg [7:0] sim_spm7F ; reg [7:0] sim_spm80 ; reg [7:0] sim_spm81 ; reg [7:0] sim_spm82 ; reg [7:0] sim_spm83 ; reg [7:0] sim_spm84 ; reg [7:0] sim_spm85 ; reg [7:0] sim_spm86 ; reg [7:0] sim_spm87 ; reg [7:0] sim_spm88 ; reg [7:0] sim_spm89 ; reg [7:0] sim_spm8A ; reg [7:0] sim_spm8B ; reg [7:0] sim_spm8C ; reg [7:0] sim_spm8D ; reg [7:0] sim_spm8E ; reg [7:0] sim_spm8F ; reg [7:0] sim_spm90 ; reg [7:0] sim_spm91 ; reg [7:0] sim_spm92 ; reg [7:0] sim_spm93 ; reg [7:0] sim_spm94 ; reg [7:0] sim_spm95 ; reg [7:0] sim_spm96 ; reg [7:0] sim_spm97 ; reg [7:0] sim_spm98 ; reg [7:0] sim_spm99 ; reg [7:0] sim_spm9A ; reg [7:0] sim_spm9B ; reg [7:0] sim_spm9C ; reg [7:0] sim_spm9D ; reg [7:0] sim_spm9E ; reg [7:0] sim_spm9F ; reg [7:0] sim_spmA0 ; reg [7:0] sim_spmA1 ; reg [7:0] sim_spmA2 ; reg [7:0] sim_spmA3 ; reg [7:0] sim_spmA4 ; reg [7:0] sim_spmA5 ; reg [7:0] sim_spmA6 ; reg [7:0] sim_spmA7 ; reg [7:0] sim_spmA8 ; reg [7:0] sim_spmA9 ; reg [7:0] sim_spmAA ; reg [7:0] sim_spmAB ; reg [7:0] sim_spmAC ; reg [7:0] sim_spmAD ; reg [7:0] sim_spmAE ; reg [7:0] sim_spmAF ; reg [7:0] sim_spmB0 ; reg [7:0] sim_spmB1 ; reg [7:0] sim_spmB2 ; reg [7:0] sim_spmB3 ; reg [7:0] sim_spmB4 ; reg [7:0] sim_spmB5 ; reg [7:0] sim_spmB6 ; reg [7:0] sim_spmB7 ; reg [7:0] sim_spmB8 ; reg [7:0] sim_spmB9 ; reg [7:0] sim_spmBA ; reg [7:0] sim_spmBB ; reg [7:0] sim_spmBC ; reg [7:0] sim_spmBD ; reg [7:0] sim_spmBE ; reg [7:0] sim_spmBF ; reg [7:0] sim_spmC0 ; reg [7:0] sim_spmC1 ; reg [7:0] sim_spmC2 ; reg [7:0] sim_spmC3 ; reg [7:0] sim_spmC4 ; reg [7:0] sim_spmC5 ; reg [7:0] sim_spmC6 ; reg [7:0] sim_spmC7 ; reg [7:0] sim_spmC8 ; reg [7:0] sim_spmC9 ; reg [7:0] sim_spmCA ; reg [7:0] sim_spmCB ; reg [7:0] sim_spmCC ; reg [7:0] sim_spmCD ; reg [7:0] sim_spmCE ; reg [7:0] sim_spmCF ; reg [7:0] sim_spmD0 ; reg [7:0] sim_spmD1 ; reg [7:0] sim_spmD2 ; reg [7:0] sim_spmD3 ; reg [7:0] sim_spmD4 ; reg [7:0] sim_spmD5 ; reg [7:0] sim_spmD6 ; reg [7:0] sim_spmD7 ; reg [7:0] sim_spmD8 ; reg [7:0] sim_spmD9 ; reg [7:0] sim_spmDA ; reg [7:0] sim_spmDB ; reg [7:0] sim_spmDC ; reg [7:0] sim_spmDD ; reg [7:0] sim_spmDE ; reg [7:0] sim_spmDF ; reg [7:0] sim_spmE0 ; reg [7:0] sim_spmE1 ; reg [7:0] sim_spmE2 ; reg [7:0] sim_spmE3 ; reg [7:0] sim_spmE4 ; reg [7:0] sim_spmE5 ; reg [7:0] sim_spmE6 ; reg [7:0] sim_spmE7 ; reg [7:0] sim_spmE8 ; reg [7:0] sim_spmE9 ; reg [7:0] sim_spmEA ; reg [7:0] sim_spmEB ; reg [7:0] sim_spmEC ; reg [7:0] sim_spmED ; reg [7:0] sim_spmEE ; reg [7:0] sim_spmEF ; reg [7:0] sim_spmF0 ; reg [7:0] sim_spmF1 ; reg [7:0] sim_spmF2 ; reg [7:0] sim_spmF3 ; reg [7:0] sim_spmF4 ; reg [7:0] sim_spmF5 ; reg [7:0] sim_spmF6 ; reg [7:0] sim_spmF7 ; reg [7:0] sim_spmF8 ; reg [7:0] sim_spmF9 ; reg [7:0] sim_spmFA ; reg [7:0] sim_spmFB ; reg [7:0] sim_spmFC ; reg [7:0] sim_spmFD ; reg [7:0] sim_spmFE ; reg [7:0] sim_spmFF ; // // initialise the values // initial begin kcpsm6_status = "A,NZ,NC,ID,Reset" ; kcpsm6_opcode = "LOAD s0, s0 " ; sim_s0 = 8'h00 ; sim_s1 = 8'h00 ; sim_s2 = 8'h00 ; sim_s3 = 8'h00 ; sim_s4 = 8'h00 ; sim_s5 = 8'h00 ; sim_s6 = 8'h00 ; sim_s7 = 8'h00 ; sim_s8 = 8'h00 ; sim_s9 = 8'h00 ; sim_sA = 8'h00 ; sim_sB = 8'h00 ; sim_sC = 8'h00 ; sim_sD = 8'h00 ; sim_sE = 8'h00 ; sim_sF = 8'h00 ; sim_spm00 = 8'h00 ; sim_spm01 = 8'h00 ; sim_spm02 = 8'h00 ; sim_spm03 = 8'h00 ; sim_spm04 = 8'h00 ; sim_spm05 = 8'h00 ; sim_spm06 = 8'h00 ; sim_spm07 = 8'h00 ; sim_spm08 = 8'h00 ; sim_spm09 = 8'h00 ; sim_spm0A = 8'h00 ; sim_spm0B = 8'h00 ; sim_spm0C = 8'h00 ; sim_spm0D = 8'h00 ; sim_spm0E = 8'h00 ; sim_spm0F = 8'h00 ; sim_spm10 = 8'h00 ; sim_spm11 = 8'h00 ; sim_spm12 = 8'h00 ; sim_spm13 = 8'h00 ; sim_spm14 = 8'h00 ; sim_spm15 = 8'h00 ; sim_spm16 = 8'h00 ; sim_spm17 = 8'h00 ; sim_spm18 = 8'h00 ; sim_spm19 = 8'h00 ; sim_spm1A = 8'h00 ; sim_spm1B = 8'h00 ; sim_spm1C = 8'h00 ; sim_spm1D = 8'h00 ; sim_spm1E = 8'h00 ; sim_spm1F = 8'h00 ; sim_spm20 = 8'h00 ; sim_spm21 = 8'h00 ; sim_spm22 = 8'h00 ; sim_spm23 = 8'h00 ; sim_spm24 = 8'h00 ; sim_spm25 = 8'h00 ; sim_spm26 = 8'h00 ; sim_spm27 = 8'h00 ; sim_spm28 = 8'h00 ; sim_spm29 = 8'h00 ; sim_spm2A = 8'h00 ; sim_spm2B = 8'h00 ; sim_spm2C = 8'h00 ; sim_spm2D = 8'h00 ; sim_spm2E = 8'h00 ; sim_spm2F = 8'h00 ; sim_spm30 = 8'h00 ; sim_spm31 = 8'h00 ; sim_spm32 = 8'h00 ; sim_spm33 = 8'h00 ; sim_spm34 = 8'h00 ; sim_spm35 = 8'h00 ; sim_spm36 = 8'h00 ; sim_spm37 = 8'h00 ; sim_spm38 = 8'h00 ; sim_spm39 = 8'h00 ; sim_spm3A = 8'h00 ; sim_spm3B = 8'h00 ; sim_spm3C = 8'h00 ; sim_spm3D = 8'h00 ; sim_spm3E = 8'h00 ; sim_spm3F = 8'h00 ; sim_spm40 = 8'h00 ; sim_spm41 = 8'h00 ; sim_spm42 = 8'h00 ; sim_spm43 = 8'h00 ; sim_spm44 = 8'h00 ; sim_spm45 = 8'h00 ; sim_spm46 = 8'h00 ; sim_spm47 = 8'h00 ; sim_spm48 = 8'h00 ; sim_spm49 = 8'h00 ; sim_spm4A = 8'h00 ; sim_spm4B = 8'h00 ; sim_spm4C = 8'h00 ; sim_spm4D = 8'h00 ; sim_spm4E = 8'h00 ; sim_spm4F = 8'h00 ; sim_spm50 = 8'h00 ; sim_spm51 = 8'h00 ; sim_spm52 = 8'h00 ; sim_spm53 = 8'h00 ; sim_spm54 = 8'h00 ; sim_spm55 = 8'h00 ; sim_spm56 = 8'h00 ; sim_spm57 = 8'h00 ; sim_spm58 = 8'h00 ; sim_spm59 = 8'h00 ; sim_spm5A = 8'h00 ; sim_spm5B = 8'h00 ; sim_spm5C = 8'h00 ; sim_spm5D = 8'h00 ; sim_spm5E = 8'h00 ; sim_spm5F = 8'h00 ; sim_spm60 = 8'h00 ; sim_spm61 = 8'h00 ; sim_spm62 = 8'h00 ; sim_spm63 = 8'h00 ; sim_spm64 = 8'h00 ; sim_spm65 = 8'h00 ; sim_spm66 = 8'h00 ; sim_spm67 = 8'h00 ; sim_spm68 = 8'h00 ; sim_spm69 = 8'h00 ; sim_spm6A = 8'h00 ; sim_spm6B = 8'h00 ; sim_spm6C = 8'h00 ; sim_spm6D = 8'h00 ; sim_spm6E = 8'h00 ; sim_spm6F = 8'h00 ; sim_spm70 = 8'h00 ; sim_spm71 = 8'h00 ; sim_spm72 = 8'h00 ; sim_spm73 = 8'h00 ; sim_spm74 = 8'h00 ; sim_spm75 = 8'h00 ; sim_spm76 = 8'h00 ; sim_spm77 = 8'h00 ; sim_spm78 = 8'h00 ; sim_spm79 = 8'h00 ; sim_spm7A = 8'h00 ; sim_spm7B = 8'h00 ; sim_spm7C = 8'h00 ; sim_spm7D = 8'h00 ; sim_spm7E = 8'h00 ; sim_spm7F = 8'h00 ; sim_spm80 = 8'h00 ; sim_spm81 = 8'h00 ; sim_spm82 = 8'h00 ; sim_spm83 = 8'h00 ; sim_spm84 = 8'h00 ; sim_spm85 = 8'h00 ; sim_spm86 = 8'h00 ; sim_spm87 = 8'h00 ; sim_spm88 = 8'h00 ; sim_spm89 = 8'h00 ; sim_spm8A = 8'h00 ; sim_spm8B = 8'h00 ; sim_spm8C = 8'h00 ; sim_spm8D = 8'h00 ; sim_spm8E = 8'h00 ; sim_spm8F = 8'h00 ; sim_spm90 = 8'h00 ; sim_spm91 = 8'h00 ; sim_spm92 = 8'h00 ; sim_spm93 = 8'h00 ; sim_spm94 = 8'h00 ; sim_spm95 = 8'h00 ; sim_spm96 = 8'h00 ; sim_spm97 = 8'h00 ; sim_spm98 = 8'h00 ; sim_spm99 = 8'h00 ; sim_spm9A = 8'h00 ; sim_spm9B = 8'h00 ; sim_spm9C = 8'h00 ; sim_spm9D = 8'h00 ; sim_spm9E = 8'h00 ; sim_spm9F = 8'h00 ; sim_spmA0 = 8'h00 ; sim_spmA1 = 8'h00 ; sim_spmA2 = 8'h00 ; sim_spmA3 = 8'h00 ; sim_spmA4 = 8'h00 ; sim_spmA5 = 8'h00 ; sim_spmA6 = 8'h00 ; sim_spmA7 = 8'h00 ; sim_spmA8 = 8'h00 ; sim_spmA9 = 8'h00 ; sim_spmAA = 8'h00 ; sim_spmAB = 8'h00 ; sim_spmAC = 8'h00 ; sim_spmAD = 8'h00 ; sim_spmAE = 8'h00 ; sim_spmAF = 8'h00 ; sim_spmB0 = 8'h00 ; sim_spmB1 = 8'h00 ; sim_spmB2 = 8'h00 ; sim_spmB3 = 8'h00 ; sim_spmB4 = 8'h00 ; sim_spmB5 = 8'h00 ; sim_spmB6 = 8'h00 ; sim_spmB7 = 8'h00 ; sim_spmB8 = 8'h00 ; sim_spmB9 = 8'h00 ; sim_spmBA = 8'h00 ; sim_spmBB = 8'h00 ; sim_spmBC = 8'h00 ; sim_spmBD = 8'h00 ; sim_spmBE = 8'h00 ; sim_spmBF = 8'h00 ; sim_spmC0 = 8'h00 ; sim_spmC1 = 8'h00 ; sim_spmC2 = 8'h00 ; sim_spmC3 = 8'h00 ; sim_spmC4 = 8'h00 ; sim_spmC5 = 8'h00 ; sim_spmC6 = 8'h00 ; sim_spmC7 = 8'h00 ; sim_spmC8 = 8'h00 ; sim_spmC9 = 8'h00 ; sim_spmCA = 8'h00 ; sim_spmCB = 8'h00 ; sim_spmCC = 8'h00 ; sim_spmCD = 8'h00 ; sim_spmCE = 8'h00 ; sim_spmCF = 8'h00 ; sim_spmD0 = 8'h00 ; sim_spmD1 = 8'h00 ; sim_spmD2 = 8'h00 ; sim_spmD3 = 8'h00 ; sim_spmD4 = 8'h00 ; sim_spmD5 = 8'h00 ; sim_spmD6 = 8'h00 ; sim_spmD7 = 8'h00 ; sim_spmD8 = 8'h00 ; sim_spmD9 = 8'h00 ; sim_spmDA = 8'h00 ; sim_spmDB = 8'h00 ; sim_spmDC = 8'h00 ; sim_spmDD = 8'h00 ; sim_spmDE = 8'h00 ; sim_spmDF = 8'h00 ; sim_spmE0 = 8'h00 ; sim_spmE1 = 8'h00 ; sim_spmE2 = 8'h00 ; sim_spmE3 = 8'h00 ; sim_spmE4 = 8'h00 ; sim_spmE5 = 8'h00 ; sim_spmE6 = 8'h00 ; sim_spmE7 = 8'h00 ; sim_spmE8 = 8'h00 ; sim_spmE9 = 8'h00 ; sim_spmEA = 8'h00 ; sim_spmEB = 8'h00 ; sim_spmEC = 8'h00 ; sim_spmED = 8'h00 ; sim_spmEE = 8'h00 ; sim_spmEF = 8'h00 ; sim_spmF0 = 8'h00 ; sim_spmF1 = 8'h00 ; sim_spmF2 = 8'h00 ; sim_spmF3 = 8'h00 ; sim_spmF4 = 8'h00 ; sim_spmF5 = 8'h00 ; sim_spmF6 = 8'h00 ; sim_spmF7 = 8'h00 ; sim_spmF8 = 8'h00 ; sim_spmF9 = 8'h00 ; sim_spmFA = 8'h00 ; sim_spmFB = 8'h00 ; sim_spmFC = 8'h00 ; sim_spmFD = 8'h00 ; sim_spmFE = 8'h00 ; sim_spmFF = 8'h00 ; end // //synthesis translate_on // //********************************************************************************** // // /////////////////////////////////////////////////////////////////////////////////////////// // // // Start of kcpsm6 circuit description // // Summary of all primitives defined. // // 29 x LUT6 79 LUTs // 50 x LUT6_2 // 48 x FD 82 flip-flops // 20 x FDR (Depending on the value of 'hwbuild' up) // 0 x FDS (to eight FDR will be replaced by FDS ) // 14 x FDRE // 29 x MUXCY // 27 x XORCY // 4 x RAM32M (16 LUTs) // // 2 x RAM64M or 8 x RAM128X1S or 8 x RAM256X1S // (8 LUTs) (16 LUTs) (32 LUTs) // /////////////////////////////////////////////////////////////////////////////////////////// // // /////////////////////////////////////////////////////////////////////////////////////////// // // Perform check of generic to report error as soon as possible. // /////////////////////////////////////////////////////////////////////////////////////////// // initial begin if (scratch_pad_memory_size != 64 && scratch_pad_memory_size != 128 && scratch_pad_memory_size != 256) begin #1; $display("\n\nInvalid 'scratch_pad_memory_size'. Please set to 64, 128 or 256.\n\n"); $finish; end end // /////////////////////////////////////////////////////////////////////////////////////////// // // State Machine and Control // // // 1 x LUT6 // 4 x LUT6_2 // 9 x FD // /////////////////////////////////////////////////////////////////////////////////////////// // (* HBLKNM = "kcpsm6_control" *) LUT6_2 #( .INIT (64'hFFFFF55500000EEE)) reset_lut( .I0 (run), .I1 (internal_reset), .I2 (stack_pointer_carry[4]), .I3 (t_state[2]), .I4 (reset), .I5 (1'b1), .O5 (run_value), .O6 (internal_reset_value)); (* HBLKNM = "kcpsm6_control" *) FD run_flop ( .D (run_value), .Q (run), .C (clk)); (* HBLKNM = "kcpsm6_control" *) FD internal_reset_flop( .D (internal_reset_value), .Q (internal_reset), .C (clk)); (* HBLKNM = "kcpsm6_decode2" *) FD sync_sleep_flop( .D (sleep), .Q (sync_sleep), .C (clk)); (* HBLKNM = "kcpsm6_control" *) LUT6_2 #( .INIT (64'h0083000B00C4004C)) t_state_lut( .I0 (t_state[1]), .I1 (t_state[2]), .I2 (sync_sleep), .I3 (internal_reset), .I4 (special_bit), .I5 (1'b1), .O5 (t_state_value[1]), .O6 (t_state_value[2])); (* HBLKNM = "kcpsm6_control" *) FD t_state1_flop ( .D (t_state_value[1]), .Q (t_state[1]), .C (clk)); (* HBLKNM = "kcpsm6_control" *) FD t_state2_flop ( .D (t_state_value[2]), .Q (t_state[2]), .C (clk)); (* HBLKNM = "kcpsm6_decode0" *) LUT6_2 #( .INIT (64'h0010000000000800)) int_enable_type_lut( .I0 (instruction[13]), .I1 (instruction[14]), .I2 (instruction[15]), .I3 (instruction[16]), .I4 (instruction[17]), .I5 (1'b1), .O5 (loadstar_type), .O6 (int_enable_type)) ; (* HBLKNM = "kcpsm6_decode0" *) LUT6 #( .INIT (64'h000000000000CAAA)) interrupt_enable_lut( .I0 (interrupt_enable), .I1 (instruction[0]), .I2 (int_enable_type), .I3 (t_state[1]), .I4 (active_interrupt), .I5 (internal_reset), .O (interrupt_enable_value)); (* HBLKNM = "kcpsm6_decode0" *) FD interrupt_enable_flop ( .D (interrupt_enable_value), .Q (interrupt_enable), .C (clk)); (* HBLKNM = "kcpsm6_decode2" *) FD sync_interrupt_flop ( .D (interrupt), .Q (sync_interrupt), .C (clk)); (* HBLKNM = "kcpsm6_control" *) LUT6_2 # ( .INIT (64'hCC33FF0080808080)) active_interrupt_lut( .I0 (interrupt_enable), .I1 (t_state[2]), .I2 (sync_interrupt), .I3 (bank), .I4 (loadstar_type), .I5 (1'b1), .O5 (active_interrupt_value), .O6 (sx_addr4_value)); (* HBLKNM = "kcpsm6_control" *) FD active_interrupt_flop ( .D (active_interrupt_value), .Q (active_interrupt), .C (clk)); (* HBLKNM = "kcpsm6_decode1" *) FD interrupt_ack_flop ( .D (active_interrupt), .Q (interrupt_ack), .C (clk)); // /////////////////////////////////////////////////////////////////////////////////////////// // // Decoders // // // 2 x LUT6 // 10 x LUT6_2 // 2 x FD // 6 x FDR // /////////////////////////////////////////////////////////////////////////////////////////// // // // Decoding for Program Counter and Stack // (* HBLKNM = "kcpsm6_decode0" *) LUT6 #( .INIT (64'h5A3CFFFF00000000)) pc_move_is_valid_lut( .I0 (carry_flag), .I1 (zero_flag), .I2 (instruction[14]), .I3 (instruction[15]), .I4 (instruction[16]), .I5 (instruction[17]), .O (pc_move_is_valid)) ; (* HBLKNM = "kcpsm6_decode0" *) LUT6_2 # ( .INIT (64'h7777027700000200)) move_type_lut( .I0 (instruction[12]), .I1 (instruction[13]), .I2 (instruction[14]), .I3 (instruction[15]), .I4 (instruction[16]), .I5 (1'b1), .O5 (returni_type), .O6 (move_type)) ; (* HBLKNM = "kcpsm6_vector1" *) LUT6_2 # ( .INIT (64'h0000F000000023FF)) pc_mode1_lut( .I0 (instruction[12]), .I1 (returni_type), .I2 (move_type), .I3 (pc_move_is_valid), .I4 (active_interrupt), .I5 (1'b1), .O5 (pc_mode[0]), .O6 (pc_mode[1])) ; (* HBLKNM = "kcpsm6_vector1" *) LUT6 # ( .INIT (64'hFFFFFFFF00040000)) pc_mode2_lut( .I0 (instruction[12]), .I1 (instruction[14]), .I2 (instruction[15]), .I3 (instruction[16]), .I4 (instruction[17]), .I5 (active_interrupt), .O (pc_mode[2])) ; (* HBLKNM = "kcpsm6_stack1" *) LUT6_2 # ( .INIT (64'hFFFF100000002000)) push_pop_lut( .I0 (instruction[12]), .I1 (instruction[13]), .I2 (move_type), .I3 (pc_move_is_valid), .I4 (active_interrupt), .I5 (1'b1), .O5 (pop_stack), .O6 (push_stack)) ; // // Decoding for ALU // (* HBLKNM = "kcpsm6_decode2" *) LUT6_2 #( .INIT (64'h03CA000004200000)) alu_decode0_lut( .I0 (instruction[13]), .I1 (instruction[14]), .I2 (instruction[15]), .I3 (instruction[16]), .I4 (1'b1), .I5 (1'b1), .O5 (alu_mux_sel_value[0]), .O6 (arith_logical_sel[0])) ; (* HBLKNM = "kcpsm6_decode2" *) FD alu_mux_sel0_flop( .D (alu_mux_sel_value[0]), .Q (alu_mux_sel[0]), .C (clk)) ; (* HBLKNM = "kcpsm6_decode1" *) LUT6_2 #( .INIT (64'h7708000000000F00)) alu_decode1_lut( .I0 (carry_flag), .I1 (instruction[13]), .I2 (instruction[14]), .I3 (instruction[15]), .I4 (instruction[16]), .I5 (1'b1), .O5 (alu_mux_sel_value[1]), .O6 (arith_carry_in)) ; (* HBLKNM = "kcpsm6_decode1" *) FD alu_mux_sel1_flop ( .D (alu_mux_sel_value[1]), .Q (alu_mux_sel[1]), .C (clk)) ; (* HBLKNM = "kcpsm6_decode2" *) LUT6_2 # ( .INIT (64'hD000000002000000)) alu_decode2_lut( .I0 (instruction[14]), .I1 (instruction[15]), .I2 (instruction[16]), .I3 (1'b1), .I4 (1'b1), .I5 (1'b1), .O5 (arith_logical_sel[1]), .O6 (arith_logical_sel[2])) ; // // Decoding for strobes and enables // (* HBLKNM = "kcpsm6_strobes" *) LUT6_2 # ( .INIT (64'h00013F3F0010F7CE)) register_enable_type_lut( .I0 (instruction[13]), .I1 (instruction[14]), .I2 (instruction[15]), .I3 (instruction[16]), .I4 (instruction[17]), .I5 (1'b1), .O5 (flag_enable_type), .O6 (register_enable_type)) ; (* HBLKNM = "kcpsm6_strobes" *) LUT6_2 # ( .INIT (64'hC0CC0000A0AA0000)) register_enable_lut( .I0 (flag_enable_type), .I1 (register_enable_type), .I2 (instruction[12]), .I3 (instruction[17]), .I4 (t_state[1]), .I5 (1'b1), .O5 (flag_enable_value), .O6 (register_enable_value)) ; (* HBLKNM = "kcpsm6_strobes" *) FDR flag_enable_flop ( .D (flag_enable_value), .Q (flag_enable), .R (active_interrupt), .C (clk)) ; (* HBLKNM = "kcpsm6_strobes" *) FDR register_enable_flop ( .D (register_enable_value), .Q (register_enable), .R (active_interrupt), .C (clk)) ; (* HBLKNM = "kcpsm6_strobes" *) LUT6_2 # ( .INIT (64'h8000000020000000)) spm_enable_lut( .I0 (instruction[13]), .I1 (instruction[14]), .I2 (instruction[17]), .I3 (strobe_type), .I4 (t_state[1]), .I5 (1'b1), .O5 (k_write_strobe_value), .O6 (spm_enable_value)) ; (* HBLKNM = "kcpsm6_strobes" *) FDR k_write_strobe_flop ( .D (k_write_strobe_value), .Q (k_write_strobe), .R (active_interrupt), .C (clk)) ; (* HBLKNM = "kcpsm6_strobes" *) FDR spm_enable_flop ( .D (spm_enable_value), .Q (spm_enable), .R (active_interrupt), .C (clk)) ; (* HBLKNM = "kcpsm6_strobes" *) LUT6_2 # ( .INIT (64'h4000000001000000)) read_strobe_lut( .I0 (instruction[13]), .I1 (instruction[14]), .I2 (instruction[17]), .I3 (strobe_type), .I4 (t_state[1]), .I5 (1'b1), .O5 (read_strobe_value), .O6 (write_strobe_value)) ; (* HBLKNM = "kcpsm6_strobes" *) FDR write_strobe_flop ( .D (write_strobe_value), .Q (write_strobe), .R (active_interrupt), .C (clk)) ; (* HBLKNM = "kcpsm6_strobes" *) FDR read_strobe_flop ( .D (read_strobe_value), .Q (read_strobe), .R (active_interrupt), .C (clk)) ; // /////////////////////////////////////////////////////////////////////////////////////////// // // Register bank control // // // 2 x LUT6 // 1 x FDR // 1 x FD // /////////////////////////////////////////////////////////////////////////////////////////// // (* HBLKNM = "kcpsm6_stack1" *) LUT6 # ( .INIT (64'h0080020000000000)) regbank_type_lut( .I0 (instruction[12]), .I1 (instruction[13]), .I2 (instruction[14]), .I3 (instruction[15]), .I4 (instruction[16]), .I5 (instruction[17]), .O (regbank_type)) ; (* HBLKNM = "kcpsm6_stack1" *) LUT6 # ( .INIT (64'hACACFF00FF00FF00)) bank_lut( .I0 (instruction[0]), .I1 (shadow_bank), .I2 (instruction[16]), .I3 (bank), .I4 (regbank_type), .I5 (t_state[1]), .O (bank_value)) ; (* HBLKNM = "kcpsm6_stack1" *) FDR bank_flop ( .D (bank_value), .Q (bank), .R (internal_reset), .C (clk)) ; (* HBLKNM = "kcpsm6_control" *) FD sx_addr4_flop ( .D (sx_addr4_value), .Q (sx_addr[4]), .C (clk)) ; assign sx_addr[3:0] = instruction[11:8] ; assign sy_addr = {bank, instruction[7:4]} ; // /////////////////////////////////////////////////////////////////////////////////////////// // // Flags // // // 3 x LUT6 // 5 x LUT6_2 // 3 x FD // 2 x FDRE // 2 x XORCY // 5 x MUXCY // /////////////////////////////////////////////////////////////////////////////////////////// // (* HBLKNM = "kcpsm6_control" *) XORCY arith_carry_xorcy ( .LI (1'b0), .CI (carry_arith_logical[7]), .O (arith_carry_value)) ; (* HBLKNM = "kcpsm6_control" *) FD arith_carry_flop ( .D (arith_carry_value), .Q (arith_carry), .C (clk)) ; (* HBLKNM = "kcpsm6_decode2" *) LUT6_2 # ( .INIT (64'h0000000087780000)) lower_parity_lut( .I0 (instruction[13]), .I1 (carry_flag), .I2 (arith_logical_result[0]), .I3 (arith_logical_result[1]), .I4 (1'b1), .I5 (1'b1), .O5 (lower_parity), .O6 (lower_parity_sel)) ; (* HBLKNM = "kcpsm6_decode2" *) MUXCY parity_muxcy ( .DI (lower_parity), .CI (1'b0), .S (lower_parity_sel), .O (carry_lower_parity)) ; (* HBLKNM = "kcpsm6_decode2" *) LUT6 #( .INIT (64'h6996966996696996)) upper_parity_lut( .I0 (arith_logical_result[2]), .I1 (arith_logical_result[3]), .I2 (arith_logical_result[4]), .I3 (arith_logical_result[5]), .I4 (arith_logical_result[6]), .I5 (arith_logical_result[7]), .O (upper_parity)) ; (* HBLKNM = "kcpsm6_decode2" *) XORCY parity_xorcy( .LI (upper_parity), .CI (carry_lower_parity), .O (parity)) ; (* HBLKNM = "kcpsm6_decode1" *) LUT6 #( .INIT (64'hFFFFAACCF0F0F0F0)) shift_carry_lut( .I0 (sx[0]), .I1 (sx[7]), .I2 (shadow_carry_flag), .I3 (instruction[3]), .I4 (instruction[7]), .I5 (instruction[16]), .O (shift_carry_value)) ; (* HBLKNM = "kcpsm6_decode1" *) FD shift_carry_flop( .D (shift_carry_value), .Q (shift_carry), .C (clk)) ; (* HBLKNM = "kcpsm6_flags" *) LUT6_2 #( .INIT (64'h3333AACCF0AA0000)) carry_flag_lut( .I0 (shift_carry), .I1 (arith_carry), .I2 (parity), .I3 (instruction[14]), .I4 (instruction[15]), .I5 (instruction[16]), .O5 (drive_carry_in_zero), .O6 (carry_flag_value)) ; (* HBLKNM = "kcpsm6_flags" *) FDRE carry_flag_flop( .D (carry_flag_value), .Q (carry_flag), .CE (flag_enable), .R (internal_reset), .C (clk)) ; (* HBLKNM = "kcpsm6_flags" *) MUXCY init_zero_muxcy( .DI (drive_carry_in_zero), .CI (1'b0), .S (carry_flag_value), .O (carry_in_zero)) ; (* HBLKNM = "kcpsm6_decode1" *) LUT6_2 # ( .INIT (64'hA280000000F000F0)) use_zero_flag_lut( .I0 (instruction[13]), .I1 (instruction[14]), .I2 (instruction[15]), .I3 (instruction[16]), .I4 (1'b1), .I5 (1'b1), .O5 (strobe_type), .O6 (use_zero_flag_value)) ; (* HBLKNM = "kcpsm6_decode1" *) FD use_zero_flag_flop( .D (use_zero_flag_value), .Q (use_zero_flag), .C (clk)) ; (* HBLKNM = "kcpsm6_flags" *) LUT6_2 #( .INIT (64'h0000000000000001)) lower_zero_lut( .I0 (alu_result[0]), .I1 (alu_result[1]), .I2 (alu_result[2]), .I3 (alu_result[3]), .I4 (alu_result[4]), .I5 (1'b1), .O5 (lower_zero), .O6 (lower_zero_sel)) ; (* HBLKNM = "kcpsm6_flags" *) MUXCY lower_zero_muxcy( .DI (lower_zero), .CI (carry_in_zero), .S (lower_zero_sel), .O (carry_lower_zero)) ; (* HBLKNM = "kcpsm6_flags" *) LUT6_2 # ( .INIT (64'h0000000D00000000)) middle_zero_lut( .I0 (use_zero_flag), .I1 (zero_flag), .I2 (alu_result[5]), .I3 (alu_result[6]), .I4 (alu_result[7]), .I5 (1'b1), .O5 (middle_zero), .O6 (middle_zero_sel)) ; (* HBLKNM = "kcpsm6_flags" *) MUXCY middle_zero_muxcy( .DI (middle_zero), .CI (carry_lower_zero), .S (middle_zero_sel), .O (carry_middle_zero)) ; (* HBLKNM = "kcpsm6_flags" *) LUT6 #( .INIT (64'hFBFF000000000000)) upper_zero_lut( .I0 (instruction[14]), .I1 (instruction[15]), .I2 (instruction[16]), .I3 (1'b1), .I4 (1'b1), .I5 (1'b1), .O (upper_zero_sel)) ; (* HBLKNM = "kcpsm6_flags" *) MUXCY upper_zero_muxcy( .DI (shadow_zero_flag), .CI (carry_middle_zero), .S (upper_zero_sel), .O (zero_flag_value)) ; (* HBLKNM = "kcpsm6_flags" *) FDRE zero_flag_flop( .D (zero_flag_value), .Q (zero_flag), .CE (flag_enable), .R (internal_reset), .C (clk)) ; // /////////////////////////////////////////////////////////////////////////////////////////// // // 12-bit Program Address Generation // /////////////////////////////////////////////////////////////////////////////////////////// // // // Prepare 12-bit vector from the sX and sY register outputs. // assign register_vector = {sx[3:0], sy} ; genvar i ; generate for (i = 0 ; i <= 11 ; i = i+1) begin : address_loop parameter [7:0] id4 = 8'h30 + i/4 ; parameter [7:0] id8 = 8'h30 + i/8 ; parameter [7:0] ip4d8 = 8'h30 + (i+4)/8 ; // /////////////////////////////////////////////////////////////////////////////////////////// // // Selection of vector to load program counter // // instruction[12] // 0 Constant aaa from instruction(11:0) // 1 Return vector from stack // // 'aaa' is used during 'JUMP aaa', 'JUMP c, aaa', 'CALL aaa' and 'CALL c, aaa'. // Return vector is used during 'RETURN', 'RETURN c', 'RETURN&LOAD' and 'RETURNI'. // // 6 x LUT6_2 // 12 x FD // /////////////////////////////////////////////////////////////////////////////////////////// // // // Pipeline output of the stack memory // (* HBLKNM = {"kcpsm6_stack_ram",ip4d8} *) FD return_vector_flop( .D (stack_memory[i]), .Q (return_vector[i]), .C (clk)); // // Multiplex instruction constant address and output from stack. // 2 bits per LUT so only generate when 'i' is even. // if (i % 2 == 0) begin: output_data (* HBLKNM = {"kcpsm6_vector",id8} *) LUT6_2 #( .INIT (64'hFF00F0F0CCCCAAAA)) pc_vector_mux_lut( .I0 (instruction[i]), .I1 (return_vector[i]), .I2 (instruction[i+1]), .I3 (return_vector[i+1]), .I4 (instruction[12]), .I5 (1'b1), .O5 (pc_vector[i]), .O6 (pc_vector[i+1])); end //output_data // /////////////////////////////////////////////////////////////////////////////////////////// // // Program Counter // // Reset by internal_reset has highest priority. // Enabled by t_state[1] has second priority. // // The function performed is defined by pc_mode(2:0). // // pc_mode [2] [1] [0] // 0 0 1 pc+1 for normal program flow. // 1 0 0 Forces interrupt vector value (+0) during active interrupt. // The vector is defined by a generic with default value FF0 hex. // 1 1 0 register_vector (+0) for 'JUMP (sX, sY)' and 'CALL (sX, sY)'. // 0 1 0 pc_vector (+0) for 'JUMP/CALL aaa' and 'RETURNI'. // 0 1 1 pc_vector+1 for 'RETURN'. // // Note that pc_mode[0] is High during operations that require an increment to occur. // The LUT6 associated with the LSB must invert pc or pc_vector in these cases and // pc_mode[0] also has to be connected to the start of the carry chain. // // 3 Slices // 12 x LUT6 // 11 x MUXCY // 12 x XORCY // 12 x FDRE // /////////////////////////////////////////////////////////////////////////////////////////// // (* HBLKNM = {"kcpsm6_pc",id4} *) FDRE pc_flop( .D (pc_value[i]), .Q (pc[i]), .R (internal_reset), .CE (t_state[1]), .C (clk)); if (i == 0) begin: lsb_pc // // Logic of LSB must invert selected value when pc_mode[0] is High. // The interrupt vector is defined by a generic. // if (interrupt_vector[i] == 1'b0) begin: low_int_vector (* HBLKNM = {"kcpsm6_pc",id4} *) LUT6 #( .INIT (64'h00AA000033CC0F00)) pc_lut( .I0 (register_vector[i]), .I1 (pc_vector[i]), .I2 (pc[i]), .I3 (pc_mode[0]), .I4 (pc_mode[1]), .I5 (pc_mode[2]), .O (half_pc[i])); end //low_int_vector if (interrupt_vector[i] == 1'b1) begin: high_int_vector (* HBLKNM = {"kcpsm6_pc",id4} *) LUT6 #( .INIT (64'h00AA00FF33CC0F00)) pc_lut( .I0 (register_vector[i]), .I1 (pc_vector[i]), .I2 (pc[i]), .I3 (pc_mode[0]), .I4 (pc_mode[1]), .I5 (pc_mode[2]), .O (half_pc[i])); end //high_int_vector // // pc_mode[0] connected to first MUXCY and carry input is 1'b0 // (* HBLKNM = {"kcpsm6_pc",id4} *) XORCY pc_xorcy( .LI (half_pc[i]), .CI (1'b0), .O (pc_value[i])); (* HBLKNM = {"kcpsm6_pc",id4} *) MUXCY pc_muxcy( .DI (pc_mode[0]), .CI (1'b0), .S (half_pc[i]), .O (carry_pc[i])); end //lsb_pc if (i > 0) begin : upper_pc // // Logic of upper section selects required value. // The interrupt vector is defined by a generic. // if (interrupt_vector[i] == 1'b0) begin: low_int_vector (* HBLKNM = {"kcpsm6_pc",id4} *) LUT6 #( .INIT (64'h00AA0000CCCCF000)) pc_lut( .I0 (register_vector[i]), .I1 (pc_vector[i]), .I2 (pc[i]), .I3 (pc_mode[0]), .I4 (pc_mode[1]), .I5 (pc_mode[2]), .O (half_pc[i])); end //low_int_vector if (interrupt_vector[i] == 1'b1) begin: high_int_vector (* HBLKNM = {"kcpsm6_pc",id4} *) LUT6 #( .INIT (64'h00AA00FFCCCCF000)) pc_lut( .I0 (register_vector[i]), .I1 (pc_vector[i]), .I2 (pc[i]), .I3 (pc_mode[0]), .I4 (pc_mode[1]), .I5 (pc_mode[2]), .O (half_pc[i])); end //high_int_vector // // Carry chain implementing remainder of increment function // (* HBLKNM = {"kcpsm6_pc",id4} *) XORCY pc_xorcy( .LI (half_pc[i]), .CI (carry_pc[i-1]), .O (pc_value[i])); // // No MUXCY required at the top of the chain // if (i < 11) begin: mid_pc (* HBLKNM = {"kcpsm6_pc",id4} *) MUXCY pc_muxcy( .DI (1'b0), .CI (carry_pc[i-1]), .S (half_pc[i]), .O (carry_pc[i])); end //mid_pc end //upper_pc // /////////////////////////////////////////////////////////////////////////////////////////// // end //address_loop endgenerate // /////////////////////////////////////////////////////////////////////////////////////////// // // Stack // Preserves upto 31 nested values of the Program Counter during CALL and RETURN. // Also preserves flags and bank selection during interrupt. // // 2 x RAM32M // 4 x FD // 5 x FDR // 1 x LUT6 // 4 x LUT6_2 // 5 x XORCY // 5 x MUXCY // /////////////////////////////////////////////////////////////////////////////////////////// // (* HBLKNM = "kcpsm6_stack_ram0" *) FD shadow_carry_flag_flop( .D (stack_carry_flag), .Q (shadow_carry_flag), .C (clk)) ; (* HBLKNM = "kcpsm6_stack_ram0" *) FD stack_zero_flop( .D (stack_zero_flag), .Q (shadow_zero_value), .C (clk)) ; (* HBLKNM = "kcpsm6_decode1" *) FD shadow_zero_flag_flop( .D (shadow_zero_value), .Q (shadow_zero_flag), .C (clk)) ; (* HBLKNM = "kcpsm6_stack_ram0" *) FD shadow_bank_flop( .D (stack_bank), .Q (shadow_bank), .C (clk)) ; (* HBLKNM = "kcpsm6_stack_ram0" *) FD stack_bit_flop( .D (stack_bit), .Q (special_bit), .C (clk)) ; (* HBLKNM = "kcpsm6_stack_ram0" *) RAM32M #( .INIT_A (64'h0000000000000000), .INIT_B (64'h0000000000000000), .INIT_C (64'h0000000000000000), .INIT_D (64'h0000000000000000)) stack_ram_low ( .DOA ({stack_zero_flag, stack_carry_flag}), .DOB ({stack_bit, stack_bank}), .DOC (stack_memory[1:0]), .DOD (stack_memory[3:2]), .ADDRA (stack_pointer[4:0]), .ADDRB (stack_pointer[4:0]), .ADDRC (stack_pointer[4:0]), .ADDRD (stack_pointer[4:0]), .DIA ({zero_flag, carry_flag}), .DIB ({run, bank}), .DIC (pc[1:0]), .DID (pc[3:2]), .WE (t_state[1]), .WCLK (clk)); (* HBLKNM = "kcpsm6_stack_ram1" *) RAM32M #( .INIT_A (64'h0000000000000000), .INIT_B (64'h0000000000000000), .INIT_C (64'h0000000000000000), .INIT_D (64'h0000000000000000)) stack_ram_high( .DOA (stack_memory[5:4]), .DOB (stack_memory[7:6]), .DOC (stack_memory[9:8]), .DOD (stack_memory[11:10]), .ADDRA (stack_pointer[4:0]), .ADDRB (stack_pointer[4:0]), .ADDRC (stack_pointer[4:0]), .ADDRD (stack_pointer[4:0]), .DIA (pc[5:4]), .DIB (pc[7:6]), .DIC (pc[9:8]), .DID (pc[11:10]), .WE (t_state[1]), .WCLK (clk)); generate for (i = 0 ; i <= 4 ; i = i+1) begin : stack_loop parameter [7:0] id4 = 8'h30 + i/4 ; if (i == 0) begin: lsb_stack (* HBLKNM = {"kcpsm6_stack",id4} *) FDR pointer_flop( .D (stack_pointer_value[i]), .Q (stack_pointer[i]), .R (internal_reset), .C (clk)) ; (* HBLKNM = {"kcpsm6_stack",id4} *) LUT6_2 #( .INIT (64'h001529AAAAAAAAAA)) stack_pointer_lut( .I0 (stack_pointer[i]), .I1 (pop_stack), .I2 (push_stack), .I3 (t_state[1]), .I4 (t_state[2]), .I5 (1'b1), .O5 (feed_pointer_value[i]), .O6 (half_pointer_value[i])); (* HBLKNM = {"kcpsm6_stack",id4} *) XORCY stack_xorcy( .LI (half_pointer_value[i]), .CI (1'b0), .O (stack_pointer_value[i])); (* HBLKNM = {"kcpsm6_stack",id4} *) MUXCY stack_muxcy( .DI (feed_pointer_value[i]), .CI (1'b0), .S (half_pointer_value[i]), .O (stack_pointer_carry[i])); end //lsb_stack if (i > 0) begin: upper_stack (* HBLKNM = {"kcpsm6_stack",id4} *) FDR pointer_flop( .D (stack_pointer_value[i]), .Q (stack_pointer[i]), .R (internal_reset), .C (clk)) ; (* HBLKNM = {"kcpsm6_stack",id4} *) LUT6_2 #( .INIT (64'h002A252AAAAAAAAA)) stack_pointer_lut( .I0 (stack_pointer[i]), .I1 (pop_stack), .I2 (push_stack), .I3 (t_state[1]), .I4 (t_state[2]), .I5 (1'b1), .O5 (feed_pointer_value[i]), .O6 (half_pointer_value[i])); (* HBLKNM = {"kcpsm6_stack",id4} *) XORCY stack_xorcy( .LI (half_pointer_value[i]), .CI (stack_pointer_carry[i-1]), .O (stack_pointer_value[i])); (* HBLKNM = {"kcpsm6_stack",id4} *) MUXCY stack_muxcy( .DI (feed_pointer_value[i]), .CI (stack_pointer_carry[i-1]), .S (half_pointer_value[i]), .O (stack_pointer_carry[i])); end //upper_stack end //stack_loop endgenerate // /////////////////////////////////////////////////////////////////////////////////////////// // // 8-bit Data Path // /////////////////////////////////////////////////////////////////////////////////////////// // generate for (i = 0 ; i <= 7 ; i = i+1) begin : data_path_loop parameter [7:0] id1 = 8'h30 + i ; parameter [7:0] id2 = 8'h30 + i/2 ; parameter [7:0] id4 = 8'h30 + i/4 ; // /////////////////////////////////////////////////////////////////////////////////////////// // // Selection of second operand to ALU and port_id // // instruction[12] // 0 Register sY // 1 Constant kk // // 4 x LUT6_2 // /////////////////////////////////////////////////////////////////////////////////////////// // // // 2 bits per LUT so only generate when 'i' is even // if (i % 2 == 0) begin: output_data (* HBLKNM = "kcpsm6_port_id" *) LUT6_2 #( .INIT (64'hFF00F0F0CCCCAAAA)) sy_kk_mux_lut( .I0 (sy[i]), .I1 (instruction[i]), .I2 (sy[i+1]), .I3 (instruction[i+1]), .I4 (instruction[12]), .I5 (1'b1), .O5 (sy_or_kk[i]), .O6 (sy_or_kk[i+1])); end //output_data // /////////////////////////////////////////////////////////////////////////////////////////// // // Selection of out_port value // // instruction[13] // 0 Register sX // 1 Constant kk from instruction(11:4) // // 4 x LUT6_2 // /////////////////////////////////////////////////////////////////////////////////////////// // // // 2 bits per LUT so only generate when 'i' is even // if (i % 2 == 0) begin: second_operand (* HBLKNM = "kcpsm6_out_port" *) LUT6_2 #( .INIT (64'hFF00F0F0CCCCAAAA)) out_port_lut( .I0 (sx[i]), .I1 (instruction[i+4]), .I2 (sx[i+1]), .I3 (instruction[i+5]), .I4 (instruction[13]), .I5 (1'b1), .O5 (out_port[i]), .O6 (out_port[i+1])); end //second_operand; // /////////////////////////////////////////////////////////////////////////////////////////// // // Arithmetic and Logical operations // // Definition of.... // ADD and SUB also used for ADDCY, SUBCY, COMPARE and COMPARECY. // LOAD, AND, OR and XOR also used for LOAD*, RETURN&LOAD, TEST and TESTCY. // // arith_logical_sel [2] [1] [0] // 0 0 0 - LOAD // 0 0 1 - AND // 0 1 0 - OR // 0 1 1 - XOR // 1 X 0 - SUB // 1 X 1 - ADD // // Includes pipeline stage. // // 2 Slices // 8 x LUT6_2 // 8 x MUXCY // 8 x XORCY // 8 x FD // /////////////////////////////////////////////////////////////////////////////////////////// // (* HBLKNM = {"kcpsm6_add",id4} *) LUT6_2 #( .INIT (64'h69696E8ACCCC0000)) arith_logical_lut( .I0 (sy_or_kk[i]), .I1 (sx[i]), .I2 (arith_logical_sel[0]), .I3 (arith_logical_sel[1]), .I4 (arith_logical_sel[2]), .I5 (1'b1), .O5 (logical_carry_mask[i]), .O6 (half_arith_logical[i])); (* HBLKNM = {"kcpsm6_add",id4} *) FD arith_logical_flop( .D (arith_logical_value[i]), .Q (arith_logical_result[i]), .C (clk)) ; if (i == 0) begin: lsb_arith_logical // // Carry input to first MUXCY and XORCY // (* HBLKNM = {"kcpsm6_add",id4} *) MUXCY arith_logical_muxcy( .DI (logical_carry_mask[i]), .CI (arith_carry_in), .S (half_arith_logical[i]), .O (carry_arith_logical[i])); (* HBLKNM = {"kcpsm6_add",id4} *) XORCY arith_logical_xorcy( .LI (half_arith_logical[i]), .CI (arith_carry_in), .O (arith_logical_value[i])); end //lsb_arith_logical if (i > 0) begin: upper_arith_logical // // Main carry chain // (* HBLKNM = {"kcpsm6_add",id4} *) MUXCY arith_logical_muxcy( .DI (logical_carry_mask[i]), .CI (carry_arith_logical[i-1]), .S (half_arith_logical[i]), .O (carry_arith_logical[i])); (* HBLKNM = {"kcpsm6_add",id4} *) XORCY arith_logical_xorcy( .LI (half_arith_logical[i]), .CI (carry_arith_logical[i-1]), .O (arith_logical_value[i])); end //upper_arith_logical; // /////////////////////////////////////////////////////////////////////////////////////////// // // Shift and Rotate operations // // Definition of SL0, SL1, SLX, SLA, RL, SR0, SR1, SRX, SRA, and RR // // instruction [3] [2] [1] [0] // 0 1 1 0 - SL0 // 0 1 1 1 - SL1 // 0 1 0 0 - SLX // 0 0 0 0 - SLA // 0 0 1 0 - RL // 1 1 1 0 - SR0 // 1 1 1 1 - SR1 // 1 0 1 0 - SRX // 1 0 0 0 - SRA // 1 1 0 0 - RR // // instruction[3] // 0 - Left // 1 - Right // // instruction [2] [1] Bit shifted in // 0 0 Carry_flag // 0 1 sX[7] // 1 0 sX[0] // 1 1 instruction[0] // // Includes pipeline stage. // // 4 x LUT6_2 // 1 x LUT6 // 8 x FD // /////////////////////////////////////////////////////////////////////////////////////////// // if (hwbuild[i] == 1'b0) begin: low_hwbuild // // Reset Flip-flop to form 1'b0 for this bit of HWBUILD // (* HBLKNM = "kcpsm6_sandr" *) FDR shift_rotate_flop( .D (shift_rotate_value[i]), .Q (shift_rotate_result[i]), .R (instruction[7]), .C (clk)) ; end // low_hwbuild; if (hwbuild[i] == 1'b1) begin: high_hwbuild // // Set Flip-flop to form 1'b1 for this bit of HWBUILD // (* HBLKNM = "kcpsm6_sandr" *) FDS shift_rotate_flop( .D (shift_rotate_value[i]), .Q (shift_rotate_result[i]), .S (instruction[7]), .C (clk)) ; end // high_hwbuild; if (i == 0) begin: lsb_shift_rotate // // Select bit to be shifted or rotated into result // (* HBLKNM = "kcpsm6_decode1" *) LUT6 #( .INIT (64'hBFBC8F8CB3B08380)) shift_bit_lut( .I0 (instruction[0]), .I1 (instruction[1]), .I2 (instruction[2]), .I3 (carry_flag), .I4 (sx[0]), .I5 (sx[7]), .O (shift_in_bit)); // // Define lower bits of result // (* HBLKNM = "kcpsm6_sandr" *) LUT6_2 #( .INIT (64'hFF00F0F0CCCCAAAA)) shift_rotate_lut( .I0 (shift_in_bit), .I1 (sx[i+1]), .I2 (sx[i]), .I3 (sx[i+2]), .I4 (instruction[3]), .I5 (1'b1), .O5 (shift_rotate_value[i]), .O6 (shift_rotate_value[i+1])); end // lsb_shift_rotate; if (i == 2 || i == 4) begin: mid_shift_rotate // // Define middle bits of result // (* HBLKNM = "kcpsm6_sandr" *) LUT6_2 #( .INIT (64'hFF00F0F0CCCCAAAA)) shift_rotate_lut( .I0 (sx[i-1]), .I1 (sx[i+1]), .I2 (sx[i]), .I3 (sx[i+2]), .I4 (instruction[3]), .I5 (1'b1), .O5 (shift_rotate_value[i]), .O6 (shift_rotate_value[i+1])); end // mid_shift_rotate; if (i == 6) begin: msb_shift_rotate // // Define upper bits of result // (* HBLKNM = "kcpsm6_sandr" *) LUT6_2 #( .INIT (64'hFF00F0F0CCCCAAAA)) shift_rotate_lut( .I0 (sx[i-1]), .I1 (sx[i+1]), .I2 (sx[i]), .I3 (shift_in_bit), .I4 (instruction[3]), .I5 (1'b1), .O5 (shift_rotate_value[i]), .O6 (shift_rotate_value[i+1])); end // msb_shift_rotate; // /////////////////////////////////////////////////////////////////////////////////////////// // // Multiplex outputs from ALU functions, scratch pad memory and input port. // // alu_mux_sel [1] [0] // 0 0 Arithmetic and Logical Instructions // 0 1 Shift and Rotate Instructions // 1 0 Input Port // 1 1 Scratch Pad Memory // // 8 x LUT6 // /////////////////////////////////////////////////////////////////////////////////////////// // (* HBLKNM = {"kcpsm6_alu",id4} *) LUT6 #( .INIT (64'hFF00F0F0CCCCAAAA)) alu_mux_lut( .I0 (arith_logical_result[i]), .I1 (shift_rotate_result[i]), .I2 (in_port[i]), .I3 (spm_data[i]), .I4 (alu_mux_sel[0]), .I5 (alu_mux_sel[1]), .O (alu_result[i])); // /////////////////////////////////////////////////////////////////////////////////////////// // // Scratchpad Memory with output register. // // The size of the scratch pad memory is defined by the 'scratch_pad_memory_size' generic. // The default size is 64 bytes the same as KCPSM3 but this can be increased to 128 or 256 // bytes at an additional cost of 2 and 6 Slices. // // // 8 x RAM256X1S (256 bytes). // 8 x RAM128X1S (128 bytes). // 2 x RAM64M (64 bytes). // // 8 x FD. // /////////////////////////////////////////////////////////////////////////////////////////// // if (scratch_pad_memory_size == 64) begin : small_spm (* HBLKNM = {"kcpsm6_spm",id4} *) FD spm_flop( .D (spm_ram_data[i]), .Q (spm_data[i]), .C (clk)) ; if (i == 0 || i == 4) begin: small_spm_ram RAM64M #( .INIT_A (64'h0000000000000000), .INIT_B (64'h0000000000000000), .INIT_C (64'h0000000000000000), .INIT_D (64'h0000000000000000)) spm_ram( .DOA (spm_ram_data[i]), .DOB (spm_ram_data[i+1]), .DOC (spm_ram_data[i+2]), .DOD (spm_ram_data[i+3]), .ADDRA (sy_or_kk[5:0]), .ADDRB (sy_or_kk[5:0]), .ADDRC (sy_or_kk[5:0]), .ADDRD (sy_or_kk[5:0]), .DIA (sx[i]), .DIB (sx[i+1]), .DIC (sx[i+2]), .DID (sx[i+3]), .WE (spm_enable), .WCLK (clk)); end // small_spm_ram; end // small_spm; if (scratch_pad_memory_size == 128) begin : medium_spm (* HBLKNM = {"kcpsm6_spm",id2} *) RAM128X1S #( .INIT (128'h00000000000000000000000000000000)) spm_ram( .D (sx[i]), .WE (spm_enable), .WCLK (clk), .A0 (sy_or_kk[0]), .A1 (sy_or_kk[1]), .A2 (sy_or_kk[2]), .A3 (sy_or_kk[3]), .A4 (sy_or_kk[4]), .A5 (sy_or_kk[5]), .A6 (sy_or_kk[6]), .O (spm_ram_data[i])); (* HBLKNM = {"kcpsm6_spm",id2} *) FD spm_flop( .D (spm_ram_data[i]), .Q (spm_data[i]), .C (clk)) ; end // medium_spm; if (scratch_pad_memory_size == 256) begin : large_spm (* HBLKNM = {"kcpsm6_spm",id1} *) RAM256X1S #( .INIT (256'h0000000000000000000000000000000000000000000000000000000000000000)) spm_ram ( .D (sx[i]), .WE (spm_enable), .WCLK (clk), .A (sy_or_kk), .O (spm_ram_data[i])); (* HBLKNM = {"kcpsm6_spm",id1} *) FD spm_flop( .D (spm_ram_data[i]), .Q (spm_data[i]), .C (clk)) ; end // large_spm; // /////////////////////////////////////////////////////////////////////////////////////////// // end // data_path_loop; endgenerate // /////////////////////////////////////////////////////////////////////////////////////////// // // Two Banks of 16 General Purpose Registers. // // sx_addr - Address for sX is formed by bank select and instruction[11:8] // sy_addr - Address for sY is formed by bank select and instruction[7:4] // // 2 Slices // 2 x RAM32M // /////////////////////////////////////////////////////////////////////////////////////////// // (* HBLKNM = "kcpsm6_reg0" *) RAM32M #( .INIT_A (64'h0000000000000000), .INIT_B (64'h0000000000000000), .INIT_C (64'h0000000000000000), .INIT_D (64'h0000000000000000)) lower_reg_banks( .DOA (sy[1:0]), .DOB (sx[1:0]), .DOC (sy[3:2]), .DOD (sx[3:2]), .ADDRA (sy_addr), .ADDRB (sx_addr), .ADDRC (sy_addr), .ADDRD (sx_addr), .DIA (alu_result[1:0]), .DIB (alu_result[1:0]), .DIC (alu_result[3:2]), .DID (alu_result[3:2]), .WE (register_enable), .WCLK (clk)); (* HBLKNM = "kcpsm6_reg1" *) RAM32M #( .INIT_A (64'h0000000000000000), .INIT_B (64'h0000000000000000), .INIT_C (64'h0000000000000000), .INIT_D (64'h0000000000000000)) upper_reg_banks( .DOA (sy[5:4]), .DOB (sx[5:4]), .DOC (sy[7:6]), .DOD (sx[7:6]), .ADDRA (sy_addr), .ADDRB (sx_addr), .ADDRC (sy_addr), .ADDRD (sx_addr), .DIA (alu_result[5:4]), .DIB (alu_result[5:4]), .DIC (alu_result[7:6]), .DID (alu_result[7:6]), .WE (register_enable), .WCLK (clk)); // /////////////////////////////////////////////////////////////////////////////////////////// // // Connections to KCPSM6 outputs. // /////////////////////////////////////////////////////////////////////////////////////////// // assign address = pc; assign bram_enable = t_state[2]; // /////////////////////////////////////////////////////////////////////////////////////////// // // Connections KCPSM6 Outputs. // /////////////////////////////////////////////////////////////////////////////////////////// // assign port_id = sy_or_kk; // /////////////////////////////////////////////////////////////////////////////////////////// // // End of description for kcpsm6 macro. // /////////////////////////////////////////////////////////////////////////////////////////// // // ***************************************************** // * Code for simulation purposes only after this line * // ***************************************************** // // // Disassemble the instruction codes to form a text string for display. // Determine status of reset and flags and present in the form of a text string. // Provide signals to simulate the contents of each register and scratch pad memory // location. // /////////////////////////////////////////////////////////////////////////////////////////// // //All of this section is ignored during synthesis. //synthesis translate_off // // // Variables for contents of each register in each bank // reg [7:0] bank_a_s0 ; reg [7:0] bank_a_s1 ; reg [7:0] bank_a_s2 ; reg [7:0] bank_a_s3 ; reg [7:0] bank_a_s4 ; reg [7:0] bank_a_s5 ; reg [7:0] bank_a_s6 ; reg [7:0] bank_a_s7 ; reg [7:0] bank_a_s8 ; reg [7:0] bank_a_s9 ; reg [7:0] bank_a_sa ; reg [7:0] bank_a_sb ; reg [7:0] bank_a_sc ; reg [7:0] bank_a_sd ; reg [7:0] bank_a_se ; reg [7:0] bank_a_sf ; reg [7:0] bank_b_s0 ; reg [7:0] bank_b_s1 ; reg [7:0] bank_b_s2 ; reg [7:0] bank_b_s3 ; reg [7:0] bank_b_s4 ; reg [7:0] bank_b_s5 ; reg [7:0] bank_b_s6 ; reg [7:0] bank_b_s7 ; reg [7:0] bank_b_s8 ; reg [7:0] bank_b_s9 ; reg [7:0] bank_b_sa ; reg [7:0] bank_b_sb ; reg [7:0] bank_b_sc ; reg [7:0] bank_b_sd ; reg [7:0] bank_b_se ; reg [7:0] bank_b_sf ; // initial begin bank_a_s0 = 8'h00 ; bank_a_s1 = 8'h00 ; bank_a_s2 = 8'h00 ; bank_a_s3 = 8'h00 ; bank_a_s4 = 8'h00 ; bank_a_s5 = 8'h00 ; bank_a_s6 = 8'h00 ; bank_a_s7 = 8'h00 ; bank_a_s8 = 8'h00 ; bank_a_s9 = 8'h00 ; bank_a_sa = 8'h00 ; bank_a_sb = 8'h00 ; bank_a_sc = 8'h00 ; bank_a_sd = 8'h00 ; bank_a_se = 8'h00 ; bank_a_sf = 8'h00 ; bank_b_s0 = 8'h00 ; bank_b_s1 = 8'h00 ; bank_b_s2 = 8'h00 ; bank_b_s3 = 8'h00 ; bank_b_s4 = 8'h00 ; bank_b_s5 = 8'h00 ; bank_b_s6 = 8'h00 ; bank_b_s7 = 8'h00 ; bank_b_s8 = 8'h00 ; bank_b_s9 = 8'h00 ; bank_b_sa = 8'h00 ; bank_b_sb = 8'h00 ; bank_b_sc = 8'h00 ; bank_b_sd = 8'h00 ; bank_b_se = 8'h00 ; bank_b_sf = 8'h00 ; end // // Temporary variables for instruction decoding // wire [1:16] sx_decode ; //sX register specification wire [1:16] sy_decode ; //sY register specification wire [1:16] kk_decode ; //constant value specification wire [1:24] aaa_decode ; //address specification wire clk_del ; // Delayed clock for simulation // ///////////////////////////////////////////////////////////////////////////////////////// // // Function to convert 4-bit binary nibble to hexadecimal character // ///////////////////////////////////////////////////////////////////////////////////////// // function [1:8] hexcharacter ; input [3:0] nibble ; begin case (nibble) 4'b0000 : hexcharacter = "0" ; 4'b0001 : hexcharacter = "1" ; 4'b0010 : hexcharacter = "2" ; 4'b0011 : hexcharacter = "3" ; 4'b0100 : hexcharacter = "4" ; 4'b0101 : hexcharacter = "5" ; 4'b0110 : hexcharacter = "6" ; 4'b0111 : hexcharacter = "7" ; 4'b1000 : hexcharacter = "8" ; 4'b1001 : hexcharacter = "9" ; 4'b1010 : hexcharacter = "A" ; 4'b1011 : hexcharacter = "B" ; 4'b1100 : hexcharacter = "C" ; 4'b1101 : hexcharacter = "D" ; 4'b1110 : hexcharacter = "E" ; 4'b1111 : hexcharacter = "F" ; endcase end endfunction // ///////////////////////////////////////////////////////////////////////////////////////// // // decode first register sX assign sx_decode[1:8] = "s"; assign sx_decode[9:16] = hexcharacter(instruction[11:8]); // decode second register sY assign sy_decode[1:8] = "s"; assign sy_decode[9:16] = hexcharacter(instruction[7:4]); // decode constant value assign kk_decode[1:8] = hexcharacter(instruction[7:4]); assign kk_decode[9:16] = hexcharacter(instruction[3:0]); // address value assign aaa_decode[1:8] = hexcharacter(instruction[11:8]); assign aaa_decode[9:16] = hexcharacter(instruction[7:4]); assign aaa_decode[17:24] = hexcharacter(instruction[3:0]); assign #200 clk_del = clk ; // decode instruction //always @ (clk or instruction or carry_flag or zero_flag or bank or interrupt_enable) always @ (posedge clk_del) begin : simulation case (instruction[17:12]) 6'b000000 : kcpsm6_opcode <= {"LOAD ", sx_decode, ", ", sy_decode, " "} ; 6'b000001 : kcpsm6_opcode <= {"LOAD ", sx_decode, ", ", kk_decode, " "} ; 6'b010110 : kcpsm6_opcode <= {"STAR ", sx_decode, ", ", sy_decode, " "} ; 6'b000010 : kcpsm6_opcode <= {"AND ", sx_decode, ", ", sy_decode, " "} ; 6'b000011 : kcpsm6_opcode <= {"AND ", sx_decode, ", ", kk_decode, " "} ; 6'b000100 : kcpsm6_opcode <= {"OR ", sx_decode, ", ", sy_decode, " "} ; 6'b000101 : kcpsm6_opcode <= {"OR ", sx_decode, ", ", kk_decode, " "} ; 6'b000110 : kcpsm6_opcode <= {"XOR ", sx_decode, ", ", sy_decode, " "} ; 6'b000111 : kcpsm6_opcode <= {"XOR ", sx_decode, ", ", kk_decode, " "} ; 6'b001100 : kcpsm6_opcode <= {"TEST ", sx_decode, ", ", sy_decode, " "} ; 6'b001101 : kcpsm6_opcode <= {"TEST ", sx_decode, ", ", kk_decode, " "} ; 6'b001110 : kcpsm6_opcode <= {"TESTCY ", sx_decode, ", ", sy_decode, " "} ; 6'b001111 : kcpsm6_opcode <= {"TESTCY ", sx_decode, ", ", kk_decode, " "} ; 6'b010000 : kcpsm6_opcode <= {"ADD ", sx_decode, ", ", sy_decode, " "} ; 6'b010001 : kcpsm6_opcode <= {"ADD ", sx_decode, ", ", kk_decode, " "} ; 6'b010010 : kcpsm6_opcode <= {"ADDCY ", sx_decode, ", ", sy_decode, " "} ; 6'b010011 : kcpsm6_opcode <= {"ADDCY ", sx_decode, ", ", kk_decode, " "} ; 6'b011000 : kcpsm6_opcode <= {"SUB ", sx_decode, ", ", sy_decode, " "} ; 6'b011001 : kcpsm6_opcode <= {"SUB ", sx_decode, ", ", kk_decode, " "} ; 6'b011010 : kcpsm6_opcode <= {"SUBCY ", sx_decode, ", ", sy_decode, " "} ; 6'b011011 : kcpsm6_opcode <= {"SUBCY ", sx_decode, ", ", kk_decode, " "} ; 6'b011100 : kcpsm6_opcode <= {"COMPARE ", sx_decode, ", ", sy_decode, " "} ; 6'b011101 : kcpsm6_opcode <= {"COMPARE ", sx_decode, ", ", kk_decode, " "} ; 6'b011110 : kcpsm6_opcode <= {"COMPARECY ", sx_decode, ", ", sy_decode, " "} ; 6'b011111 : kcpsm6_opcode <= {"COMPARECY ", sx_decode, ", ", kk_decode, " "} ; 6'b010100 : begin if (instruction[7] == 1'b1) kcpsm6_opcode <= {"HWBUILD ", sx_decode, " "} ; else case (instruction[3:0]) 4'b0110 : kcpsm6_opcode <= {"SL0 ", sx_decode, " "} ; 4'b0111 : kcpsm6_opcode <= {"SL1 ", sx_decode, " "} ; 4'b0100 : kcpsm6_opcode <= {"SLX ", sx_decode, " "} ; 4'b0000 : kcpsm6_opcode <= {"SLA ", sx_decode, " "} ; 4'b0010 : kcpsm6_opcode <= {"RL ", sx_decode, " "} ; 4'b1110 : kcpsm6_opcode <= {"SR0 ", sx_decode, " "} ; 4'b1111 : kcpsm6_opcode <= {"SR1 ", sx_decode, " "} ; 4'b1010 : kcpsm6_opcode <= {"SRX ", sx_decode, " "} ; 4'b1000 : kcpsm6_opcode <= {"SRA ", sx_decode, " "} ; 4'b1100 : kcpsm6_opcode <= {"RR ", sx_decode, " "} ; default : kcpsm6_opcode <= "Invalid Instruction"; endcase end 6'b101100 : kcpsm6_opcode <= {"OUTPUT ", sx_decode, ", (", sy_decode, ") "} ; 6'b101101 : kcpsm6_opcode <= {"OUTPUT ", sx_decode, ", ", kk_decode, " "} ; 6'b101011 : kcpsm6_opcode <= {"OUTPUTK ", aaa_decode[1:16], ", ", aaa_decode[17:24], " " }; 6'b001000 : kcpsm6_opcode <= {"INPUT ", sx_decode, ", (", sy_decode, ") "} ; 6'b001001 : kcpsm6_opcode <= {"INPUT ", sx_decode, ", ", kk_decode, " "} ; 6'b101110 : kcpsm6_opcode <= {"STORE ", sx_decode, ", (", sy_decode, ") "} ; 6'b101111 : kcpsm6_opcode <= {"STORE ", sx_decode, ", ", kk_decode, " "} ; 6'b001010 : kcpsm6_opcode <= {"FETCH ", sx_decode, ", (", sy_decode, ") "} ; 6'b001011 : kcpsm6_opcode <= {"FETCH ", sx_decode, ", ", kk_decode, " "} ; 6'b100010 : kcpsm6_opcode <= {"JUMP ", aaa_decode, " "} ; 6'b110010 : kcpsm6_opcode <= {"JUMP Z, ", aaa_decode, " "} ; 6'b110110 : kcpsm6_opcode <= {"JUMP NZ, ", aaa_decode, " "} ; 6'b111010 : kcpsm6_opcode <= {"JUMP C, ", aaa_decode, " "} ; 6'b111110 : kcpsm6_opcode <= {"JUMP NC, ", aaa_decode, " "} ; 6'b100110 : kcpsm6_opcode <= {"JUMP@ (", sx_decode, ", ", sy_decode, ") "} ; 6'b100000 : kcpsm6_opcode <= {"CALL ", aaa_decode, " "} ; 6'b110000 : kcpsm6_opcode <= {"CALL Z, ", aaa_decode, " "} ; 6'b110100 : kcpsm6_opcode <= {"CALL NZ, ", aaa_decode, " "} ; 6'b111000 : kcpsm6_opcode <= {"CALL C, ", aaa_decode, " "} ; 6'b111100 : kcpsm6_opcode <= {"CALL NC, ", aaa_decode, " "} ; 6'b100100 : kcpsm6_opcode <= {"CALL@ (", sx_decode, ", ", sy_decode, ") "} ; 6'b100101 : kcpsm6_opcode <= {"RETURN "} ; 6'b110001 : kcpsm6_opcode <= {"RETURN Z "} ; 6'b110101 : kcpsm6_opcode <= {"RETURN NZ "} ; 6'b111001 : kcpsm6_opcode <= {"RETURN C "} ; 6'b111101 : kcpsm6_opcode <= {"RETURN NC "} ; 6'b100001 : kcpsm6_opcode <= {"LOAD&RETURN ", sx_decode, ", ", kk_decode, " "} ; 6'b101001 : begin case (instruction[0]) 1'b0 : kcpsm6_opcode <= "RETURNI DISABLE "; 1'b1 : kcpsm6_opcode <= "RETURNI ENABLE "; default : kcpsm6_opcode <= "Invalid Instruction"; endcase end 6'b101000 : begin case (instruction[0]) 1'b0 : kcpsm6_opcode <= "DISABLE INTERRUPT "; 1'b1 : kcpsm6_opcode <= "ENABLE INTERRUPT "; default : kcpsm6_opcode <= "Invalid Instruction"; endcase end 6'b110111 : begin case (instruction[0]) 1'b0 : kcpsm6_opcode <= "REGBANK A "; 1'b1 : kcpsm6_opcode <= "REGBANK B "; default : kcpsm6_opcode <= "Invalid Instruction"; endcase end default : kcpsm6_opcode <= "Invalid Instruction"; endcase // Flag status information if (zero_flag == 1'b0) kcpsm6_status[17:40] <= "NZ,"; else kcpsm6_status[17:40] <= " Z,"; if (carry_flag == 1'b0) kcpsm6_status[41:64] <= "NC,"; else kcpsm6_status[41:64] <= " C,"; if (interrupt_enable == 1'b0) kcpsm6_status[65:80] <= "ID"; else kcpsm6_status[65:80] <= "IE"; // Operational status if (clk) begin if (internal_reset == 1'b1) kcpsm6_status[81 : 128] <= ",Reset"; else if (sync_sleep == 1'b1 && t_state == 2'b00) kcpsm6_status[81 : 128] <= ",Sleep"; else kcpsm6_status[81 : 128] <= " "; end // Simulation of register contents if (clk) begin if (register_enable == 1'b1) begin case (sx_addr) 5'b00000 : bank_a_s0 <= alu_result ; 5'b00001 : bank_a_s1 <= alu_result ; 5'b00010 : bank_a_s2 <= alu_result ; 5'b00011 : bank_a_s3 <= alu_result ; 5'b00100 : bank_a_s4 <= alu_result ; 5'b00101 : bank_a_s5 <= alu_result ; 5'b00110 : bank_a_s6 <= alu_result ; 5'b00111 : bank_a_s7 <= alu_result ; 5'b01000 : bank_a_s8 <= alu_result ; 5'b01001 : bank_a_s9 <= alu_result ; 5'b01010 : bank_a_sa <= alu_result ; 5'b01011 : bank_a_sb <= alu_result ; 5'b01100 : bank_a_sc <= alu_result ; 5'b01101 : bank_a_sd <= alu_result ; 5'b01110 : bank_a_se <= alu_result ; 5'b01111 : bank_a_sf <= alu_result ; 5'b10000 : bank_b_s0 <= alu_result ; 5'b10001 : bank_b_s1 <= alu_result ; 5'b10010 : bank_b_s2 <= alu_result ; 5'b10011 : bank_b_s3 <= alu_result ; 5'b10100 : bank_b_s4 <= alu_result ; 5'b10101 : bank_b_s5 <= alu_result ; 5'b10110 : bank_b_s6 <= alu_result ; 5'b10111 : bank_b_s7 <= alu_result ; 5'b11000 : bank_b_s8 <= alu_result ; 5'b11001 : bank_b_s9 <= alu_result ; 5'b11010 : bank_b_sa <= alu_result ; 5'b11011 : bank_b_sb <= alu_result ; 5'b11100 : bank_b_sc <= alu_result ; 5'b11101 : bank_b_sd <= alu_result ; 5'b11110 : bank_b_se <= alu_result ; 5'b11111 : bank_b_sf <= alu_result ; endcase end //simulation of scratch pad memory contents if (spm_enable == 1'b1) begin case (sy_or_kk) 8'b00000000 : sim_spm00 <= sx; 8'b00000001 : sim_spm01 <= sx; 8'b00000010 : sim_spm02 <= sx; 8'b00000011 : sim_spm03 <= sx; 8'b00000100 : sim_spm04 <= sx; 8'b00000101 : sim_spm05 <= sx; 8'b00000110 : sim_spm06 <= sx; 8'b00000111 : sim_spm07 <= sx; 8'b00001000 : sim_spm08 <= sx; 8'b00001001 : sim_spm09 <= sx; 8'b00001010 : sim_spm0A <= sx; 8'b00001011 : sim_spm0B <= sx; 8'b00001100 : sim_spm0C <= sx; 8'b00001101 : sim_spm0D <= sx; 8'b00001110 : sim_spm0E <= sx; 8'b00001111 : sim_spm0F <= sx; 8'b00010000 : sim_spm10 <= sx; 8'b00010001 : sim_spm11 <= sx; 8'b00010010 : sim_spm12 <= sx; 8'b00010011 : sim_spm13 <= sx; 8'b00010100 : sim_spm14 <= sx; 8'b00010101 : sim_spm15 <= sx; 8'b00010110 : sim_spm16 <= sx; 8'b00010111 : sim_spm17 <= sx; 8'b00011000 : sim_spm18 <= sx; 8'b00011001 : sim_spm19 <= sx; 8'b00011010 : sim_spm1A <= sx; 8'b00011011 : sim_spm1B <= sx; 8'b00011100 : sim_spm1C <= sx; 8'b00011101 : sim_spm1D <= sx; 8'b00011110 : sim_spm1E <= sx; 8'b00011111 : sim_spm1F <= sx; 8'b00100000 : sim_spm20 <= sx; 8'b00100001 : sim_spm21 <= sx; 8'b00100010 : sim_spm22 <= sx; 8'b00100011 : sim_spm23 <= sx; 8'b00100100 : sim_spm24 <= sx; 8'b00100101 : sim_spm25 <= sx; 8'b00100110 : sim_spm26 <= sx; 8'b00100111 : sim_spm27 <= sx; 8'b00101000 : sim_spm28 <= sx; 8'b00101001 : sim_spm29 <= sx; 8'b00101010 : sim_spm2A <= sx; 8'b00101011 : sim_spm2B <= sx; 8'b00101100 : sim_spm2C <= sx; 8'b00101101 : sim_spm2D <= sx; 8'b00101110 : sim_spm2E <= sx; 8'b00101111 : sim_spm2F <= sx; 8'b00110000 : sim_spm30 <= sx; 8'b00110001 : sim_spm31 <= sx; 8'b00110010 : sim_spm32 <= sx; 8'b00110011 : sim_spm33 <= sx; 8'b00110100 : sim_spm34 <= sx; 8'b00110101 : sim_spm35 <= sx; 8'b00110110 : sim_spm36 <= sx; 8'b00110111 : sim_spm37 <= sx; 8'b00111000 : sim_spm38 <= sx; 8'b00111001 : sim_spm39 <= sx; 8'b00111010 : sim_spm3A <= sx; 8'b00111011 : sim_spm3B <= sx; 8'b00111100 : sim_spm3C <= sx; 8'b00111101 : sim_spm3D <= sx; 8'b00111110 : sim_spm3E <= sx; 8'b00111111 : sim_spm3F <= sx; 8'b01000000 : sim_spm40 <= sx; 8'b01000001 : sim_spm41 <= sx; 8'b01000010 : sim_spm42 <= sx; 8'b01000011 : sim_spm43 <= sx; 8'b01000100 : sim_spm44 <= sx; 8'b01000101 : sim_spm45 <= sx; 8'b01000110 : sim_spm46 <= sx; 8'b01000111 : sim_spm47 <= sx; 8'b01001000 : sim_spm48 <= sx; 8'b01001001 : sim_spm49 <= sx; 8'b01001010 : sim_spm4A <= sx; 8'b01001011 : sim_spm4B <= sx; 8'b01001100 : sim_spm4C <= sx; 8'b01001101 : sim_spm4D <= sx; 8'b01001110 : sim_spm4E <= sx; 8'b01001111 : sim_spm4F <= sx; 8'b01010000 : sim_spm50 <= sx; 8'b01010001 : sim_spm51 <= sx; 8'b01010010 : sim_spm52 <= sx; 8'b01010011 : sim_spm53 <= sx; 8'b01010100 : sim_spm54 <= sx; 8'b01010101 : sim_spm55 <= sx; 8'b01010110 : sim_spm56 <= sx; 8'b01010111 : sim_spm57 <= sx; 8'b01011000 : sim_spm58 <= sx; 8'b01011001 : sim_spm59 <= sx; 8'b01011010 : sim_spm5A <= sx; 8'b01011011 : sim_spm5B <= sx; 8'b01011100 : sim_spm5C <= sx; 8'b01011101 : sim_spm5D <= sx; 8'b01011110 : sim_spm5E <= sx; 8'b01011111 : sim_spm5F <= sx; 8'b01100000 : sim_spm60 <= sx; 8'b01100001 : sim_spm61 <= sx; 8'b01100010 : sim_spm62 <= sx; 8'b01100011 : sim_spm63 <= sx; 8'b01100100 : sim_spm64 <= sx; 8'b01100101 : sim_spm65 <= sx; 8'b01100110 : sim_spm66 <= sx; 8'b01100111 : sim_spm67 <= sx; 8'b01101000 : sim_spm68 <= sx; 8'b01101001 : sim_spm69 <= sx; 8'b01101010 : sim_spm6A <= sx; 8'b01101011 : sim_spm6B <= sx; 8'b01101100 : sim_spm6C <= sx; 8'b01101101 : sim_spm6D <= sx; 8'b01101110 : sim_spm6E <= sx; 8'b01101111 : sim_spm6F <= sx; 8'b01110000 : sim_spm70 <= sx; 8'b01110001 : sim_spm71 <= sx; 8'b01110010 : sim_spm72 <= sx; 8'b01110011 : sim_spm73 <= sx; 8'b01110100 : sim_spm74 <= sx; 8'b01110101 : sim_spm75 <= sx; 8'b01110110 : sim_spm76 <= sx; 8'b01110111 : sim_spm77 <= sx; 8'b01111000 : sim_spm78 <= sx; 8'b01111001 : sim_spm79 <= sx; 8'b01111010 : sim_spm7A <= sx; 8'b01111011 : sim_spm7B <= sx; 8'b01111100 : sim_spm7C <= sx; 8'b01111101 : sim_spm7D <= sx; 8'b01111110 : sim_spm7E <= sx; 8'b01111111 : sim_spm7F <= sx; 8'b10000000 : sim_spm80 <= sx; 8'b10000001 : sim_spm81 <= sx; 8'b10000010 : sim_spm82 <= sx; 8'b10000011 : sim_spm83 <= sx; 8'b10000100 : sim_spm84 <= sx; 8'b10000101 : sim_spm85 <= sx; 8'b10000110 : sim_spm86 <= sx; 8'b10000111 : sim_spm87 <= sx; 8'b10001000 : sim_spm88 <= sx; 8'b10001001 : sim_spm89 <= sx; 8'b10001010 : sim_spm8A <= sx; 8'b10001011 : sim_spm8B <= sx; 8'b10001100 : sim_spm8C <= sx; 8'b10001101 : sim_spm8D <= sx; 8'b10001110 : sim_spm8E <= sx; 8'b10001111 : sim_spm8F <= sx; 8'b10010000 : sim_spm90 <= sx; 8'b10010001 : sim_spm91 <= sx; 8'b10010010 : sim_spm92 <= sx; 8'b10010011 : sim_spm93 <= sx; 8'b10010100 : sim_spm94 <= sx; 8'b10010101 : sim_spm95 <= sx; 8'b10010110 : sim_spm96 <= sx; 8'b10010111 : sim_spm97 <= sx; 8'b10011000 : sim_spm98 <= sx; 8'b10011001 : sim_spm99 <= sx; 8'b10011010 : sim_spm9A <= sx; 8'b10011011 : sim_spm9B <= sx; 8'b10011100 : sim_spm9C <= sx; 8'b10011101 : sim_spm9D <= sx; 8'b10011110 : sim_spm9E <= sx; 8'b10011111 : sim_spm9F <= sx; 8'b10100000 : sim_spmA0 <= sx; 8'b10100001 : sim_spmA1 <= sx; 8'b10100010 : sim_spmA2 <= sx; 8'b10100011 : sim_spmA3 <= sx; 8'b10100100 : sim_spmA4 <= sx; 8'b10100101 : sim_spmA5 <= sx; 8'b10100110 : sim_spmA6 <= sx; 8'b10100111 : sim_spmA7 <= sx; 8'b10101000 : sim_spmA8 <= sx; 8'b10101001 : sim_spmA9 <= sx; 8'b10101010 : sim_spmAA <= sx; 8'b10101011 : sim_spmAB <= sx; 8'b10101100 : sim_spmAC <= sx; 8'b10101101 : sim_spmAD <= sx; 8'b10101110 : sim_spmAE <= sx; 8'b10101111 : sim_spmAF <= sx; 8'b10110000 : sim_spmB0 <= sx; 8'b10110001 : sim_spmB1 <= sx; 8'b10110010 : sim_spmB2 <= sx; 8'b10110011 : sim_spmB3 <= sx; 8'b10110100 : sim_spmB4 <= sx; 8'b10110101 : sim_spmB5 <= sx; 8'b10110110 : sim_spmB6 <= sx; 8'b10110111 : sim_spmB7 <= sx; 8'b10111000 : sim_spmB8 <= sx; 8'b10111001 : sim_spmB9 <= sx; 8'b10111010 : sim_spmBA <= sx; 8'b10111011 : sim_spmBB <= sx; 8'b10111100 : sim_spmBC <= sx; 8'b10111101 : sim_spmBD <= sx; 8'b10111110 : sim_spmBE <= sx; 8'b10111111 : sim_spmBF <= sx; 8'b11000000 : sim_spmC0 <= sx; 8'b11000001 : sim_spmC1 <= sx; 8'b11000010 : sim_spmC2 <= sx; 8'b11000011 : sim_spmC3 <= sx; 8'b11000100 : sim_spmC4 <= sx; 8'b11000101 : sim_spmC5 <= sx; 8'b11000110 : sim_spmC6 <= sx; 8'b11000111 : sim_spmC7 <= sx; 8'b11001000 : sim_spmC8 <= sx; 8'b11001001 : sim_spmC9 <= sx; 8'b11001010 : sim_spmCA <= sx; 8'b11001011 : sim_spmCB <= sx; 8'b11001100 : sim_spmCC <= sx; 8'b11001101 : sim_spmCD <= sx; 8'b11001110 : sim_spmCE <= sx; 8'b11001111 : sim_spmCF <= sx; 8'b11010000 : sim_spmD0 <= sx; 8'b11010001 : sim_spmD1 <= sx; 8'b11010010 : sim_spmD2 <= sx; 8'b11010011 : sim_spmD3 <= sx; 8'b11010100 : sim_spmD4 <= sx; 8'b11010101 : sim_spmD5 <= sx; 8'b11010110 : sim_spmD6 <= sx; 8'b11010111 : sim_spmD7 <= sx; 8'b11011000 : sim_spmD8 <= sx; 8'b11011001 : sim_spmD9 <= sx; 8'b11011010 : sim_spmDA <= sx; 8'b11011011 : sim_spmDB <= sx; 8'b11011100 : sim_spmDC <= sx; 8'b11011101 : sim_spmDD <= sx; 8'b11011110 : sim_spmDE <= sx; 8'b11011111 : sim_spmDF <= sx; 8'b11100000 : sim_spmE0 <= sx; 8'b11100001 : sim_spmE1 <= sx; 8'b11100010 : sim_spmE2 <= sx; 8'b11100011 : sim_spmE3 <= sx; 8'b11100100 : sim_spmE4 <= sx; 8'b11100101 : sim_spmE5 <= sx; 8'b11100110 : sim_spmE6 <= sx; 8'b11100111 : sim_spmE7 <= sx; 8'b11101000 : sim_spmE8 <= sx; 8'b11101001 : sim_spmE9 <= sx; 8'b11101010 : sim_spmEA <= sx; 8'b11101011 : sim_spmEB <= sx; 8'b11101100 : sim_spmEC <= sx; 8'b11101101 : sim_spmED <= sx; 8'b11101110 : sim_spmEE <= sx; 8'b11101111 : sim_spmEF <= sx; 8'b11110000 : sim_spmF0 <= sx; 8'b11110001 : sim_spmF1 <= sx; 8'b11110010 : sim_spmF2 <= sx; 8'b11110011 : sim_spmF3 <= sx; 8'b11110100 : sim_spmF4 <= sx; 8'b11110101 : sim_spmF5 <= sx; 8'b11110110 : sim_spmF6 <= sx; 8'b11110111 : sim_spmF7 <= sx; 8'b11111000 : sim_spmF8 <= sx; 8'b11111001 : sim_spmF9 <= sx; 8'b11111010 : sim_spmFA <= sx; 8'b11111011 : sim_spmFB <= sx; 8'b11111100 : sim_spmFC <= sx; 8'b11111101 : sim_spmFD <= sx; 8'b11111110 : sim_spmFE <= sx; 8'b11111111 : sim_spmFF <= sx; endcase end end // // Assignment of internal register variables to active registers // if (bank == 1'b0) begin kcpsm6_status[1:16] <= "A,"; sim_s0 <= bank_a_s0 ; sim_s1 <= bank_a_s1 ; sim_s2 <= bank_a_s2 ; sim_s3 <= bank_a_s3 ; sim_s4 <= bank_a_s4 ; sim_s5 <= bank_a_s5 ; sim_s6 <= bank_a_s6 ; sim_s7 <= bank_a_s7 ; sim_s8 <= bank_a_s8 ; sim_s9 <= bank_a_s9 ; sim_sA <= bank_a_sa ; sim_sB <= bank_a_sb ; sim_sC <= bank_a_sc ; sim_sD <= bank_a_sd ; sim_sE <= bank_a_se ; sim_sF <= bank_a_sf ; end else begin kcpsm6_status[1:16] <= "B,"; sim_s0 <= bank_b_s0 ; sim_s1 <= bank_b_s1 ; sim_s2 <= bank_b_s2 ; sim_s3 <= bank_b_s3 ; sim_s4 <= bank_b_s4 ; sim_s5 <= bank_b_s5 ; sim_s6 <= bank_b_s6 ; sim_s7 <= bank_b_s7 ; sim_s8 <= bank_b_s8 ; sim_s9 <= bank_b_s9 ; sim_sA <= bank_b_sa ; sim_sB <= bank_b_sb ; sim_sC <= bank_b_sc ; sim_sD <= bank_b_sd ; sim_sE <= bank_b_se ; sim_sF <= bank_b_sf ; end // // end //process simulation; //synthesis translate_on // // ************************** // * End of simulation code * // ************************** // // /////////////////////////////////////////////////////////////////////////////////////////// // endmodule // /////////////////////////////////////////////////////////////////////////////////////////// // // END OF FILE kcpsm6.v // ///////////////////////////////////////////////////////////////////////////////////////////
mem256x8.v
`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 11:53:17 04/03/2017 // Design Name: // Module Name: mem16x8 // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module mem256x8( input [7:0] addr, input clk, input wen, input [7:0] din, output [7:0] dout ); localparam WIDTH = 8; localparam DEPTH = 256; localparam ADDR_SIZE = 8; // input clk; // input [WIDTH-1:0] din; // input wen; // output [WIDTH-1:0] dout; reg [WIDTH-1:0] mem_array[0:DEPTH-1]; always @(posedge clk) begin if ( wen == 1 ) // normal write begin mem_array[addr] <= din; end end assign dout = mem_array[addr] ; endmodule
mux21_8bit.v
`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 07:27:29 08/31/2016 // Design Name: // Module Name: reg8e // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module mux21_8bit( input [7:0] i0, input [7:0] i1, input s, output [7:0] y ); assign y = s ? i1 : i0; endmodule
mux3_8bit.v
`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 09:14:03 04/05/2017 // Design Name: // Module Name: mux3_8bit // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module mux3_8bit( input [7:0] I0, input [7:0] I1, input [7:0] I2, input [1:0] S, output [7:0] Y ); assign Y = (S[1] == 1'b1) ? I2 : (S[0] == 1'b1) ? I1 : I0; endmodule
mux3_8bit_stx_beh.prj
verilog isim_temp "mux3_8bit.v" verilog isim_temp "C:/Xilinx/14.7/ISE_DS/ISE//verilog/src/glbl.v"
Nexys3_master.ucf
## This file is a general .ucf for Nexys3 rev B board ## To use it in a project: ## - remove or comment the lines corresponding to unused pins ## - rename the used signals according to the project ## Clock signal NET "CLKPORT" LOC = "V10" | IOSTANDARD = "LVCMOS33"; #Bank = 2, pin name = IO_L30N_GCLK0_USERCCLK, Sch name = GCLK #Net "clk" TNM_NET = sys_clk_pin; #TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 100000 kHz; ## onBoard USB controller ## NOTE: DEPP and DSTM net names use some of the same pins, if trying to use both DEPP and DSTM use a signle net name for each shared pin. ## Data bus for both the DEPP and DSTM interfaces uncomment lines 15-22 if using either one #NET "DB<0>" LOC = "E1" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L50N_M3BA2, Sch name = U-FD0 #NET "DB<1>" LOC = "F4" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L51P_M3A10, Sch name = U-FD1 #NET "DB<2>" LOC = "F3" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L51N_M3A4, Sch name = U-FD2 #NET "DB<3>" LOC = "D2" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L52P_M3A8, Sch name = U-FD3 #NET "DB<4>" LOC = "D1" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L52N_M3A9, Sch name = U-FD4 #NET "DB<5>" LOC = "H7" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L53P_M3CKE, Sch name = U-FD5 #NET "DB<6>" LOC = "G6" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L53N_M3A12, Sch name = U-FD6 #NET "DB<7>" LOC = "E4" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L54P_M3RESET, Sch name = U-FD7 ## If using the DEPP interface uncomment lines 25-28 #NET "EppWRITE" LOC = "F5" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L55N_M3A14, Sch name = U-FLAGC #NET "EppASTB" LOC = "H1" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L41N_GCLK26_M3DQ5, Sch name = U-FLAGA #NET "EppDSTB" LOC = "K4" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L42P_GCLK25_TRDY2_M3UDM, Sch name = U-FLAGB #NET "EppWAIT" LOC = "C2" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L83P, Sch name = U-SLRD ## If using the DSTM interface uncomment lines 31-40 #NET "DstmIFCLK" LOC = "H2" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L41P_GCLK27_M3DQ4, Sch name = U-IFCLK #NET "DstmSLCS" LOC = "F6" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L55P_M3A13, Sch name = U-SLCS #NET "DstmFLAGA" LOC = "H1" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L41N_GCLK26_M3DQ5, Sch name = U-FLAGA #NET "DstmFLAGB" LOC = "K4" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L42P_GCLK25_TRDY2_M3UDM, Sch name = U-FLAGB #NET "DstmADR<0>" LOC = "H5" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L49N_M3A2, Sch name = U-FIFOAD0 #NET "DstmADR<1>" LOC = "E3" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L50P_M3WE, Sch name = U-FIFOAD1 #Net "DstmSLRD" LOC = "C2" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L83P, Sch name = U-SLRD #NET "DstmSLWR" LOC = "C1" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L83N_VREF, Sch name = U-SLWR #NET "DstmSLOE" LOC = "H6" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L49P_M3A7, Sch name = U-SLOE #NET "DstmPKTEND" LOC = "D3" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L54N_M3A11, Sch name = U-PKTEND #NET "UsbMode" LOC = "F1" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L48N_M3BA1, Sch name = U-INT0# ## onBoard Cellular RAM, Numonyx StrataFlash and Numonyx Quad Flash #NET "MemOE" LOC = "L18" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L46N_FOE_B_M1DQ3, Sch name = P30-OE #NET "MemWR" LOC = "M16" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L47P_FWE_B_M1DQ0, Sch name = P30-WE #NET "RamAdv" LOC = "H18" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L43N_GCLK4_M1DQ5, Sch name = P30-ADV #NET "RamCS" LOC = "L15" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L42P_GCLK7_M1UDM, Sch name = MT-CE #NET "RamClk" LOC = "R10" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L29P_GCLK3, Sch name = P30-CLK #NET "RamCRE" LOC = "M18" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L47N_LDC_M1DQ1, Sch name = MT-CRE #NET "RamLB" LOC = "K16" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L41N_GCLK8_M1CASN, Sch name = MT-LB #NET "RamUB" LOC = "K15" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L41P_GCLK9_IRDY1_M1RASN, Sch name = MT-UB #NET "RamWait" LOC = "V4" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L63N, Sch name = P30-WAIT #NET "FlashRp" LOC = "T4" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L63P, Sch name = P30-RST #NET "FlashCS" LOC = "L17" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L46P_FCS_B_M1DQ2, Sch name = P30-CE #NET "QuadSpiFlashCS" LOC="V3" | IOSTANDARD = "LVCMOS33"; #Bank = MISC, Pin name = IO_L65N_CSO_B_2, Sch name = CS #NET "QuadSpiFlashSck" LOC="R15" | IOSTANDARD = "LVCMOS33"; #Bank = MISC, Pin name = IO_L1P_CCLK_2, Sch name = SCK #NET "QuadSpiFlashDB<0>" LOC="T13" | IOSTANDARD = "LVCMOS33"; #Dual/Quad SPI Flash DB<0>, Bank = MISC, Pin name = IO_L3N_MOSI_CSI_B_MISO0_2, Sch name = SDI #NET "MemAdr<1>" LOC = "K18" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L45N_A0_M1LDQSN, Sch name = P30-A0 #NET "MemAdr<2>" LOC = "K17" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L45P_A1_M1LDQS, Sch name = P30-A1 #NET "MemAdr<3>" LOC = "J18" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L44N_A2_M1DQ7, Sch name = P30-A2 #NET "MemAdr<4>" LOC = "J16" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L44P_A3_M1DQ6, Sch name = P30-A3 #NET "MemAdr<5>" LOC = "G18" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L38N_A4_M1CLKN, Sch name = P30-A4 #NET "MemAdr<6>" LOC = "G16" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L38P_A5_M1CLK, Sch name = P30-A5 #NET "MemAdr<7>" LOC = "H16" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L37N_A6_M1A1, Sch name = P30-A6 #NET "MemAdr<8>" LOC = "H15" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L37P_A7_M1A0, Sch name = P30-A7 #NET "MemAdr<9>" LOC = "H14" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L36N_A8_M1BA1, Sch name = P30-A8 #NET "MemAdr<10>" LOC = "H13" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L36P_A9_M1BA0, Sch name = P30-A9 #NET "MemAdr<11>" LOC = "F18" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L35N_A10_M1A2, Sch name = P30-A10 #NET "MemAdr<12>" LOC = "F17" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L35P_A11_M1A7, Sch name = P30-A11 #NET "MemAdr<13>" LOC = "K13" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L34N_A12_M1BA2, Sch name = P30-A12 #NET "MemAdr<14>" LOC = "K12" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L34P_A13_M1WE, Sch name = P30-A13 #NET "MemAdr<15>" LOC = "E18" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L33N_A14_M1A4, Sch name = P30-A14 #NET "MemAdr<16>" LOC = "E16" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L33P_A15_M1A10, Sch name = P30-A15 #NET "MemAdr<17>" LOC = "G13" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L32N_A16_M1A9, Sch name = P30-A16 #NET "MemAdr<18>" LOC = "H12" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L32P_A17_M1A8, Sch name = P30-A17 #NET "MemAdr<19>" LOC = "D18" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L31N_A18_M1A12, Sch name = P30-A18 #NET "MemAdr<20>" LOC = "D17" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L31P_A19_M1CKE, Sch name = P30-A19 #NET "MemAdr<21>" LOC = "G14" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L30N_A20_M1A11, Sch name = P30-A20 #NET "MemAdr<22>" LOC = "F14" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L30P_A21_M1RESET Sch name = P30-A21 #NET "MemAdr<23>" LOC = "C18" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L29N_A22_M1A14, Sch name = P30-A22 #NET "MemAdr<24>" LOC = "C17" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L29P_A23_M1A13, Sch name = P30-A23 #NET "MemAdr<25>" LOC = "F16" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L1N_A24_VREF, Sch name = P30-A24 #NET "MemAdr<26>" LOC = "F15" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L1P_A25, Sch name = P30-A25 #NET "MemDB<0>" LOC = "R13" | IOSTANDARD = "LVCMOS33"; #Ram or Numonyx Paralell Flash DB<0>, or Dual/Quad SPI Flash DB<1>, Bank = MISC, Pin name = IO_L3P_D0_DIN_MISO_MISO1_2, Sch name = P30-DQ0 #NET "MemDB<1>" LOC = "T14" | IOSTANDARD = "LVCMOS33"; #Ram or Numonyx Paralell Flash DB<1>, or Quad SPI Flash DB<2>, Bank = MISC, Pin name = IO_L12P_D1_MISO2_2, Sch name = P30-DQ1 #NET "MemDB<2>" LOC = "V14" | IOSTANDARD = "LVCMOS33"; #Ram or Numonyx Paralell Flash DB<2>, or Quad SPI Flash DB<3>, Bank = MISC, Pin name = IO_L12N_D2_MISO3_2, Sch name = P30-DQ2 #NET "MemDB<3>" LOC = "U5" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_49P_D3, Sch name = P30-DQ3 #NET "MemDB<4>" LOC = "V5" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_49N_D4, Sch name = P30-DQ4 #NET "MemDB<5>" LOC = "R3" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L62P_D5, Sch name = P30-DQ5 #NET "MemDB<6>" LOC = "T3" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L62N_D6, Sch name = P30-DQ6 #NET "MemDB<7>" LOC = "R5" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L48P_D7, Sch name = P30-DQ7 #NET "MemDB<8>" LOC = "N5" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L64P_D8, Sch name = P30-DQ8 #NET "MemDB<9>" LOC = "P6" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L64N_D9, Sch name = P30-DQ9 #NET "MemDB<10>" LOC = "P12" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L13N_D10, Sch name = P30-DQ10 #NET "MemDB<11>" LOC = "U13" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L14P_D11, Sch name = P30-DQ11 #NET "MemDB<12>" LOC = "V13" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L14N_D12, Sch name = P30-DQ12 #NET "MemDB<13>" LOC = "U10" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L30P_GCLK1_D13, Sch name = P30-DQ13 #NET "MemDB<14>" LOC = "R8" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L31P_GCLK31_D14, Sch name = P30-DQ14 #NET "MemDB<15>" LOC = "T8" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L31N_GCLK30_D15, Sch name = P30-DQ15 ## 7 segment display NET "CA" LOC = "T17" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L51P_M1DQ12, Sch name = CA NET "CB" LOC = "T18" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L51N_M1DQ13, Sch name = CB NET "CC" LOC = "U17" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L52P_M1DQ14, Sch name = CC NET "CD" LOC = "U18" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L52N_M1DQ15, Sch name = CD NET "CE" LOC = "M14" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L53P, Sch name = CE NET "CF" LOC = "N14" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L53N_VREF, Sch name = CF NET "CG" LOC = "L14" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L61P, Sch name = CG NET "DP" LOC = "M13" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L61N, Sch name = DP NET "an<0>" LOC = "N16" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L50N_M1UDQSN, Sch name = AN0 NET "an<1>" LOC = "N15" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L50P_M1UDQS, Sch name = AN1 NET "an<2>" LOC = "P18" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L49N_M1DQ11, Sch name = AN2 NET "an<3>" LOC = "P17" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L49P_M1DQ10, Sch name = AN3 ## Leds NET "led<0>" LOC = "U16" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L2P_CMPCLK, Sch name = LD0 NET "led<1>" LOC = "V16" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L2N_CMPMOSI, Sch name = LD1 NET "led<2>" LOC = "U15" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L5P, Sch name = LD2 NET "led<3>" LOC = "V15" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L5N, Sch name = LD3 NET "led<4>" LOC = "M11" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L15P, Sch name = LD4 NET "led<5>" LOC = "N11" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L15N, Sch name = LD5 NET "led<6>" LOC = "R11" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L16P, Sch name = LD6 NET "led<7>" LOC = "T11" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L16N_VREF, Sch name = LD7 ## Switches NET "sw<0>" LOC = "T10" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L29N_GCLK2, Sch name = SW0 NET "sw<1>" LOC = "T9" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L32P_GCLK29, Sch name = SW1 NET "sw<2>" LOC = "V9" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L32N_GCLK28, Sch name = SW2 NET "sw<3>" LOC = "M8" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L40P, Sch name = SW3 NET "sw<4>" LOC = "N8" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L40N, Sch name = SW4 NET "sw<5>" LOC = "U8" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L41P, Sch name = SW5 NET "sw<6>" LOC = "V8" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L41N_VREF, Sch name = SW6 NET "sw<7>" LOC = "T5" | IOSTANDARD = "LVCMOS33"; #Bank = MISC, Pin name = IO_L48N_RDWR_B_VREF_2, Sch name = SW7 ## Buttons NET "btn<0>" LOC = "B8" | IOSTANDARD = "LVCMOS33"; #Bank = 0, Pin name = IO_L33P, Sch name = BTNS NET "btn<1>" LOC = "A8" | IOSTANDARD = "LVCMOS33"; #Bank = 0, Pin name = IO_L33N, Sch name = BTNU NET "btn<2>" LOC = "C4" | IOSTANDARD = "LVCMOS33"; #Bank = 0, Pin name = IO_L1N_VREF, Sch name = BTNL NET "btn<3>" LOC = "C9" | IOSTANDARD = "LVCMOS33"; #Bank = 0, Pin name = IO_L34N_GCLK18, Sch name = BTND NET "btn<4>" LOC = "D9" | IOSTANDARD = "LVCMOS33"; #Bank = 0, Pin name = IO_L34P_GCLK19, Sch name = BTNR ## VGA Connector #NET "vgaRed<0>" LOC = "U7" | IOSTANDARD = "LVCMOS33"; # Bank = 2, Pin name = IO_L43P, Sch name = RED0 #NET "vgaRed<1>" LOC = "V7" | IOSTANDARD = "LVCMOS33"; # Bank = 2, Pin name = IO_L43N, Sch name = RED1 #NET "vgaRed<2>" LOC = "N7" | IOSTANDARD = "LVCMOS33"; # Bank = 2, Pin name = IO_L44P, Sch name = RED2 #NET "vgaGreen<0>" LOC = "P8" | IOSTANDARD = "LVCMOS33"; # Bank = 2, Pin name = IO_L44N, Sch name = GRN0 #NET "vgaGreen<1>" LOC = "T6" | IOSTANDARD = "LVCMOS33"; # Bank = 2, Pin name = IO_L45P, Sch name = GRN1 #NET "vgaGreen<2>" LOC = "V6" | IOSTANDARD = "LVCMOS33"; # Bank = 2, Pin name = IO_L45N, Sch name = GRN2 #NET "vgaBlue<1>" LOC = "R7" | IOSTANDARD = "LVCMOS33"; # Bank = 2, Pin name = IO_L46P, Sch name = BLU1 #NET "vgaBlue<2>" LOC = "T7" | IOSTANDARD = "LVCMOS33"; # Bank = 2, Pin name = IO_L46N, Sch name = BLU2 #NET "Hsync" LOC = "N6" | IOSTANDARD = "LVCMOS33"; # Bank = 2, Pin name = IO_L47P, Sch name = HSYNC #NET "Vsync" LOC = "P7" | IOSTANDARD = "LVCMOS33"; # Bank = 2, Pin name = IO_L47N, Sch name = VSYNC ## 12 pin connectors ##JA #NET "JA<0>" LOC = "T12" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L19P, Sch name = JA1 #NET "JA<1>" LOC = "V12" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L19N, Sch name = JA2 #NET "JA<2>" LOC = "N10" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L20P, Sch name = JA3 #NET "JA<3>" LOC = "P11" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L20N, Sch name = JA4 #NET "JA<4>" LOC = "M10" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L22P, Sch name = JA7 #NET "JA<5>" LOC = "N9" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L22N, Sch name = JA8 #NET "JA<6>" LOC = "U11" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L23P, Sch name = JA9 #NET "JA<7>" LOC = "V11" | IOSTANDARD = "LVCMOS33"; #Bank = 2, Pin name = IO_L23N, Sch name = JA10 ##JB #NET "JB<0>" LOC = "K2" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L38P_M3DQ2, Sch name = JB1 #NET "JB<1>" LOC = "K1" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L38N_M3DQ3, Sch name = JB2 #NET "JB<2>" LOC = "L4" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L39P_M3LDQS, Sch name = JB3 #NET "JB<3>" LOC = "L3" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L39N_M3LDQSN, Sch name = JB4 #NET "JB<4>" LOC = "J3" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L40P_M3DQ6, Sch name = JB7 #NET "JB<5>" LOC = "J1" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L40N_M3DQ7, Sch name = JB8 #NET "JB<6>" LOC = "K3" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L42N_GCLK24_M3LDM, Sch name = JB9 #NET "JB<7>" LOC = "K5" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L43N_GCLK22_IRDY2_M3CASN, Sch name = JB10 ##JC #NET "JC<0>" LOC = "H3" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L44N_GCLK20_M3A6, Sch name = JC1 #NET "JC<1>" LOC = "L7" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L45P_M3A3, Sch name = JC2 #NET "JC<2>" LOC = "K6" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L45N_M3ODT, Sch name = JC3 #NET "JC<3>" LOC = "G3" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L46P_M3CLK, Sch name = JC4 #NET "JC<4>" LOC = "G1" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L46N_M3CLKN, Sch name = JC7 #NET "JC<5>" LOC = "J7" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L47P_M3A0, Sch name = JC8 #NET "JC<6>" LOC = "J6" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L47N_M3A1, Sch name = JC9 #NET "JC<7>" LOC = "F2" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L48P_M3BA0, Sch name = JC10 ##JD, LX16 Die only #NET "JD<0>" LOC = "G11" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L40P, Sch name = JD1 #NET "JD<1>" LOC = "F10" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L40N, Sch name = JD2 #NET "JD<2>" LOC = "F11" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L42P, Sch name = JD3 #NET "JD<3>" LOC = "E11" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L42N, Sch name = JD4 #NET "JD<4>" LOC = "D12" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L47P, Sch name = JD7 #NET "JD<5>" LOC = "C12" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L47N, Sch name = JD8 #NET "JD<6>" LOC = "F12" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L51P, Sch name = JD9 #NET "JD<7>" LOC = "E12" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L51N, Sch name = JD10 ## SMSC ethernet PHY #NET "PhyRstn" LOC = "P3" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L2N, Sch name = ETH-RST #NET "PhyCrs" LOC = "N3" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L1N_VREF, Sch name = ETH-CRS #NET "PhyCol" LOC = "P4" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L2P, Sch name = ETH-COL #NET "PhyClk25Mhz" LOC = "N4" | IOSTANDARD = "LVCMOS33"; #Unconnected if R172 is not loaded, Bank = 3, Pin name = IO_L1P, Sch name = ETH-CLK25MHZ #NET "PhyTxd<3>" LOC = "T1" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L33N_M3DQ13, Sch name = ETH-TXD3 #NET "PhyTxd<2>" LOC = "T2" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L33P_M3DQ12, Sch name = ETH-TXD2 #NET "PhyTxd<1>" LOC = "U1" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L32N_M3DQ15, Sch name = ETH-TXD1 #NET "PhyTxd<0>" LOC = "U2" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L32P_M3DQ14, Sch name = ETH-TXD0 #NET "PhyTxEn" LOC = "L2" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L37P_M3DQ0, Sch name = ETH-TX_EN #NET "PhyTxClk" LOC = "L5" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L43P_GCLK23_M3RASN, Sch name = ETH-TX_CLK #NET "PhyTxEr" LOC = "P2" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L34P_M3UDQS, Sch name = ETH-TXD4 #NET "PhyRxd<3>" LOC = "M3" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L36P_M3DQ8, Sch name = ETH-RXD3 #NET "PhyRxd<2>" LOC = "N1" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L35N_M3DQ11, Sch name = ETH-RXD2 #NET "PhyRxd<1>" LOC = "N2" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L35P_M3DQ10, Sch name = ETH-RXD1 #NET "PhyRxd<0>" LOC = "P1" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L34N_M3UDQSN, Sch name = ETH-RXD0 #NET "PhyRxDv" LOC = "L1" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L37N_M3DQ1, Sch name = ETH-RX_DV #NET "PhyRxEr" LOC = "M1" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L36N_M3DQ9, Sch name = ETH-RXD4 #NET "PhyRxClk" LOC = "H4" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L44P_GCLK21_M3A5, Sch name = ETH-RX_CLK #NET "PhyMdc" LOC = "M5" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L31N_VREF, Sch name = ETH-MDC #NET "PhyMdio" LOC = "L6" | IOSTANDARD = "LVCMOS33"; #Bank = 3, Pin name = IO_L31P, Sch name = ETH-MDIO ## Pic USB-HID interface #NET "PS2KeyboardData" LOC = "J13" | IOSTANDARD = "LVCMOS33" | PULLUP; #Bank = 1, Pin name = IO_L39P_M1A3, Sch name = PIC-SDI1 #NET "PS2KeyboardClk" LOC = "L12" | IOSTANDARD = "LVCMOS33" | PULLUP; #Bank = 1, Pin name = IO_L40P_GCLK11_M1A5, Sch name = PIC-SCK1 #NET "PS2MouseData" LOC = "K14" | IOSTANDARD = "LVCMOS33" | PULLUP; #Bank = 1, Pin name = IO_L39N_M1ODT, Sch name = PIC-SDO1 #NET "PS2MouseClk" LOC = "L13" | IOSTANDARD = "LVCMOS33" | PULLUP; #Bank = 1, Pin name = IO_L40N_GCLK10_M1A6, Sch name = PIC-SS1 #NET "PicGpio<0>" LOC = "L16" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L42N_GCLK6_TRDY1_M1LDM, Sch name = PIC-GPIO0 #NET "PicGpio<1>" LOC = "H17" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L43P_GCLK5_M1DQ4, Sch name = PIC-GPIO1 ## Usb-RS232 interface #NET "RsRx" LOC = "N17" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L48P_HDC_M1DQ8, Sch name = MCU-RX #NET "RsTx" LOC = "N18" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L48N_M1DQ9, Sch name = MCU-TX ## VHDCI Connector #NET "EXP-IO_P<0>" LOC = "B2" | IOSTANDARD = "LVCMOS33"; #Bank = 0, Pin name = IO_L2P, Sch name = EXP_IO1_P #NET "EXP-IO_N<0>" LOC = "A2" | IOSTANDARD = "LVCMOS33"; #Bank = 0, Pin name = IO_L2N, Sch name = EXP_IO1_N #NET "EXP-IO_P<1>" LOC = "D6" | IOSTANDARD = "LVCMOS33"; #Bank = 0, Pin name = IO_L3P, Sch name = EXP_IO2_P #NET "EXP-IO_N<1>" LOC = "C6" | IOSTANDARD = "LVCMOS33"; #Bank = 0, Pin name = IO_L3N, Sch name = EXP_IO2_N #NET "EXP-IO_P<2>" LOC = "B3" | IOSTANDARD = "LVCMOS33"; #Bank = 0, Pin name = IO_L4P, Sch name = EXP_IO3_P #NET "EXP-IO_N<2>" LOC = "A3" | IOSTANDARD = "LVCMOS33"; #Bank = 0, Pin name = IO_L4N, Sch name = EXP_IO3_N #NET "EXP-IO_P<3>" LOC = "B4" | IOSTANDARD = "LVCMOS33"; #Bank = 0, Pin name = IO_L5P, Sch name = EXP_IO4_P #NET "EXP-IO_N<3>" LOC = "A4" | IOSTANDARD = "LVCMOS33"; #Bank = 0, Pin name = IO_L5N, Sch name = EXP_IO4_N #NET "EXP-IO_P<4>" LOC = "C5" | IOSTANDARD = "LVCMOS33"; #Bank = 0, Pin name = IO_L6P, Sch name = EXP_IO5_P #NET "EXP-IO_N<4>" LOC = "A5" | IOSTANDARD = "LVCMOS33"; #Bank = 0, Pin name = IO_L6N, Sch name = EXP_IO5_N #NET "EXP-IO_P<5>" LOC = "B6" | IOSTANDARD = "LVCMOS33"; #Bank = 0, Pin name = IO_L8P, Sch name = EXP_IO6_P #NET "EXP-IO_N<5>" LOC = "A6" | IOSTANDARD = "LVCMOS33"; #Bank = 0, Pin name = IO_L8N_VREF, Sch name = EXP_IO6_N #NET "EXP-IO_P<6>" LOC = "C7" | IOSTANDARD = "LVCMOS33"; #Bank = 0, Pin name = IO_L10P, Sch name = EXP_IO7_P #NET "EXP-IO_N<6>" LOC = "A7" | IOSTANDARD = "LVCMOS33"; #Bank = 0, Pin name = IO_L10N, Sch name = EXP_IO7_N #NET "EXP-IO_P<7>" LOC = "D8" | IOSTANDARD = "LVCMOS33"; #Bank = 0, Pin name = IO_L11P, Sch name = EXP_IO8_P #NET "EXP-IO_N<7>" LOC = "C8" | IOSTANDARD = "LVCMOS33"; #Bank = 0, Pin name = IO_L11N, Sch name = EXP_IO8_N #NET "EXP-IO_P<8>" LOC = "B9" | IOSTANDARD = "LVCMOS33"; #Bank = 0, Pin name = IO_L35P_GCLK17, Sch name = EXP_IO9_P #NET "EXP-IO_N<8>" LOC = "A9" | IOSTANDARD = "LVCMOS33"; #Bank = 0, Pin name = IO_L35N_GCLK16, Sch name = EXP_IO9_N #NET "EXP-IO_P<9>" LOC = "D11" | IOSTANDARD = "LVCMOS33"; #Bank = 0, Pin name = IO_L36P_GCLK15, Sch name = EXP_IO10_P #NET "EXP-IO_N<9>" LOC = "C11" | IOSTANDARD = "LVCMOS33"; #Bank = 0, Pin name = IO_L36N_GCLK14, Sch name = EXP_IO10_N #NET "EXP-IO_P<10>" LOC = "C10" | IOSTANDARD = "LVCMOS33"; #Bank = 0, Pin name = IO_L37P_GCLK13, Sch name = EXP_IO11_P #NET "EXP-IO_N<10>" LOC = "A10" | IOSTANDARD = "LVCMOS33"; #Bank = 0, Pin name = IO_L37N_GCLK12, Sch name = EXP_IO11_N #NET "EXP-IO_P<11>" LOC = "G9" | IOSTANDARD = "LVCMOS33"; #Bank = 0, Pin name = IO_L38P, Sch name = EXP_IO12_P #NET "EXP-IO_N<11>" LOC = "F9" | IOSTANDARD = "LVCMOS33"; #Bank = 0, Pin name = IO_L38N_VREF, Sch name = EXP_IO12_N #NET "EXP-IO_P<12>" LOC = "B11" | IOSTANDARD = "LVCMOS33"; #Bank = 0, Pin name = IO_L39P, Sch name = EXP_IO13_P #NET "EXP-IO_N<12>" LOC = "A11" | IOSTANDARD = "LVCMOS33"; #Bank = 0, Pin name = IO_L39N, Sch name = EXP_IO13_N #NET "EXP-IO_P<13>" LOC = "B12" | IOSTANDARD = "LVCMOS33"; #Bank = 0, Pin name = IO_L41P, Sch name = EXP_IO14_P #NET "EXP-IO_N<13>" LOC = "A12" | IOSTANDARD = "LVCMOS33"; #Bank = 0, Pin name = IO_L41N, Sch name = EXP_IO14_N #NET "EXP-IO_P<14>" LOC = "C13" | IOSTANDARD = "LVCMOS33"; #Bank = 0, Pin name = IO_L50P, Sch name = EXP_IO15_P #NET "EXP-IO_N<14>" LOC = "A13" | IOSTANDARD = "LVCMOS33"; #Bank = 0, Pin name = IO_L50N, Sch name = EXP_IO15_N #NET "EXP-IO_P<15>" LOC = "B14" | IOSTANDARD = "LVCMOS33"; #Bank = 0, Pin name = IO_L62P, Sch name = EXP_IO16_P #NET "EXP-IO_N<15>" LOC = "A14" | IOSTANDARD = "LVCMOS33"; #Bank = 0, Pin name = IO_L62N_VREF, Sch name = EXP_IO16_N #NET "EXP-IO_P<16>" LOC = "F13" | IOSTANDARD = "LVCMOS33"; #Bank = 0, Pin name = IO_L63P_SCP7, Sch name = EXP_IO17_P #NET "EXP-IO_N<16>" LOC = "E13" | IOSTANDARD = "LVCMOS33"; #Bank = 0, Pin name = IO_L63N_SCP6, Sch name = EXP_IO17_N #NET "EXP-IO_P<17>" LOC = "C15" | IOSTANDARD = "LVCMOS33"; #Bank = 0, Pin name = IO_L64P_SCP5, Sch name = EXP_IO18_P #NET "EXP-IO_N<17>" LOC = "A15" | IOSTANDARD = "LVCMOS33"; #Bank = 0, Pin name = IO_L64N_SCP4, Sch name = EXP_IO18_N #NET "EXP-IO_P<18>" LOC = "D14" | IOSTANDARD = "LVCMOS33"; #Bank = 0, Pin name = IO_L65P_SCP3, Sch name = EXP_IO19_P #NET "EXP-IO_N<18>" LOC = "C14" | IOSTANDARD = "LVCMOS33"; #Bank = 0, Pin name = IO_L65N_SCP2, Sch name = EXP_IO19_N #NET "EXP-IO_P<19>" LOC = "B16" | IOSTANDARD = "LVCMOS33"; #Bank = 0, Pin name = IO_L66P_SCP1, Sch name = EXP_IO20_P #NET "EXP-IO_N<19>" LOC = "A16" | IOSTANDARD = "LVCMOS33"; #Bank = 0, Pin name = IO_L66N_SCP0, Sch name = EXP_IO20_N
par_usage_statistics.html
| Par Statistics |
| Total Non-vccgnd Signals=493 |
| Total Non-vccgnd Design Pins=1932 |
| Total Non-vccgnd Conns=1932 |
| Total Non-vccgnd Timing Constrained Conns=1696 |
| Phase 1 CPU=2.7 sec |
| Phase 2 CPU=3.0 sec |
| Phase 3 CPU=3.7 sec |
| Phase 4 CPU=4.2 sec |
| Phase 5 CPU=5.3 sec |
| Phase 6 CPU=5.3 sec |
| Phase 7 CPU=5.3 sec |
| Phase 8 CPU=5.3 sec |
| Phase 9 CPU=5.3 sec |
| Phase 10 CPU=5.4 sec |
| AvgWirelenPerPin Fanout 1=4.0 |
| AvgWirelenPerPin Fanout 2=2.5 |
| AvgWirelenPerPin Fanout 3=2.7 |
| AvgWirelenPerPin Fanout 4=2.0 |
| AvgWirelenPerPin Fanout 10=4.1 |
| AvgWirelenPerPin Fanout 50=2.3 |
| AvgWirelenPerPin Fanout 100=9.9 |
| AvgWirelenPerPin Fanout 500=0.0 |
| AvgWirelenPerPin Fanout 5000=0.0 |
| AvgWirelenPerPin Fanout 20000=0.0 |
| AvgWirelenPerPin Fanout 50000=0.0 |
| AvgWirelenPerPin Fanout 100000=0.0 |
| IRR Gamma=1.4510 |
pe4_2.v
`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 12:43:26 10/12/2016 // Design Name: // Module Name: pe4_2 // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module pe4_2( input I0, input I1, input I2, input I3, output [1:0] Y, output V ); reg [1:0] yint; always @* begin if(I3==1) yint = 2'b11; else if(I2==1) yint = 2'b10; else if(I1==1) yint = 2'b01; else yint = 2'b00; end assign V = I3 | I2 | I1 | I0; assign Y = yint; endmodule
reg8e.v
`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 07:27:29 08/31/2016 // Design Name: // Module Name: reg8e // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module reg8e( input clk, input reset, input en, input [7:0] d, output reg [7:0] q ); always @(posedge clk) begin if(reset) q <= 8'b00000000; else if(en) q <= d; end endmodule
sevenseg_decoder.v
`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 10:06:30 10/24/2008 // Design Name: // Module Name: sevenseg_decoder // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module sevenseg_decoder( input [3:0] digit, output reg A, output reg B, output reg C, output reg D, output reg E, output reg F, output reg G ); always @(digit) begin A <= 1; B <= 1; C <= 1; D <= 1; E <= 1; F <= 1; G <= 1; case(digit) 4'd0: begin A <= 0; B <= 0; C <= 0; D <= 0; E <= 0; F <= 0; end 4'd1: begin B <= 0; C <= 0; end 4'd2: begin A <= 0; B <= 0; D <= 0; E <= 0; G <= 0; end 4'd3: begin A <= 0; B <= 0; C <= 0; D <= 0; G <= 0; end 4'd4: begin B <= 0; C <= 0; F <= 0; G <= 0; end 4'd5: begin A <= 0; C <= 0; D <= 0; F <= 0; G <= 0; end 4'd6: begin C <= 0; D <= 0; E <= 0; F <= 0; G <= 0; end 4'd7: begin A <= 0; B <= 0; C <= 0; end 4'd8: begin A <= 0; B <= 0; C <= 0; D <= 0; E <= 0; F <= 0; G <= 0; end 4'd9: begin A <= 0; B <= 0; C <= 0; F <= 0; G <= 0; end endcase end endmodule
sqrt_sys_tb.v
// Verilog test fixture created from schematic C:\Users\Mark\Dropbox\EE209\Lab\sqrt2\sqrt_sys.sch - Wed Nov 25 15:46:16 2015 `timescale 1ns / 1ps module heap_soc_tb(); // Inputs reg [3:0] BTNS; reg [7:0] SWITCHES; reg CLK; reg RESET; // Output wire [7:0] DISP; wire [7:0] LEDS; // Bidirs task do_pblaze_push; input [7:0] val; begin BTNS[0] = 1; SWITCHES = val; #200; // leave enough to time for Picoblaze to poll and see this input BTNS[0] = 0; for(i=0; i < 60; i=i+1) begin wait(CLK == 0); wait(CLK == 1); end #5; end endtask task do_pblaze_pop; begin BTNS[1] = 1; #200; // leave enough to time for Picoblaze to poll and see this input BTNS[1] = 0; for(i=0; i < 60; i=i+1) begin wait(CLK == 0); wait(CLK == 1); end #5; end endtask task do_pblaze_top; begin BTNS[2] = 1; #200; // leave enough to time for Picoblaze to poll and see this input BTNS[2] = 0; for(i=0; i < 25; i=i+1) begin wait(CLK == 0); wait(CLK == 1); end #5; end endtask task do_pblaze_size; begin BTNS[3] = 1; #200; // leave enough to time for Picoblaze to poll and see this input BTNS[3] = 0; for(i=0; i < 25; i=i+1) begin wait(CLK == 0); wait(CLK == 1); end #5; end endtask // UUT instantiation heap_soc UUT ( .clk(CLK), .reset(RESET), .btns(BTNS), .switches(SWITCHES), .leds(LEDS), .disp(DISP) ); integer i; // Initialize Inputs always #10 CLK = ~CLK; initial begin CLK = 1; RESET = 1; BTNS = 3'b0000; #105; RESET = 0; // SIZE op do_pblaze_size(); // PUSH op do_pblaze_push(8'h07); // PUSH op do_pblaze_push(8'h04); // SIZE op do_pblaze_size(); // TOP op do_pblaze_top(); // POP op do_pblaze_pop(); // SIZE op do_pblaze_size(); // TOP op do_pblaze_top(); #5; $stop(); end endmodule
_xmsgs/pn_parser.xmsgs
