Electrical Engineering Project-Need A PRO!! in Cadence

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FINAL PROJECT/FINAL PROJECT PRESENTATION TEMPLATE.pptx

Name of the project

Group #

Names

Requirements of the design e.g. IB, L etc.

Schematic (hand drawn)

SPICE open-loop DC gain sweep

Fig. 1: VOUTDIF (VOUT+ - VOUT-) Vs. VINCM

Gain calculated from Fig. 1 curve (slope)

SPICE open-loop DC gain sweep

Fig. 2: VOUT+ and VOUT- Vs. VINCM

SPICE open loop gain

Fig. 3: Open loop gain (in dB) simulation result (Unity gain BW= 56.23 MHz, BW = 34.09KHz, Rc= 23kΩ, Cc=500fF)

Gain = ?

-3 dB frequency = ?

Unity gain frequency = ?

SPICE open loop phase (and phase margin)

Phase Margin = ?

Fig. 4: Open loop phase simulation result (Unity gain BW= 54.7 MHz, PM= 710, Rc= 23kΩ, Cc=500fF)

SPICE open-loop slew rate

Fig. 5: Positive Input signal.

Fig. 6: negative Input signal.

SPICE open-loop slew rate

Fig. 7: Vout- and Vout+ vs. time (CL=2pF, Rc= 23kΩ, Cc=500fF). Slew rate = -13.62 V/µs.

Fig. 8: Voutdif vs. time (CL=2pF, Rc= 23kΩ, Cc=500fF). Slew rate = -25.51 V/µs.

 

Positive slew rate

SPICE open-loop slew rate

Fig. 6: Vout- and Vout+ vs. time (CL=2pF, Rc= 23kΩ, Cc=500fF). Slew rate = -13.6 V/µs.

Fig. 7: Voutdif vs. time (CL=2pF, Rc= 23kΩ, Cc=500fF). Slew rate = -25.6 V/µs. 

Negative slew rate

Spice open loop impulse response stability of CMFB

Current into each output.

Vout- and Vout+ response for (CL=2pF, Rc= 23kΩ, Cc=500fF).

__MACOSX/FINAL PROJECT/._FINAL PROJECT PRESENTATION TEMPLATE.pptx

FINAL PROJECT/.DS_Store

__MACOSX/FINAL PROJECT/._.DS_Store

FINAL PROJECT/two_stage.xlsx

NMOS

MOS Devices Mirror
Type Input Design, Process VAL Choices Parameter Units M11 M12, M13 M14 M3, M4 M15 M16
Hand Simulated Hand Simulated Hand Simulated Hand Simulated Hand Simulated Hand Simulated
ID µA 25 25 12.5 12.5 50 51.38 50 50.59 25 100 25.72 25 25.66
VEFF= VGS-VT V 0.25 0.251 0.25 0.251 0.25 0.253 0.25 0.2499 0.25 0.25 0.2405 0.25 0.24
L (eff) µm 1 1 1 1 1 1 1 1 1 1 1 1 1
VSB V 0 0 0 0 0 0 0 0 0.35 0.35 0.5296 0.35 0.5296
M --- 2 2 1 1 4 4 4 4 2 4 2 2 2
VAL V/µm 10 10 10 10 10 10 10 10 10 10 10 10 10
Geometry S = W/L --- 10 10 5 5 20 20.88 20 20 10 10 10 10 10
W (Total) µm 10 10 5 5 20 20.88 20 20 10 10 10 10 10
WL µm2 10 10 5 5 20 20.88 20 20 10 10 10 10 10
Bias Voltages VT V 0.75 0.724 0.75 0.724 0.75 0.722 0.75 0.721 0.5934752416 0.5934752416 0.8805 0.5934752416 0.8805
∆VT V 0 0 0 0 0 0 0 0 0.1565247584 0.1565247584 0.1305 0.1565247584 0.1305
VGS V 1 0.975 1 0.975 1 0.975 1 0.971 0.8434752416 0.8434752416 1.121 0.8434752416 1.12
VDS,Sat V 0.179 0.181 0.179 0.181 0.179 0.183 0.179 0.180 0.179 0.179 0.189 0.179 0.1888
Small Signal Parameters gm/ID V-1 8 10.37 8 10.36 8 10.197 8 10.44 8 8 10.47 8 10.49
gm µS 200 259.2 100 129.6 400 523.9 400 528.4 200 800 269.4 200 269.2
VA V 10.00 10.00 10.00 10.00 10.00 10.00 10.00 10.00 10.00 10.00 10.00 10.00 10
gds µS 2.50 2.38 1.25 1.19 5.00 9.91 5.00 3.33 2.50 10.00 1.76 2.50 1.753
η --- 0.39 0.39 0.39 0.39 0.39 0.39 0.39 0.39 0.33 0.33 0.30 0.33 0.303534137
gmb µS 78.26 84.55 39.13 42.26 156.52 170.70 156.52 172.20 65.28 261.10 64.81 65.28 64.76
Intrinsic Gate Capacitance CGOX fF 25.60 25.60 12.80 12.80 51.20 53.45 51.20 51.20 25.60 25.60 25.60 25.60 25.6
Cgsi fF 17.1 17.1 8.5 8.5 34.1 35.6 34.1 34.1 17.1 17.1 17.1 17.1 17.0666666667
Cgbi fF 2.4 2.4 1.2 1.2 4.9 5.1 4.9 4.9 2.4 2.4 2.4 2.4 2.4380952381
Cgdi fF 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0
Extrinsic Gate Capacitance CGSO fF 2.0 2.0 1.0 1.0 4.0 4.2 4.0 4.0 2.0 2.0 2.0 2.0 2
CGBO fF 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1
CGDO fF 2.0 2.0 1.0 1.0 4.0 4.2 4.0 4.0 2.0 2.0 2.0 2.0 2
Total Gate Capacitance CGS fF 19.1 15.3 9.5 7.7 38.1 32.1 38.1 30.6 19.1 19.1 15.2 19.1 15.21
CGB fF 3.44 5.19 2.22 2.59 5.88 10.70 5.88 10.38 3.44 3.44 4.99 3.44 4.99
CGD fF 2.0 1.7 1.0 0.0 4.0 3.7 4.00 3.47 2.0 2.0 1.7 2.0 1.735
Drain-Body Capacitance AD (µm)2 9 9 9 9 18 18.792 18 18 9 9 9 9 9
CJ (D) fF 3.6 3.6 3.6 3.6 7.2 7.5 7.2 7.2 3.6 3.6 3.6 3.6 3.6
PD µm 13.6 13.6 13.6 13.6 27.2 28.1 27.2 27.2 13.6 17.2 13.6 13.6 13.6
CJSW (D) fF 4.1 4.1 4.1 4.1 8.2 8.4 8.2 8.2 4.1 5.2 4.1 4.1 4.08
CDB0 fF 7.7 7.7 7.7 7.7 15.4 15.9 15.4 15.4 7.7 8.8 7.7 7.7 7.68
Source-Body Capacitance AS (µm)2 18 18 9 9 27 28.188 27 27 18 13.5 18 18 18
CJ (S) fF 7.2 7.2 3.6 3.6 10.8 11.3 10.8 10.8 7.2 5.4 7.2 7.2 7.2
PS µm 27.2 27.2 13.6 13.6 40.8 42.1 40.8 40.8 27.2 25.8 27.2 27.2 27.2
CJSW (S) fF 8.2 8.2 4.1 4.1 12.2 12.6 12.2 12.2 8.2 7.7 8.2 8.2 8.16
CSB0 fF 15.4 15.4 7.7 7.7 23.0 23.9 23.0 23.0 15.4 13.1 15.4 15.4 15.36
Intrin. Gain AVI=gm/gds V/V 80 109.0909090909 80 108.7248322148 80 52.8764634639 80 158.8217613466 80 80 153.0681818182 80 153.5653166001
Intrin. BW fTi MHz 1632.0 2115.0 1632.0 2115.0 1632.0 2047.4 1631.9598656884 2155.8189825743 1632.0 6527.8 2198.2 1632.0 2196.6179792166

PMOS

MOS Devices Mirror Mirror Diff pair
Type Input Design, Process VAL Choices Parameter Units M5 M6,M7 M8 M9 M10 M1, M2
Hand Simulated Hand Simulated Hand Simulated Hand Simulated Hand Simulated Hand Simulated
ID µA 25 25 50 50.59 25 24.99 25 25.72 25 25.66 12.5 100 100 12.5
VEFF= VGS-VT V 0.25 0.251 0.25 0.211 0.25 0.222 0.25 0.222 0.25 0.25 0.25 0.25 0.2
L (eff) µm 1 1 1 1 1 1 1 1 1 1 1 1 1 1
VSB V 0 0 0 0 0 0 0 0 0 0 0.35 0.35 0 0.4065
M --- 4 4 8 8 4 4 4 4 4 4 2 2 4 2
VAL V/µm 8 8 8 8 8 8 8 8 8 8 8 8 8 8
Geometry S = W/L --- 27.9999986 28 55.9999972 54.4 27.9999986 28 27.9999986 26.4 27.9999986 28 13.9999993 111.9999944 27.9999986 14
W (Total) µm 27.9999986 28 55.9999972 54.4 27.9999986 28 27.9999986 26.4 27.9999986 28 13.9999993 111.9999944 27.9999986 14
WL µm2 27.9999986 28 55.9999972 54.4 27.9999986 28 27.9999986 26.4 27.9999986 28 13.9999993 111.9999944 27.9999986 14
Bias Voltages VT V -1 -0.724 -1 -0.9331 -1 -0.933 -1 -0.933 -1 -0.933 -1.1341640786 -1.1341640786 -1 -1.043
∆VT V 0 -0.276 0 -0.0669 0 -0.067 0 -0.067 0 -0.067 1.8841640786 0.1565247584 0.1565247584 1.793
VGS V -1.25 -0.975 -1.25 -1.144 -1.25 -1.155 -1.25 -1.155 -1.25 -1.147 -1.3841640786 -1.3841640786 -1.25 -1.243
VDS,Sat V 0.183 0.181 0.183 0.199 0.183 0.208 0.183 0.207 0.183 0.201 0.183 0.183 0.183 0.200
Small Signal Parameters gm/ID V-1 8 10.36 8 9.1 8 8.72 8 8.73 8 9.05 8 8 8 9.27
gm µS 200 259.2 400 460.4 200 217.9 200 224.6 200 232.2 100 800 800 115.9
VA V 8.00 8.00 8.00 8.00 8.00 8.00 8.00 8.00 8.00 8.00 8.00 8.00 8.00 8.00
gds µS 3.13 2.38 6.25 4.37 3.13 5.42 3.13 2.53 3.13 2.56 1.56 12.50 12.50 1.05
η --- 0.335 0.335 0.335 0.335 0.335 0.335 0.335 0.335 0.335 0.335 0.280 0.280 0.335 0.280
gmb µS 67.1 84.6 134.2 154.4 67.1 62.8 67.1 64.8 67.1 66.9 28.0 223.8 268.3 27.9
Intrinsic Gate Capacitance CGOX fF 71.7 71.7 143.4 143.4 71.7 71.7 71.7 71.7 71.7 71.7 35.8 286.7 71.7 35.8
Cgsi fF 47.8 47.8 95.6 95.6 47.8 47.8 47.8 47.8 47.8 47.8 23.9 191.1 47.8 23.9
Cgbi fF 6.4 6.4 12.8 12.8 6.4 6.4 6.4 6.4 6.4 6.4 3.2 25.6 6.4 3.2
Cgdi fF 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00
Extrinsic Gate Capacitance CGSO fF 5.60 5.60 11.20 11.20 5.60 5.60 5.60 5.60 5.60 5.60 2.80 22.40 5.60 2.80
CGBO fF 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00
CGDO fF 5.60 5.60 11.20 11.20 5.60 5.60 5.60 5.60 5.60 5.60 2.80 22.40 5.60 2.80
Total Gate Capacitance CGS fF 53.39 15.32 106.77 94.17 53.39 48.74 53.40 45.64 53.40 48.61 26.69 213.55 53.39 24.20
CGB fF 7.39 5.18 13.78 13.98 7.39 7.02 7.40 6.85 7.40 7.09 4.19 26.56 7.39 3.38
CGD fF 5.60 1.74 11.20 14.45 5.60 7.61 5.60 7.00 5.60 7.46 2.80 22.40 5.60 3.73
Drain-Body Capacitance AD (µm)2 25.19999874 25.2 50.39999748 50.4 25.19999874 25.2 25.19999874 25.2 25.19999874 25.2 12.59999937 100.79999496 25.19999874 12.6
CJ (D) fF 17.6 17.6 35.3 35.3 17.6 17.6 17.6 17.6 17.6 17.6 8.8 70.6 17.6 8.8
PD µm 35.2 35.2 70.4 70.4 35.2 35.2 35.2 35.2 35.2 35.2 17.6 115.6 35.2 17.6
CJSW (D) fF 10.6 10.6 21.1 21.1 10.6 10.6 10.6 10.6 10.6 10.6 5.3 34.7 10.6 5.3
CDB0 fF 28.2 28.2 56.4 56.4 28.2 28.2 28.2 28.2 28.2 28.2 14.1 105.2 28.2 14.1
Source-Body Capacitance AS (µm)2 37.79999811 37.8 62.99999685 63 37.79999811 37.8 37.8 37.8 37.8 37.8 25.19999874 201.59998992 37.79999811 25.2
CJ (S) fF 26.5 26.5 44.1 44.1 26.5 26.5 26.5 26.5 26.5 26.5 17.6 141.1 26.5 17.6
PS µm 52.8 52.8 88.0 88.0 52.8 52.8 52.8 52.8 52.8 52.8 35.2 231.2 52.8 35.2
CJSW (S) fF 15.8 15.8 26.4 26.4 15.8 15.8 15.8 15.8 15.8 15.8 10.6 69.4 15.8 10.6
CSB0 fF 42.3 42.3 70.5 70.5 42.3 42.3 42.3 42.3 42.3 42.3 28.2 210.5 42.3 28.2
Intrin. Gain AVI=gm/gds V/V 64 109.0909090909 64 105.3788052186 64 40.2029520295 64 88.7045813586 64 90.5616224649 64 64 64 110.5916030534
Intrin. BW fTi MHz 587.6 761.5 587.6 676.0 587.6 639.8 587.3 659.5 587.3 681.8 587.5507772367 587.6 2350.2 680.666343334

Process

Parameter Units NMOS PMOS
COX' fF/µm2 2.56 2.56
µ0 cm2/VS 437.5 152.34
n0 1.4 1.365
µ0COX' µA/V2 112 39
µ0COX'/n0 µA/V2 80 28.57143
VT0 V 0.75 -1
Y V1/2 0.7 0.6
PHI = 2øF V 0.8 0.8
CGSO, CGSO fF/µm 0.2 0.2
CGBO fF/µm 1 1
CJ fF/µm 0.4 0.7
PB V 0.8 0.8
MJ 0.5 0.5
CJSW fF/µm 0.3 0.3
PBSW V 0.8 0.8
MJSW 0.33 0.33
WDIF µm 1.8 1.8

__MACOSX/FINAL PROJECT/._two_stage.xlsx

FINAL PROJECT/Two-stage_OTA_with_CMFB_transistor_sizing_tips.pdf

__MACOSX/FINAL PROJECT/._Two-stage_OTA_with_CMFB_transistor_sizing_tips.pdf

FINAL PROJECT/MOS Parameter Spreadsheet_hand_calculation (1).xlsx

NMOS

NMOS Devices
Type Parameter Units
Input Design, Process VAL Choices ID µA 100 100 100 100 100 100
VEFF = VGS-VT V 0.25 0.25 0.25 0.5 0.5 0.5
L (eff) µm 0.5 0.85 1.9 0.5 0.85 1.9
VSB V 0 0 0 0 0 0
M … 2 2 4 1 2 2
VAL V/µm 9 17.65 16.26 9 17.65 16.26
Geometry S=W/L … 40 40 40 10 10 10
W (total) µm 20 34 76 5 8.5 19
WL (total) (µm)2 10 28.9 144.4 2.5 7.225 36.1
Bias Voltages VT V 0.7 0.7 0.7 0.7 0.7 0.7
ΔVT V 0 0 0 0 0 0
VGS V 0.95 0.95 0.95 1.2 1.2 1.2
VDS,sat V 0.179 0.179 0.179 0.357 0.357 0.357
Small Signal Param gm/ID V-1 8 8 8 4 4 4
gm µS 800 800 800 400 400 400
VA V 4.50 15.00 30.89 4.50 15.00 30.89
gds µS 22.22 6.67 3.24 22.22 6.67 3.24
η … 0.391 0.391 0.391 0.391 0.391 0.391
gmb µS 313.0 313.0 313.0 156.5 156.5 156.5
Intrins. Gate Capac. CGOX fF 25.6 74.0 369.7 6.4 18.5 92.4
Cgsi fF 17.1 49.3 246.4 4.3 12.3 61.6
Cgbi fF 2.4 7.0 35.2 0.6 1.8 8.8
Cgdi fF 0.0 0.0 0.0 0.0 0.0 0.0
Extrins. Gate Overlap. C CGSO fF 4 6.8 15.2 1 1.7 3.8
CGBO fF 0.5 0.85 1.9 0.5 0.85 1.9
CGDO fF 4 6.8 15.2 1 1.7 3.8
Total Gate Capac. CGS fF 21.1 56.1 261.6 5.3 14.0 65.4
CGB fF 2.9 7.9 37.1 1.1 2.6 10.7
CGD fF 4.0 6.8 15.2 1.0 1.7 3.8
Drain-Body Capac. AD (µm)2 18 30.6 68.4 9 7.65 17.1
CJ (D) fF 7.2 12.2 27.4 3.6 3.1 6.8
PD µm 23.6 37.6 83.2 13.6 12.1 22.6
CJSW (D) fF 7.1 11.3 25.0 4.1 3.6 6.8
CDB0 fF 14.3 23.5 52.3 7.7 6.7 13.6
Source-Body Capac. AS (µm)2 36 61.2 102.6 9 15.3 34.2
CJ (S) fF 14.4 24.5 41.0 3.6 6.1 13.7
PS µm 47.2 75.2 124.8 13.6 24.2 45.2
CJSW (S) fF 14.2 22.6 37.4 4.1 7.3 13.6
CSB0 fF 28.6 47.0 78.5 7.7 13.4 27.2
Intrin. Gain AVI=gm/gds V/V 36 120.02 247.152 18 60.01 123.576
Intrin. BW fTi MHz 6527.8 2258.8 452.1 13055.7 4517.5 904.1
Parameters Units NMOS
Cox' fF/µm2 2.56
µ0 cm2/VS 437.5
n0 1.4
µ0Cox' µA/V2 112
µ0Cox'/n0 µA/V2 80
VT0 V 0.7
Y V1/2 0.7
PHI = 2ФF V 0.8
CGSO, CGDO fF/µm 0.2
CGBO fF/µm 1
CJ fF/µm2 0.4
PB V 0.8
MJ 0.5
CJSW fF/µm 0.3
PBSW V 0.8
MJSW 0.33
WDIF µm 1.8

PMOS

PMOS Devices
Type Parameter Units
Input Design, Process VAL Choices ID µA 100 100 100 100 100 100
VEFF = VGS-VT V 0.25 0.25 0.25 0.5 0.5 0.5
L (eff) µm 0.5 0.85 1.9 0.5 0.85 1.9
VSB V 0 0 0 0 0 0
M … 4 4 8 2 4 4
VAL V/µm 8 8 8 8 8 8
Geometry S=W/L … 112 112 112 28 28 28
W (total) µm 56 95.2 212.8 14 23.8 53.2
WL (total) (µm)2 28 80.92 404.32 7 20.23 101.08
Bias Voltages VT V -1 -1 -1 -1 -1 -1
ΔVT V 0 0 0 0 0 0
VGS V -1.25 -1.25 -1.25 -1.5 -1.5 -1.5
VDS,sat V 0.183 0.183 0.183 0.366 0.366 0.366
Small Signal Param gm/ID V-1 8 8 8 4 4 4
gm µS 800 800 800 400 400 400
VA V 4.00 6.80 15.20 4.00 6.80 15.20
gds µS 25.00 14.71 6.58 25.00 14.71 6.58
η … 0.335 0.335 0.335 0.335 0.335 0.335
gmb µS 268.3 268.3 268.3 134.2 134.2 134.2
Intrins. Gate Capac. CGOX fF 71.7 207.2 1035.1 17.9 51.8 258.8
Cgsi fF 47.8 138.1 690.0 11.9 34.5 172.5
Cgbi fF 6.4 18.5 92.3 1.6 4.6 23.1
Cgdi fF 0.0 0.0 0.0 0.0 0.0 0.0
Extrins. Gate Overlap. C CGSO fF 11.2 19.04 42.56 2.8 4.76 10.64
CGBO fF 0.5 0.85 1.9 0.5 0.85 1.9
CGDO fF 11.2 19.04 42.56 2.8 4.76 10.64
Total Gate Capac. CGS fF 59.0 157.1 732.6 14.7 39.3 183.1
CGB fF 6.9 19.3 94.2 2.1 5.5 25.0
CGD fF 11.2 19.0 42.6 2.8 4.8 10.6
Drain-Body Capac. AD (µm)2 50.4 85.68 191.52 12.6 21.42 47.88
CJ (D) fF 35.3 60.0 134.1 8.8 15.0 33.5
PD µm 63.2 102.4 227.2 17.6 31 60.4
CJSW (D) fF 19.0 30.7 68.2 5.3 9.3 18.1
CDB0 fF 54.2 90.7 202.2 14.1 24.3 51.6
Source-Body Capac. AS (µm)2 75.6 128.52 239.4 25.2 32.13 71.82
CJ (S) fF 52.9 90.0 167.6 17.6 22.5 50.3
PS µm 94.8 153.6 284 35.2 46.5 90.6
CJSW (S) fF 28.4 46.1 85.2 10.6 14.0 27.2
CSB0 fF 81.4 136.0 252.8 28.2 36.4 77.5
Intrin. Gain AVI=gm/gds V/V 32 54.4 121.6 16 27.2 60.8
Intrin. BW fTi MHz 2350.2 813.2 162.8 4700.4 1626.4 325.5
Parameters Units PMOS
Cox' fF/µm2 2.56
µ0 cm2/VS 152.34
n0 1.365
µ0Cox' µA/V2 39
µ0Cox'/n0 µA/V2 28.57143
VT0 V -1
Y V1/2 0.6
PHI = 2ФF V 0.8
CGSO, CGDO fF/µm 0.2
CGBO fF/µm 1
CJ fF/µm2 0.7
PB V 0.8
MJ 0.5
CJSW fF/µm 0.3
PBSW V 0.8
MJSW 0.33
WDIF µm 1.8

__MACOSX/FINAL PROJECT/._MOS Parameter Spreadsheet_hand_calculation (1).xlsx

FINAL PROJECT/xid-126356604_1.jpg

__MACOSX/FINAL PROJECT/._xid-126356604_1.jpg

FINAL PROJECT/Rc and Cc calculation.pdf

__MACOSX/FINAL PROJECT/._Rc and Cc calculation.pdf

FINAL PROJECT/Final Project Two-Stage op-amp table (1).xlsx

Sheet1

Parameter Description Design Selection Value calculated from SPICE Op Point Value found from SPICE Simulation
Operating voltages
VDD Positive supply voltage 1.65 V 1.65 V
VSS Negative supply voltage -1.65 V -1.65 V
VINCM Input common-mode voltage 0 V 0 V
VOUTCM Output common-mode voltage within ±0.1 V 257.2 μV
Load and compensation capacitances/resistances
CL Load capacitances to ground, each output 2 pF 2 pF
CC Compensation capacitor 0.5 pF .5 pF
RC Compensation resistor 23 kΩ 23 kΩ
Supply currents
IDD Total positive supply current 200 μA 202.55 μA
ISS Total negative supply current 200 μA 202.55 μA
Minimum/Maximum input/output voltage levels
VINCM+ Maximum common-mode voltage (inputs tied together) 0.123 V 0.194 V 0.234 V
VINCM- Minimum common-mode voltage (inputs tied together) -2.264 V -2.178 V -2.008 V
VOUT+, VOUT- (max.) Maximum single-ended output voltage (near full performance) 1.467 V 1.343 V 1.36 V
VOUT+, VOUT- (min.) Minimum single-ended output voltage (near full performance) -1.471 V -1.461 V -1.40 V
VOUT+, VOUT- (max.) Maximum single-ended output voltage (limited value) 1.539 V 1.539 V 1.451 V
VOUT+, VOUT- (min.) Minimum single-ended output voltage (limited value) -1.542 V -1.542 V -1.471 V
Two-stage op amp
IPAIR Total differential pair bias current 25 μA 25 μA
IOUT Output statge bias current, one side 50 μA 50.59 μA
ICM,PAIR Total common-mode feedback differential pair current 50 μA 51.38 μA
GM,PAIR Differential pair gm (gm of single device) 100 μS 115.9 μS
AV,1st Differential voltage gain of first stage 35.587 V/V 51.74 V/V
GM,OUTPUT Output device gm (gm of single device) 400 μS 460.4 μS
AV,2nd Differential voltage gain of second stage 35.56 V/V 68.89 V/V
AVDIF Total differential voltage gain 1265.31 V/V 3564.5 V/V 1000 V/V (AC sweep)
ROUT,SE Single-ended output resistance 88.89 kΩ 130.38 kΩ 130.38 kΩ
ROUT,DIF Differential output resistance 18.27 kΩ 19.55 kΩ 19.55 kΩ
fT Unity gain frequency for differential gain 31.83 MHz 36.89 MHz 56.23 MHz (AC sweep)
PM Phase margin at unity gain frequency (distance to -180°) 71 ° (AC sweep)
fOUTPUT Parasitic pole frequency at output, 1 side 31.83 MHz 42.05 MHz
Slew rate (large signal operation)
VOUT+, VOUT- (SR+) Positive slew rate for single-ended outputs 20 V/μs 20.24 V/μs 13.62 V/μs
VOUT+, VOUT- (SR-) Negative slew rate for single-ended outputs 50 V/μs 49.98 V/μs 13.6 V/μs
VOUTDIF (SR+) Positive slew rate for differential outputs 40 V/μs 40.48 V/μs 25.51 V/μs
VOUTDIF (SR-) Negative slew rate for differential outputs 100 V/μs 99.96 V/μs 25.6 V/μs
Closed-loop frequency and transient response for unity-gain capacitive feedback
AVDIF (CL) Closed-loop differential voltage gain 1.0 V/V @10 kHz
f-3dB (CL) Closed-loop differential voltage gain -3 dB frequency 29.35 MHz
Overshoot Small-signal output overshoot for 10 mV step input 15%

Sheet2

Sheet3

__MACOSX/FINAL PROJECT/._Final Project Two-Stage op-amp table (1).xlsx

FINAL PROJECT/Project_assignment.pdf

__MACOSX/FINAL PROJECT/._Project_assignment.pdf

__MACOSX/FINAL PROJECT/._Final_project.docx

FINAL PROJECT/How to make the background white for the shematic.pdf

Step 1. The image will download with its original colors, so it is advised to change the wire colors before trying

to export the schematic image.

Select the wire selection tool.

Select the entirety of the schematic ensuring all wires have been selected.

Right click on any wire and select the property editor. Or simply press q.

In the pop up window in the “apply to” section, apply the changes to all wire segments of any net. Then

proceed to change the color of the lines to anything dark. Select apply, then ok at the bottom of the

window.

Step 2. Select the file menu, then select export image.

From here you can either change the background color to white or select the transparent background

option. Both will result in the same image. The file saving feature will only save within the cadence

system, so when saving the file be sure to place it in a folder where you can find it, I placed mine within

the schematic files of the circuit itself.

I named my file “Schematic-image.” Right click and download the file onto your preferred location.

Prepared by: Robin Velazquez

__MACOSX/FINAL PROJECT/._How to make the background white for the shematic.pdf

FINAL PROJECT/Inked_folded_cascode_OTA_LI.jpg

__MACOSX/FINAL PROJECT/._Inked_folded_cascode_OTA_LI.jpg