Lab 7

ENGR 2105 Experiment #8 – Circuit Design Problems

1. Introduction and Goal: Designing circuits is a large part of electrical engineering. After learning some basic circuit principles, it is time to try

your hand at two designs. This exercise offers an opportunity to rate your

progress in mastering the fundamentals covered in ENGR 2105.

2. Equipment List: The following instruments and components are required • Multisim

• Calculator

3. Experimental Theory: Today’s design problems are (1) a resistive voltage divider and (2) a reactance reduction circuit. The theory required for the two

exercises is covered below.

3.1 DC Voltage Divider: Passive voltage dividers (voltage dividers without amplifiers or active elements such as transistors) are not used extensively,

but can be useful where (1) a small amount of power is required at a

different voltage than is available, or (2) cost constraints are high, since a

resistor voltage divider is simple and inexpensive.

Figure 1: Schematic of a Voltage Divider

3.1.1 Figure 1 above shows such a voltage divider. Say the voltage requirement is 0.3V. The output voltage is I·R2; 𝐼 = 𝑉 (𝑅1+𝑅2)⁄ (assuming RL, as shown in Fig.1, is not yet connected). If 70% of the

voltage drop is in the upper (R1) resistor, the desired output voltage

will be 0.3 V. Since total resistance RT of the two resistors is RT = R1 +

R2, then to get 0.3 V across the smaller resistor, we need R1 =0.7RT,

and R2 = 0.3RT. Clearly, if R2 is 30% of the total resistance, then the

voltage drop on R2 is 0.3V. That is, 𝑅2 (𝑅1 + 𝑅2)⁄ . Clearly, a voltage divider cannot increase a voltage.

3.1.2 From Experiment 2, the parallel resistance of two resistors is less than either. When the load resistor is connected, the voltage drop across R2

is no longer 0.3V, but a lower voltage (since the parallel resistance of

R2 and RL is less than that of R2).

3.1.3 The desired voltage is much lower for 𝑅𝐿 ≤ 𝑅2. In Figure 2, for example, what if R1 = 70Ω, R2 = 30Ω, and RL = 1Ω? Then without the

load, the voltage across R2 is 0.3V. where V is the input voltage. But

connect R2 and RL in parallel, and we know that the combined

resistance will be less than 1Ω! The voltage across RL will be ≈ 1.5%

of V, or ~ 2% of the input voltage. The divider is useless.

3.1.4 The size of RL is clearly important to the design. The divider must be designed so that with RL in place, output voltage of the divider is in

the desired range. This ability to maintain correct voltage under load

is called “voltage regulation.”

3.1.5 Thus a resistive voltage divider design has two specifications: First, an output voltage range is specified, (e.g., 0.45 V to 0.55 V, V the

input voltage). Second, a resistance range for RL is specified. If a load

Resistor is >> R2 the parallel resistance of R2 and RL is ≈ R2).

3.1.6 In Fig. 2, assume the desired output voltage is 0.3V, ±10%. Then

regardless of the values for RL, the output voltage must be between 0.27V

to 0.33V. Then R1 and R2 are chosen so that with the largest RL in place

(the largest parallel resistance of R2 and RL), the output voltage of the

divider must ≤ 0.33V. For the smallest RL, (resulting in the lowest

parallel resistance), the voltage must be ≥ 0.27V.

3.1.7 The following steps make it easy to solve for the resistors: 3.1.7.1 For RLmin (low end of RL), choose R2 such that RLmin > 10R2. 3.1.7.2 Now choose R1 such that [(𝑅2 𝑅1 + 𝑅2⁄ )]𝑉 = 𝑑𝑒𝑠𝑖𝑟𝑒𝑑 𝑣𝑜𝑙𝑡𝑎𝑔𝑒 3.1.7.3 Example: The input voltage is 10V. The desired voltage is 3V±10%

(or 2.7V – 3.3V). The range of RL is 10-50 kΩ. Then with RLmin = 10

kΩ, using 3.1.7.1 above, chose R2 = 1kΩ. Then R1 = 2.33 kΩ. There

are no standard resistors of that value, but there is a 2.2 kΩ standard

resistor, which should be close enough. The result: R2 = 1kΩ and R1

= 2.2 kΩ.

3.1.7.4 To check this result, with the minimum load resistor value of 10KΩ, the parallel resistance of R2 and RL ≈ 909Ω. This would give a

minimum voltage of [909Ω (2200Ω + 909Ω)⁄ ](10𝑉) = 2.9𝑉, which is above the minimum allowable of 2.7V. With the maximum load =

50KΩ, the parallel resistance of R2 and RL ≈ 980Ω. The maximum

voltage is then [980Ω (2200Ω + 980Ω)⁄ ](10𝑉) = 3.1𝑉, well below the maximum 3.3V.

3.1.7.5 A last note: R1 and R2 must not only satisfy the equation in 3.1.9.2, but also not dissipate so much power that they burn up. That is, we

would not want to use 2.2Ω and 1Ω resistors instead of the 2.2K and

1K Ω resistors, if they were low-power resistors such as those in most

of our experiments, because they would quickly burn up. Remember

to choose reasonable resistor values since, in your lab problem, you

will be using ¼ W resistors.

3.1.7.6 For the resistors chosen above? Remembering that I=V/R, the current in our divider with V = 10V would be 10 (1000 + 2200)⁄ = 0.003𝐴, or 3mA. Since power in a resistor 𝐼2𝑅, then the power in the two resistors is 0.0032 · (3200) = 0.026 Watts, well within the capacity of the two ¼ W resistors.

3.2 Bringing Current and Voltage Into Phase in an AC Circuit: In an inductive AC circuit (ref. Exp. #5), current lags voltage by some phase angle. For

|𝑗𝜔𝐿| >> 𝑅, the phase angle can approach 90 degrees. Most companies use many AC motors (in air conditioners, on assembly lines, etc.), and

electric motors work by virtue of inductive coils. Thus large industries

present an inductive load to the power company.

3.3 This inductive load draws current. Inductive current is “imaginary” mathematically, but it is real insofar as the power company demands that it

be paid for! For a large AC power user, reducing inductive load (making the

AC voltage and current as close to in-phase as possible) will reduce the

power bill. The common name for reducing the phase angle is “making the

power factor one.” The “power factor” is 𝑐𝑜𝑠 𝜃, where θ is the voltage/current phase angle in an AC circuit. If the power factor = 1, then

the phase angle = 0 (𝑐𝑜𝑠 0 = 1), and there is no reactive current. 3.3.1.1 In Fig. 3, the sinusoidal signal generator voltage is 𝑣(𝑡) = 𝑉 𝑐𝑜𝑠𝜔𝑡 .

3.3.2 Experiment 5 demonstrated that V and I are not in phase in this circuit;

current lags voltage. Can we reduce the phase angle to 0?

3.3.3 Remember: Inductive impedance = 𝑍𝐿 = 𝑗𝑋𝐿 = 𝑗𝜔𝐿; 𝑍𝐿 is always a positive, imaginary value. Capacitive impedance = 𝑍𝐶 = −𝑗𝑋𝐶 = −𝑗/𝜔𝐶; 𝑍𝐶 is always a negative, imaginary number.

3.3.4 Since inductive and capacitive impedances are imaginary and of opposite sign, adding capacitive reactance of the same magnitude as the inductive

reactance in a circuit would result in zero reactance and therefore no

reactive current. In Worksheet #8 you will develop a formula to make

circuit reactance = 0.

3.3.5 When adding capacitance to an inductive circuit, it may be necessary to use several capacitors to achieve desired capacitance. We saw in

Experiment 5 that capacitors in series add reciprocally and inferentially,

capacitors in parallel add directly.

3.3.6 For example, paralleling three 1-μF capacitors = 3 μF; 5 μF results from two series 10 μF capacitors. In Fig. 4, a correctly chosen capacitor could

bring the power factor to 1 (𝜃 = 0). 3.3.7 For companies with a heavy inductive load, adding a capacitor bank can

significantly reduce their electrical power bill.

4. Pre-Work: Prior to the lab, study this outline and review capacitive and inductive impedance. Complete formula derivations in the Worksheet.

5. Design Problems: Design the circuits, as required, in 5.1 and 5.2, below. 5.1 A DC Voltage Divider Circuit: Design a voltage divider as follows: 5.1.1 Input voltage is 10 VDC; desired output of 4 VDC ±0.3 V. The range of

the load resistance, RL, is 20-100 KΩ. Over this range, output voltage

must be (3.7-4.3 V). That is, at 20 KΩ load, output voltage must be ≥ 3.7

V, and at 100 KΩ load, output voltage must be ≤ 4.3 V.

5.1.2 Construct the voltage divider in Multisim Live, and demonstrate that the voltage across the load resistance stays “in spec” over the range of RL.

5.1.3 Enter required data in your data sheet and take screen shots of your circuits.

5.2 An AC “Phase Compensated” Circuit: 5.2.1 Using a 10 mH inductor and a 16Ω resistor, make a circuit as shown in

Fig. 3, above.

5.2.2 Use an AC Voltage Source in Multisim. Set the voltage across the series RL circuit at 5Vp with a frequency of f=1000 Hz. Calculate 𝜔.

5.2.3 Add a combined voltage and current probe between the voltage source and the resistor.

5.2.4 Use the grapher to verify that the current is out of phase with the voltage source. Take a screenshot.

5.2.5 Using the inductance value specified above, calculate the inductive impedance, 𝑗𝜔𝐿, for this circuit. Calculate the capacitor required to make the capacitive impedance equal to the inductive impedance:

𝑗𝜔𝐿 = 1

𝑗𝜔𝐶

5.2.6 In Multisim, create the circuit shown in Figure 4 using the specified inductor, resistor, and calculated capacitor valuers.

5.2.7 Use the “Grapher” to verify that the phase shift is no longer present (i.e. θ = 0). This means there is no longer an imaginary component to the

impedance.

5.2.8 When the V-I phase match is correct. Take a screen shot. 6. Laboratory Area Cleanup: Wash your hands! 7. Writing the Laboratory Report: There is no report for Experiment 8. Upload

your Data Sheet and Screen Shots to eCampus.