Topics Mechanical Engineering - IC Packaging ( 3D packaging) project report

IC Assembly Technology – Wafer Chip Scale Packaging

Lecture 8

Wafer level packaging (WLP) / Wafer Chip Scale Packaging ( WCSP)

& Introduction to 3D Packaging

WLP/WCSP

Ultimate Down-Sizing Wafer Level CSP

Dicing

Wafer

Wafer Packaging

Dicing

QFP,BGA, CSP and other lead frame & substrate based packages

Packaging

WLP/WCSP

Wafer Level Packaging / Wafer Chip Scale Packaging

Wafer Level

Processing

BGA/CSP

Flip Chip

WLP•Electrical Performance •Low Profile

•Minimum materials

•Self Alignment

•Assembly

•Standardization

•High reliability

•Test

•Low Cost

•High yield

• Process Control

• Wafer level Inspection

P a c

k a g

e S

iz e

Miniaturization

Miniaturization

Miniaturization

PDIP

SOIC

TSSOP

SOT

TQFN

UTQFN

WCSP

Can

Tube

BGA

Packaging is enabling functional density increase:

What is WCSP & What is inside WCSP ? ( Fan -in WCSP)

• WCSP (Wafer Chip Scale Package) is a package type that is

• Completely processed in wafer and when the wafer is singulated , the package is complete. • The smallest form factor possible for a package with external leads/balls

• A WCSP may include • One or more dielectric layers, such as PI (polyimide) or PBO

(Polybenzoxazole) for insulation and stress buffering. • A Cu routing layer. • A UBM (Under Bump Metal) layer consisting of one or more

metals, such as Cu or Ni. • A solder ball.

Slides 5 -21 Ref: Pat Thompson ( Texas Instruments) lecture at UTD Feb 2020

5

Benefits of WCSP

• Batch processing to lower costs • All steps prior to pick and place are performed at the wafer level; this can result in an assembly

lot size of 10Ks to 100Ks; • Lower assembly capital costs

• Handling and shipping logistics can be streamlined: • Final test is done at the wafer level; savings in test and logistics can be as, or more, important than the manufacturing

cost • No need for Known Good Die - tested like other ICs

• ICs can be packaged in the fab and shipped directly to customers for surface mounting with conventional SMT

• Reduced total cycle time can minimize inventory requirements

• Functionality can be packed into a form factor as small as the die

6

2019 IEEE 69th ECTC │ Las Vegas, Nevada │ May 28 – May 31,

2019

WCSP challenges • Wafer bumping can be costly:

• Average bumping cost of ~US$200 for 200 mm wafer • “Small die” at 1mm2 for ~30,000 die/wafer; unit cost is $0.006 • “Medium die” at 9mm2 for ~3500 die/wafer; unit cost is $0.057 • “Large die” at 50mm2 for ~625 die/wafer; unit cost is $0.32

• High cost for poor yielding wafers

• Die shrink requires a new package

• Board-level reliability • High CTE mismatch between Si die and organic PCB

• Current carrying capacity • Solder has ~1% capability of Cu

• Mechanical robustness • Exposed Si

• SMT and PCB costs • HVM SMT processes migrate to FC assembly processes and tools at ~0.2mm spacing • PCB design rules drive more expensive substrates below ~0.4mm pitch

7

2019 IEEE 69th ECTC │ Las Vegas, Nevada │ May 28 – May 31,

2019

WCSP types • Bump directly on the pad

• Simplest WCSP • UBM directly on die metal pad w/solder ball on

UBM • Bump on pad w/dielectric

• Adds a layer of dielectric for stress buffer • BOPCOA (BOP on Copper Over Anything)

• Uses Cu layer for routing, redistribution • Requires VIATOP/planar PO at wafer fab • Most common WCSP in TI; TI unique

construction • RDL (Redistribution Layer)

• Uses initial dielectric layer as stress buffer for Cu, routing

• Enables use of standard PO at wafer fab • Typical industry construction

8

Bump on pad BOP

BOPCOA RDL

High level WCSP manufacturing flow 9

Bump fab Package probe AssemblyWafer fab Wafer probe

Cu

uubm

Incoming Clean

TiW / Cu Seed Dep

Polyimide expose & develop

Polyimide Spin

Ash performed

TiW / Cu Seed Dep

UBM

Resist Pattern

Cu Plate

Resist Strip

Ball placement

Reflow

Completed BOPCOA wafer

1 um W Vias

PO

COA plate

Resist PatternResist Strip

Seed Etch

Seed Etch

COA = 6,10 um thick

PI = 6 um thick

UBM = 10, 18, 35 um thick

Polyimide Oven Cure

TiW

COA

Si

Al

BOPCOA process flow

BOPCOA bump flow 11

RDL Process Flow 12

Post-bump fabrication images 13

STANDARD FLOWWCSP assembly flow

BG Taping Back Grinding Detaping Backside Laminate Oven Cure

Laser MarkWafer MountWafer SawTape and Reel

Animation created by M. Minoc,

Texas Instruments, Ref Pat Thompson (TI) Lecture at UTD Feb 2020

Mechanical saw 15

- Heat zone creates brittle poly silicon layer in scribe street near

center of wafer

- Weaker poly-silicon layer yields when stressed to separate die

from each other

- Metal layers split and tear during singulation

- Laser leaves no visible damage to wafer

- No material is removed

Laser singulation

WCSP package definition parameters

6

Nomenclature

• Y - indicates chipscale package (also used for picostar)

• 2nd Letter – indicates Pitch

• 3rd Letter – indicates Height

Pitch 2nd Letter

0.5 A

0.4 B

0.35 C

0.3 G

Height 3rd Letter

0.55 F

0.5 G

0.4 H

0.35 J

PKG Bump

Pitch

Max Package

Height (mm)

UBM

Diameter

Ball Diameter

(pre-attach)

Bump Diameter

(post-reflow)

Bump

Height

BG Value

(mil)

Max Array

Size

YAF 500 0.55 230 250 265 200 10 11x11

YAH 500 0.4 230 200 230 140 7 7x7

YBG 400 0.5 230 225 250 170 10 9x9

YBH 400 0.4 200 180 205 130 7 6x6

YBJ 400 0.35 180 150 180 100 7 5x5

YCG 350 0.5 200 180 205 130 10 5x5

YCH 350 0.4 200 180 205 130 7 5x5

YCJ 350 0.35 180 150 180 100 7 4x4

YGJ 300 0.35 180 150 180 100 7 3x3

Post-assembly images 18

WCSP Assembly issues 19

Edge chipping

Subsurface chipping

Wafer cracking

What is Power WCSP ?

• Power WCSP is a new low-profile WCSP platform with enhanced electrical and thermal performance

• Benefits: • Thin package profile (0.3mm package height max) • Better current handling capacity and thermal

performance obtained through a combination of larger cross-sectional area and a lower electrical/thermal resistance interconnect structure

• Design flexibility

• Applications: Modules that prefer better electrical and thermal as well as require thin package

0.3mm max

Introduction to 3D packaging

3D Packaging Classifications

• Chip on Chip ( stacked chips/ bare dies- unencapsulated chips)

• Package on Package ( including stacked multi chip modules)

• Wafer Level Stacking / 3D ICs

3D Packaging

3D packaging 3D- Stacking Category

• Staked wWafer level stacking

• Stacked Bare Die

• Stacked Packaged

• Stacked Multichip Modules

Source : Alpine Microsystems

Ref: Hynix

Bottom DieSpacer Top Die

Bottom DieSpacer Top Die

3D packaging

Through-silicon via (TSV) or through-chip via is

vertical electrical connection (via) that passes completely

through a silicon wafer or die. TSVs are high performance

interconnect techniques used as an alternative to wire-

bond and flip chips to create 3D packages and 3D integrated

circuits. Compared to alternatives such as package-on-

package, the interconnect and device density is substantially

higher, and the length of the connections becomes shorter.

3D Packaging

3D packaging with TSVs ( Through Silicon Vias)

3D packaging with TSV examples

3D with TSV : memory on top of logic with TSV 3D TSV : Logic on top of memory with TSV

3D packaging

Ref Intel

Foveros 3D

Dec 2018 announcement

A combination of Flip Chip

& Through Silicon Via

( TSV ) connections

Samsung Announces Availability of its Silicon-Proven 3D IC Technology

for High-Performance Applications August 13, 2020

Samsung 'X-Cube' enables industry-first 3D SRAM-logic working silicon at 7nm and

beyond. Bandwidth and density can be scaled to suit diverse design requirements in

emerging applications

Samsung Electronics, a world leader in advanced semiconductor technology, today announced the immediate availability of its silicon-proven 3D IC packaging technology, eXtended-Cube (X-Cube), for today’s most advanced process nodes. Leveraging Samsung’s through-silicon via (TSV) technology, X-Cube enables significant leaps in speed and power efficiency to help address the rigorous performance demands of next-generation applications including 5G, artificial intelligence, high-performance computing, as well as mobile and wearable.

“Samsung’s new 3D integration technology ensures reliable TSV interconnections even at the cutting-edge EUV process nodes,” said Moonsoo Kang, senior vice president of Foundry Market Strategy at Samsung Electronics. “We are committed to bringing more 3D IC innovation that can push the boundaries of semiconductors.”

3D Packaging

3D Packaging

*The image shown is for illustration purpose only.

With Samsung’s X-Cube, chip designers can enjoy greater flexibility to build custom solutions that best suit their unique requirements.

The X-Cube test chip built on 7nm uses TSV technology to stack SRAM on top of a logic die, freeing up space to pack more memory into a smaller

footprint.

Enabled by 3D integration, the ultra-thin package design features significantly shorter signal paths between the dies for maximized data transfer

speed and energy efficiency. Customers can also scale the memory bandwidth and density to their desired specifications.

Samsung X-Cube’s silicon-proven design methodology and flow are available now for advanced nodes including 7nm and 5nm. Building on the initial design, Samsung plans to continue collaborating with global fabless customers to facilitate the deployment of 3D IC solutions in next-generation high-

performance applications.

More details on Samsung X-Cube will be presented at Hot Chips, an annual conference on high-performance computing, livestreamed Aug. 16-18.

eXtended-CubeSamsung X-CubeX-Cube

WLP/WCSP & 3D packaging summary

Fundamentals of Wafer chip scale packaging ( Fan -in WCSP) are

discussed.

Wafers scale packaging classifications & processes are dealt with.

A brief Introduction to 3D packaging is given.