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Introduction to Sequential Devices

Chapter 6

6.1 Models for Sequential Circuits

  • Elevator example:

6.1.1 Block Diagram representation

  • Memory devices:

- Semiconductor Flip-Flops

- Magnetic devices

- Delay lines

- Mechanical relays

- Rotation switches

- Etc…

  • This circuit can be represented by the following equations:

  • Vector Notation:

- All the vectors are time dependant

- Vector y has the value y(tk) at time tk.

- Input signals xi and output signal zi may assume a variety of forms

6.1.2 State Tables and Diagrams

  • The state diagram is a graphical representation of a sequential circuit in which the states are represented by circles and state transition of the circuit are shown by arrows.

  • State table : all circuit input vectors are listed across the top, while all state vectors are listed down the left side. Entries in the table are the next state and the output.

  • In practice, the state diagrams and tables are usually labeled using symbols rather than vectors. For example consider a sequential circuit with two present state variables y1, and y2. Then y= [y1 , y2]
  • Therefore the vector y can have any of the four possible values:
  • In general, if r represents the number of memory devices (number of states) in a circuit with Ns states then

  • Example: Consider the following sequential circuit with one input x, two state variables y1 and y2, and one output z.

  • The state diagram is:

  • Let assume that the circuit is initially in state A. now consider the application of the following input sequence to the circuit:

Hence the input sequence applied to the machine in state A cause the output sequence

Z=0100110111

And leaves the circuit in its final state C.

6.2 Memory Devices

  • -Most memory elements are bistable electronic circuits, that is, they exist indefinitely in one of two possible states, 0 and 1.
  • - Binary data are stored in a memory element by placing the element into the 0 state to store 0 and into the 1 state to store 1.
  • - The output of the memory indicates the present state.
  • - The input of the memory indicates the next state.
  • - Each memory element has one or more excitation inputs, so called because they are used to “excite” or drive the circuit into the desired state.

  • Two memory element types

The Two memory element types most commonly used in switching circuits are latches and flip-flops.

  • 1- LATCHES

A latch is a memory element whose excitation input signals control the state of

the device

A set latch: the excitation input forces the output of the device to 1.

A Reset latch: the excitation inputs force the device output to 0.

A Set-Reset latch: a latch with both set and reset excitation signals.

Timing Diagram of SR LATCH

  • 2- FLIP-FLOP:

A flip-flop differs from a latch in that it has a

control signal called clock. The clock signal

issues a command to the flip-flop, allowing it

to change states in accordance with its

excitation input signals.

  • - In both latches and flip-flops, the next state is determined by the excitation inputs.
  • - A latch changes state immediately in accordance with its inputs excitation signals.
  • - A flip-flop waits for its clock signal before changing states.
  • - The final state of a flip-flop is determined by its excitation values at the time the clock signal occurs.
  • - Multiple flip-flops in sequential circuit can be synchronized to a common clock signal so that they all change states together.

6.3 LATCHES

  • 6.3.1 Set-Reset Latch

6.3.1.1 Set latch

  • Consider an OR gate with both inputs are at logic 0 (which gives a 0 as output).
  • - Connect the output to one of the inputs and name the other input S (the gate remains stable with an output 0).
  • - If logic 1 is applied to the input S, then the output Q will be set to 1.
  • - Changing the input S back to 0 leaves the output Q at logic 1 because of the feedback to the other OR gate input.
  • - The device is permanently set to logic 1 => it is called a Set Latch

6.3.1.2 Reset Latch

Let’s use the NOR representation of a set latch, but instead of using the output of the NOT gate as output Q we use the output of the NOR gate as Q.

- Change the name of the input S to R.

- If logic 0 is applied initially to both inputs of the NOR gate, the output will be 1.

- Placing a logic 1 on the input R, forces the output to be 0 and the output of the NOT gate (the feedback signal) to be 1. Thus the latch output Q is reset to logic 0.

-Changing the input R back to 0 leaves the output at logic 0 because of the feedback signal.

- The output Q will remain at logic 0 permanently => it is called a Reset Latch.

  • Set-Reset Latch
  • - A combination of features of set and reset latches to set and reset the circuit as needed. (no permanent Setting or Resetting)

  • SR Latch Timing Diagrams:

The operation of any latch circuit may be described using a timing diagram. The figure bellow, illustrates the action induced in the cross-coupled NOR latches.

  • - This timing diagram represents an ideal situation in which all gate propagation delays are considered to be 0 called zero-gate-delay.
  • - In reality, every circuit output requires a nonzero amount of time to respond to changes on its inputs.
  • - Two types of delays associated with the input change and the transition in the output from high-to-low or from low-to-high.
  • - tPLH: the delay time between an input change and a corresponding low-to-high transition of an output.
  • - tPHL: the delay time between an input change and a corresponding high-to-low transition of an output.
  • SR Latch Excitation Table:

- The logical operation of the SR latch is summarized in the excitation table.

- The excitation table is simply the state table of the latch showing the state transitions for each combination of excitation inputs.

  • -Q (present state) is the state of the SR latch before an input combination is applied to S and R.
  • - Q* (next state) is the state of the SR latch after the SR inputs have been applied and steady-state result has been achieved.

  • 6.3.2 Gated SR Latch
  • To prevent state changes while S and R are changing, a control signal is often used.
  • Excitation Table:

  • When C= 0, nothing happen or the SR latch is said to be in Hold state. The value of next state will be equal to the value of present state Q* =Q. that can be concluded also from the equation.
  • When C=1, the gate SR latch behaves as a regular SR latch and the equation will become:

6.3.3 Delay Latch

  • The goal of using delay latches is to store data. Each latch will be used to store 1 bit data at a time.
  • The memory excitation input is simply the data to store.

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  • When C=0, Q* =Q then D-Latch is in the hold state
  • - When C=1, Q* =D then D-latch is said to be gated or enabled mode.

Setup time and Hold time

  • To ensure that a specific value on excitation input D will determine the final state of the latch, D must not be allowed to change too near the time at which the enable signal makes its transition from high to low.
  • - Two time constraints are defined for every latch device to identify when the excitation input must be held constant.
  • - The latch setup time tsu: the period of time immediately preceding the enable signal transition during which the excitation input must be stable.
  • - The latch hold time th: the period of time immediately following the enable signal transition during which the excitation input must be stable.

  • For any input transition at time T, no excitation input changes occur within the time period [T - tsu , T + th ].
  • - In addition to setup and hold time most gated latches require a minimum pulse width (tw) on the enable input to guarantee a correct state change.

6.4 Flip Flops

  • The latches presented thus far are not appropriate for use in synchronous sequential logic circuits because of their transparency.
  • - The outputs of the memory in the sequential circuit model that we have seen before are the input of the combinational circuit. Therefore, if we use latches, we will have the possibility of two cascaded combinational circuits feeding each other, generating oscillations and unstable transient behavior.
  • - A special timing control signal called a clock is used to restrict the change of states.

6.4.1 Master-Slave SR Flip-Flops

  • One method to prevent unstable situations is to employ two latches in a master-slave configuration.
  • - The enable signals of the two latches is driven by a complementary versions of a clock signal.
  • - When the clock signal is low: the master latch is in gated mode and the slave in hold.
  • - When the clock signal is high: the master latch is in hold mode and the slave enabled.
  • - While any latch is in hold mode, it ignores any further changes on its inputs.

  • Master-slave flip-flops are sometimes called pulse triggered because they require both logic 0 → 1 and 1 → 0 transitions of the clock input in order to operate properly.
  • On one transition the master operates (in enabled mode) and the slave in hold. On the other transition the slave operates (in enable mode) and the master in hold.

  • The only difference between the SR latch and the SR flip-flop is that the latch output reacts immediately to any input changes while the flip-flop output changes are controlled by the clock pulse.

6.4.2 Master Slave D Flip-Flops

  • - The master-slave D flip-flop can be built using two D latches. - The master latch is gate when the clock is low and the slave, when the clock is high. - QM = D during the transition 1 → 0. - Q* = D during the transition from 0 → 1.

6.4.3 Master-Slave JK flip-flop

  • May be considered an extension of SR.
  • JK operates as an SR FF whose inputs are assigned J=S and K=R.
  • In SR S=R=1 is not allowed but in JK , J=K=1, is used for a mode of operation.
  • This mode is called a toggle, 01, 10.
  • Four modes are (hold, set, reset, toggle).

6.4.4 Edge-triggered D FFs

  • Only sensitive to its excitation inputs during rising or falling transition of the clock.
  • Positive edge triggered 01
  • Negative edge triggered 10
  • Edge sensitive eliminates unstable transients by drastically reducing the period during which the input excitation signals are applied to the internal latches.

6.4.5 T Flip-Flops

  • A common building block used in sequential logic ccts that counts pulses on a signal line is T (trigger or toggle) Flip-flop.
  • Has only one excitation input T
  • Its function is to change (toggle) its state upon each negative-going transition of its excitation input signal.

  • CLOCKED T FF

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