Design a multi-cycle implementation of the reduced MIPS architecture
casi
DATA_I_O_Memory.zipdatamem.v
//DATAMEM.V // data: module datamem (clk,addr,we,datain,dataout); input clk; input we; input [31:0] addr; input [31:0] datain; output [31:0] dataout; reg [31:0] ram [0:15]; assign dataout = ram[addr[5:2]]; always @ (posedge clk) if (we) ram[addr[5:2]] <= datain; integer i; initial begin for (i = 0; i < 16; i = i + 1) ram[i] = 0; ram[4'h0] = 32'h00000000; ram[4'h1] = 32'h00000000; ram[4'h2] = 32'h0000aaaa; ram[4'h3] = 32'h00000000; ram[4'h4] = 32'h00000000; ram[4'h5] = 32'h00000000; ram[4'h6] = 32'h00000000; ram[4'h7] = 32'h00000000; ram[4'h8] = 32'h57656c63; ram[4'h9] = 32'h6f6d652e; ram[4'ha] = 32'h0a000000; ram[4'hb] = 32'hffffffff; ram[4'hc] = 32'h00000001; //ram[4'hd] = 32'h0000000A; ram[4'hd] = 32'h004C4840; ram[4'he] = 32'h00000000; ram[4'hf] = 32'h00000000; end endmodule
data_io_mem.v
//data_io_mem.v /* This file provides a wrapper for the single cycle computer * data memory. The assembler directive for data is used to base * the data memory at address 0x1000. The first 8 locations in data memory are reserved * for io data. The file generated by AsmSim will create * memory for these locations. However, the module will trap the * addresses for i/o and direct the data to physical registers. * */ module data_io_mem(clk, addr, we, datain, dataout, LEDR, LEDG, SW, R1, R2, R3, R4, R5); input clk, we; //clock and write enable inputs from sccomp input [31:0] addr, datain; //address and data input output [31:0] dataout; //IO registers output [17:0] LEDR; output [8:0] LEDG; output [31:0] R1, R2, R3, R4, R5; input [17:0] SW; wire [31:0] dataout_ram; reg wemem; //wire [31:0] LEDR, LEDG, R1, R2, R3, R4, R5; reg [31:0] datain_ram; reg [8:0] GreenLEDReg; reg [17:0] RedLEDReg, SwitchReg; reg [31:0] Out1Reg, Out2Reg, Out3Reg, Out4Reg, Out5Reg, dataout; reg IO_read_addr_error, IO_write_addr_error; always @(addr) //always output register values begin IO_read_addr_error =1'b0; if (addr < 13'h1020) case(addr) 13'h1000: dataout = {14'h0000,RedLEDReg}; 13'h1004: dataout = {24'h000000,GreenLEDReg}; 13'h1008: dataout = {14'h0000,SW}; 13'h100C: dataout = Out1Reg; 13'h1010: dataout = Out2Reg; 13'h1014: dataout = Out3Reg; 13'h1018: dataout = Out4Reg; 13'h101C: dataout = Out5Reg; default: IO_read_addr_error = 1'b1; endcase else dataout = dataout_ram; end //ooutput to peripherals assign LEDR = RedLEDReg; assign LEDG = GreenLEDReg; assign R1 = Out1Reg; assign R2 = Out2Reg; assign R3 = Out3Reg; assign R4 = Out4Reg; assign R5 = Out5Reg; always @(posedge clk) begin IO_write_addr_error =1'b0; if(we) if(addr <= 13'h1020) case(addr) 13'h1000: RedLEDReg <= datain; 13'h1004: GreenLEDReg <= datain; 13'h1008: IO_write_addr_error = 1'b1;// ignore sw address is input only 13'h100C: Out1Reg <= datain; 13'h1010: Out2Reg <= datain; 13'h1014: Out3Reg <= datain; 13'h1018: Out4Reg <= datain; 13'h101C: Out5Reg <= datain; default: IO_write_addr_error = 1'b1; endcase //else begin wemem <= we; datain_ram <= datain; end end datamem DataRam(clk, addr, wemem, datain/*_ram*/, dataout_ram); endmodule
