CIS computer science

Winter ’18 CIS 314 Final A Name: SID:

1. [5] Draw a 2-input XOR circuit using only AND, OR, and NOT gates:

2. [15] Describe the functionality of each Y86 pipeline stage during execution of the

andl rA, rB instruction in terms of the icode, ifun, rA, rB, valA, valB, valC, valP,

valE, valM, srcA, srcB, dstE, dstM, cnd signals (you may also use M, R, and PC):

IF:

ID:

EX:

MEM:

WB+PC:

3. [5] Briefly describe why the stall penalty for a pipelined Y86 ret instruction is 3

cycles:

4. [15] Consider the following C procedure: void swap(int *xp, int *yp) {

int t0 = *xp;

int t1 = *yp;

*xp = t1;

*yp = t0;

}

Write Y86 code that implements the above C procedure. Comment your code:

5. [15] Consider the following C function: int f(int *a, int *dest, int prod) {

*dest = prod ? 1 : 0;

for (int i = 0; i < len(a); ++i) {

if (prod) {

*dest *= a[i];

} else {

*dest += a[i];

}

}

}

Rewrite the above C function to minimize unnecessary function calls, memory

writes, and if statements:

6. [20] Consider the following Y86 code: mrmovl 0(%eax) %ecx

mrmovl 0(%ebx) %edx

addl %ecx %ecx

xorl %ecx %edx

a. (10) How many pipeline stalls are required when running the above code without

data forwarding? Why? Draw a pipeline diagram to support your answer:

b. (10) How many pipeline stalls are required when running the above code with

data forwarding? Why? Draw a pipeline diagram to support your answer:

7. (25) Consider a 32-byte direct-mapped cache with 8-byte blocks for an 8-bit

machine (256 bytes of memory):

a. (5) Write a C function unsigned char getOffset(unsigned char address) that

returns the cache offset for the specified address using bitwise operators (assuming

the cache parameters above):

b. (5) Write a C function unsigned char getSet(unsigned char address) that returns

the cache set for the specified address using bitwise operators (assuming the cache

parameters above):

c. (15) If the following addresses are accessed in sequence, which addresses will

result in cache hits and which will result in misses (assuming the cache parameters

above and that the cache is initially empty)? For each address, show the tag, set,

offset, and whether it resulted in hit or miss:

0x02

0x04

0x8

0x26

0x04

0x24