Digital Circuit Project

module Change_Controller_Stuc ( input A, input B, input C, input D, output [3:0] Y ); //Internal wires wire w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12,w13; wire An,Bn,Cn,Dn; // Gate Instatiations // Creating negatated signals // Propagation Delays(tPLH, tPHL): // Not gate = (29ns,29ns) //2 Input and gate = (38ns,38ns) // 3 Input and gate = (42ns,42ns) //2 Input or gate = (36ns,36ns) //3 input or gate = (36ns,36ns) not #(29,29) (An,A); not #(29,29) (Bn,B); not #(29,29) (Cn,C); not #(29,29) (Dn,D); // for Y[3] and #(38,38) (w1,B,Dn); and #(42,42) (w2,An,Bn,Cn); and #(42,42) (w3,An,Bn,D); or #(36,36) (Y[3],w1,w2,w3); //for Y[2] and #(42,42) (w4,Bn,Cn,Dn); and #(42,42) (w5,B,C,Dn); or #(36,36) (Y[2],A,w4,w5); // for Y[1] and #(38,38) (w6,A,Dn); and #(42,42) (w7,Bn,C,D); and #(42,42) (w8,B,Cn,D); and #(42,42) (w9,B,C,Dn); or #(36,36) (w12,w6,w7); or #(36,36) (w13,w8,w9); or #(36,36) (Y[1],w12,w13); // for Y[0] and #(38,38) (w10,Cn,D); and #(38,38) (w11,B,C); or #(36,36) (Y[0],w10,w11); endmodule