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Digital Fundamentals

CHAPTER

ELEVENTH EDITION

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

Counters

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-1 Two types of sequential logic.

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-2 A fixed-modulus binary counter as an example of a Moore state machine. The dashed line in the state diagram means the states between binary 1 and 25 are not shown for simplicity.

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-3 A variable-modulus binary counter as an example of a Mealy state machine. The red arrows in the state diagram represent the recycle paths that depend on the input number. The black dashed lines mean the interim states are not shown for simplicity.

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-4 A 2-bit asynchronous binary counter.

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-5 Timing diagram for the counter of Figure 9-4. As in previous chapters, output waveforms are shown in green.

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

TABLE 9–1 Binary state sequence for the counter in Figure 9–4.

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

TABLE 9–2 State sequence for a 3-bit binary counter.

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-6 Three-bit asynchronous binary counter and its timing diagram for one cycle.

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-7 Propagation delays in a 3-bit asynchronous (ripple-clocked) binary counter.

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-8 Four-bit asynchronous binary counter and its timing diagram.

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-9 An asynchronously clocked decade counter with asynchronous recycling.

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-10 Asynchronously clocked modulus-12 counter with asynchronous recycling.

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-11 Two configurations of the 74HC93 asynchronous counter. (The qualifying label, CTR DIV n, indicates a counter with n states.)

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-12 2-bit synchronous binary counters.

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-13 Timing details for the 2-bit synchronous counter operation (the propagation delays of both flip-flops are assumed to be equal).

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-14 Timing diagram for the counters of Figure 9-12.

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-15 A 3-bit synchronous binary counter.

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-16 Timing diagram for the counter of Figure 9-15.

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

TABLE 9–3 State sequence for a 3-bit binary counter.

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

TABLE 9–4 Summary of the analysis of the counter in Figure 9–15.

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-17 A 4-bit synchronous binary counter and timing diagram. Times where the AND gate outputs are HIGH are indicated by the shaded areas.

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-18 A synchronous BCD decade counter.

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-19 Timing diagram for the BCD decade counter (Q0 is the LSB).

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

TABLE 9–5 States of a BCD decade counter.

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-20 The 74HC163 4-bit synchronous binary counter. (The qualifying label CTR DIV 16 indicates a counter with sixteen states.)

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-21 Timing example for a 74HC163.

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

TABLE 9–6 Up/Down sequence for a 3-bit binary counter.

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-22 A basic 3-bit up/down synchronous counter.

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-23

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

TABLE 9–7

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-24 The 74HC190 up/down synchronous decade counter.

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-25 Timing example for a 74HC190.

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-26 State diagram for a 3-bit Gray code counter.

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

TABLE 9–8 Next-state table for 3-bit Gray code counter.

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

TABLE 9–9 Transition table for a J-K flip-flop.

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-27 Examples of the mapping procedure for the counter sequence represented in Table 9–8 and Table 9–9.

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-28 Karnaugh maps for present-state J and K inputs.

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-29 Three-bit Gray code counter.

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-30

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

TABLE 9–10 Next-state table.

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

TABLE 9–11 Transition table for a D flip-flop.

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-31

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-32

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-33 State diagram for a 3-bit up/down Gray code counter.

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

TABLE 9–12 Next-state table for 3-bit up/down Gray code counter.

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

TABLE 9–13 Transition table for a J-K flip-flop.

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-34 J and K maps for Table 9–12. The UP/DOWN control input, Y, is treated as a fourth variable.

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Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-35 Two cascaded asynchronous counters (all J and K inputs are HIGH).

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-36 Timing diagram for the cascaded counter configuration of Figure 9-35.

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-37 A modulus-100 counter using two cascaded decade counters.

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-38 Three cascaded decade counters forming a divide-by-1000 frequency divider with intermediate divide-by-10 and divide-by-100 outputs.

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-39

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-40 A divide-by-100 counter using two 74HC190 up/down decade counters connected for the up sequence.

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-41 A divide-by-40,000 counter using 74HC161 4-bit binary counters. Note that each of the parallel data inputs is shown in binary order (the right-most bit D0 is the LSB in each counter).

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-42 Decoding of state 6 (110).

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-43 A 3-bit counter with active-HIGH decoding of count 2 and count 7.

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-44 A basic decade (BCD) counter and decoder.

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-45 Outputs with glitches from the decoder in Figure 9-44. Glitch widths are exaggerated for illustration and are usually only a few nanoseconds wide.

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-46 The basic decade counter and decoder with strobing to eliminate glitches.

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-47 Strobed decoder outputs for the circuit of Figure 9-46.

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-48 Simplified logic diagram for a 12-hour digital clock. Logic details using specific devices are shown in Figures 9-49 and 9-50.

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-49 Logic diagram of typical divide-by-60 counter using synchronous decade counters. Note that the outputs are in binary order (the right-most bit is the LSB).

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-50 GS Logic diagram for hours counter and decoders. Note that on the counter inputs and outputs, the right-most bit is the LSB.

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-51 Functional block diagram for parking garage control.

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-52 Logic diagram for modulus-100 up/down counter for automobile parking control.

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-53 Parallel-to-serial data conversion logic.

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-54 Example of parallel-to-serial conversion timing for the circuit in Figure 9-53.

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-55 The 74HC163 4-bit synchronous counter.

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-56 Example of a failure that affects following counters in a cascaded arrangement.

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-57 Example of a failure in a cascaded counter with a truncated sequence.

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-58

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-59

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-60 One cycle of the elevator operation.

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-61 Elevator controller state diagram.

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-62 Elevator controller block diagram.

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-63 Floor counter state diagram.

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-64 Elevator controller logic diagram.

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-65

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-66

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-67

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-68

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-69

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-70

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-71

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-72

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-73

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-74

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-75

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-76

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-77

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-78

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-79

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-80

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-81

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-82

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-83

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

TABLE 9–14

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-84

Digital Fundamentals, Eleventh Edition Thomas L. Floyd

FIGURE 9-85