ASSIGNMENT #2 JUNE 2018 201CDE – ANALOG AND DIGITAL ELECTRONICS

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b. Write a VHDL description for a 4-bit shift register. The shift register is to be negative edge triggered. Sin is a serial input to the most significant bit of the shift register. Sout is a serial output from the least significant bit of the shift register. En_n is an active low enable. sreg is the 4-bit register. Write only the VHDL ENTITY and ARCHITECTURE construct.

10 Marks