From: jimc@tau-ceti.isc-br.com (Jim Cathey)
Subject: Re: UART needed (really BREAK detect)
Organization: Olivetti North America, Spokane, WA
Lines: 41

In article <alan-210493163447@17.129.12.26> alan@apple.com (Alan Mimms) writes:
>Actually detecting a BREAK is done by watching for a "character" containing
>all zero bits with the framing error resulting from its receipt.  This

True enough, but...

>means that the line stayed in the zero bit state even past the stop bit
>time slot, which basically indicates a BREAK.  There is no special way to
>detect BREAK that I have found other than this -- there's no magic signal
>generated by UARTs, etc.

Zilog SCC:
---------
	RR0[7]:  Break Detect

This is a very popular part, but it has a number of quirks, especially
in HDLC mode.

Signetics 68562 DUSCC:
---------------------
	RSR[2]:  Break Start Detect
	RSR[3]:  Break End Detect

Two of the bits in the Receiver Status Register.  You can enable an interrupt
on either of these bits going high, too.  Also, only one NULL will be put
in the FIFO per break detected.

This is simply the best serial chip I've ever worked with.  _Many_ less
quirks than the SCC, which is IMHO second-best.  (Death to 8250 devices!)

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