VHDL：Implement a complete single-cycle RISC processor using VHDL
Wuweijia
Assignment.docxDue date:
· 5th Oct, 2018
Goals:
· Use the knowledge gained from earlier labs to implement a complete single-cycle processor which can execute a real program.
· Improve understanding of pipelined processors.
· Gain experience writing technical reports.
Reports:
· Your answer should be in the form of a report (maximum 4 pages excluding appendices) explaining your design. Report should be IEEE format.
· You must clearly explain your datapath and control in your report, and comment every single line of VHDL code (include a listing of all your VHDL code as an Appendix).
· Report on the number of cycles required to execute your implementation.
· Comment on whether your result is a good one and what could be done to further improve performance.
· You should assume that the reader is familiar computer architecture in general, but not necessarily the the RISC-V instruction set or your architecture. You should also make your report standalone from this assignment question i.e. explain the problem and your approach in your report.
Individual Work
· This assignment should be your own, individual work, i.e. DO NOT simply copy the work from previous works which is similar to this.
· You can use any code from earlier labs.
· You can borrow ideas from other RISCV designs but your answer should only address the problem at hand and must be based on the code used in the labs. (Attachments provide some code from the lab of this course)
· Turnitin will be used to detect similar reports or VHDL code.
· Question A
Implement a single cycle RISCV processor which can execute the program below (your processor will need to implement a subset of the rv32im instruction set). The nprimes(int n) function uses the Sieve of Eratosthenes algorithm to compute all prime numbers up to and including n. This is called with n=100 and nprimes should return 25. Write your own testbench to verify that the results are correct.
GAS LISTING nprimes.s page 1
1 .file "nprimes.c"
2 .option nopic
3 .text
4 .align 2
5 .globl main
6 .type main, @function
7 main:
8 0000 130101FF addi sp,sp,-16
9 0004 13054006 li a0,100
10 0008 23261100 sw ra,12(sp)
11 000c 97000000 call nprimes
11 E7800000
12 0014 8320C100 lw ra,12(sp)
13 0018 13050000 li a0,0
14 001c 13010101 addi sp,sp,16
15 0020 67800000 jr ra
16
17 .size main, .-main
18 .globl nprimes
19 .type nprimes, @function
20 nprimes:
21 0024 93073000 li a5,3
22 0028 13060500 mv a2,a0
23 002c 63FCA708 bleu a0,a5,.L2
24 0030 B7050000 lui a1,%hi(testarray+8)
25 0034 37030000 lui t1,%hi(testarray)
26 0038 13858500 addi a0,a1,%lo(testarray+8)
27 003c 93062000 li a3,2
28 0040 93858500 addi a1,a1,%lo(testarray+8)
29 0044 13030300 addi t1,t1,%lo(testarray)
30 0048 93081000 li a7,1
31 004c 6F004001 j .L5
32 .L3:
33 0050 93861600 addi a3,a3,1
34 0054 B387D602 mul a5,a3,a3
35 0058 93854500 addi a1,a1,4
36 005c 6360F604 bgtu a5,a2,.L7
37 .L5:
38 0060 83A70500 lw a5,0(a1)
39 0064 E39607FE bnez a5,.L3
40 0068 13971600 slli a4,a3,1
41 006c E362E6FE bltu a2,a4,.L3
42 0070 93973600 slli a5,a3,3
43 0074 13982600 slli a6,a3,2
44 0078 B3876700 add a5,a5,t1
45 .L4:
46 007c 23A01701 sw a7,0(a5)
47 0080 3307D700 add a4,a4,a3
48 0084 B3870701 add a5,a5,a6
49 0088 E37AE6FE bgeu a2,a4,.L4
50 008c 93861600 addi a3,a3,1
51 0090 B387D602 mul a5,a3,a3
52 0094 93854500 addi a1,a1,4
53 0098 E374F6FC bleu a5,a2,.L5
54 .L7:
55 009c 13070500 mv a4,a0
56 00a0 93062000 li a3,2
GAS LISTING nprimes.s page 2
57 00a4 13050000 li a0,0
58 .L6:
59 00a8 83270700 lw a5,0(a4)
60 00ac 93861600 addi a3,a3,1
61 00b0 13074700 addi a4,a4,4
62 00b4 93B71700 seqz a5,a5
63 00b8 3305F500 add a0,a0,a5
64 00bc E376D6FE bleu a3,a2,.L6
65 00c0 67800000 ret
66 .L2:
67 00c4 93071000 li a5,1
68 00c8 63E6A700 bgtu a0,a5,.L16
69 00cc 13050000 li a0,0
70 00d0 67800000 ret
71 .L16:
72 00d4 37070000 lui a4,%hi(testarray+8)
73 00d8 13058700 addi a0,a4,%lo(testarray+8)
74 00dc 6FF01FFC j .L7
75
76 .comm testarray,262140,4
GAS LISTING nprimes.s page 3
DEFINED SYMBOLS
*ABS*:0000000000000000 nprimes.c
nprimes.s:7 .text:0000000000000000 main
nprimes.s:20 .text:0000000000000024 nprimes
*COM*:000000000003fffc testarray
nprimes.s:66 .text:00000000000000c4 .L2
nprimes.s:37 .text:0000000000000060 .L5
nprimes.s:54 .text:000000000000009c .L7
nprimes.s:32 .text:0000000000000050 .L3
nprimes.s:45 .text:000000000000007c .L4
nprimes.s:58 .text:00000000000000a8 .L6
nprimes.s:71 .text:00000000000000d4 .L16
NO UNDEFINED SYMBOLS
Question B
Modify your single cycle processor to implement a 2-stage pipelined processor where the first stage is instruction fetch, register fetch and decode, and the second stage implements the execute, memory and write back parts (your solution must use this exact arrangement). A suggested datapath is given below.
To help with this question, here is the assembly language input which you can modify if necessary to resolve RAW hazards by adding NOP instructions.
.file "nprimes.c"
.option nopic
.text
.align 2
.globl main
.type main, @function
main:
addi sp,sp,-16
li a0,100
sw ra,12(sp)
call nprimes
lw ra,12(sp)
li a0,0
addi sp,sp,16
jr ra
.size main, .-main
.globl nprimes
.type nprimes, @function
nprimes:
li a5,3
mv a2,a0
bleu a0,a5,.L2
lui a1,%hi(testarray+8)
lui t1,%hi(testarray)
addi a0,a1,%lo(testarray+8)
li a3,2
addi a1,a1,%lo(testarray+8)
addi t1,t1,%lo(testarray)
li a7,1
j .L5
.L3:
addi a3,a3,1
mul a5,a3,a3
addi a1,a1,4
bgtu a5,a2,.L7
.L5:
lw a5,0(a1)
bnez a5,.L3
slli a4,a3,1
bltu a2,a4,.L3
slli a5,a3,3
slli a6,a3,2
add a5,a5,t1
.L4:
sw a7,0(a5)
add a4,a4,a3
add a5,a5,a6
bgeu a2,a4,.L4
addi a3,a3,1
mul a5,a3,a3
addi a1,a1,4
bleu a5,a2,.L5
.L7:
mv a4,a0
li a3,2
li a0,0
.L6:
lw a5,0(a4)
addi a3,a3,1
addi a4,a4,4
seqz a5,a5
add a0,a0,a5
bleu a3,a2,.L6
ret
.L2:
li a5,1
bgtu a0,a5,.L16
li a0,0
ret
.L16:
lui a4,%hi(testarray+8)
addi a0,a4,%lo(testarray+8)
j .L7
.comm testarray,262140,4
A listing like that in Question A can be generated using the command
riscv32-unknown-elf-as -march=rv32im -mabi=ilp32 -a nprimes.s
Add at least one type of forwarding to your design.
